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| author | Suzuki K Poulose <suzuki.poulose@arm.com> | 2016-09-09 14:07:14 +0100 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2016-09-09 15:03:29 +0100 |
| commit | 072f0a633838aca13b5a8b211eb64f5c445cfd7c (patch) | |
| tree | c6e8d9c7f3b2c3fbdf7f3784e58aa33c1f72b025 /arch/arm64/kernel/hibernate-asm.S | |
| parent | c831b2ae257853ecd36ea4f7d788bf0665e4cf89 (diff) | |
| download | linux-072f0a633838aca13b5a8b211eb64f5c445cfd7c.tar.bz2 | |
arm64: Introduce raw_{d,i}cache_line_size
On systems with mismatched i/d cache min line sizes, we need to use
the smallest size possible across all CPUs. This will be done by fetching
the system wide safe value from CPU feature infrastructure.
However the some special users(e.g kexec, hibernate) would need the line
size on the CPU (rather than the system wide), when either the system
wide feature may not be accessible or it is guranteed that the caller
executes with a gurantee of no migration.
Provide another helper which will fetch cache line size on the current CPU.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: James Morse <james.morse@arm.com>
Reviewed-by: Geoff Levand <geoff@infradead.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/kernel/hibernate-asm.S')
| -rw-r--r-- | arch/arm64/kernel/hibernate-asm.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/kernel/hibernate-asm.S b/arch/arm64/kernel/hibernate-asm.S index 7734f3e7a1be..e56d848b6466 100644 --- a/arch/arm64/kernel/hibernate-asm.S +++ b/arch/arm64/kernel/hibernate-asm.S @@ -96,7 +96,7 @@ ENTRY(swsusp_arch_suspend_exit) add x1, x10, #PAGE_SIZE /* Clean the copied page to PoU - based on flush_icache_range() */ - dcache_line_size x2, x3 + raw_dcache_line_size x2, x3 sub x3, x2, #1 bic x4, x10, x3 2: dc cvau, x4 /* clean D line / unified line */ |