diff options
| author | Mark Brown <broonie@kernel.org> | 2021-05-12 16:11:31 +0100 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2021-05-26 20:04:28 +0100 |
| commit | ad4711f962e08eff8d6e9b03f9670b1af6ea9395 (patch) | |
| tree | bb1979f64369118ce873375598f7f0bfc3115b86 /arch/arm64/kernel/entry-fpsimd.S | |
| parent | c9f6890bca111a879a8af1f2390ac49cf05b11df (diff) | |
| download | linux-ad4711f962e08eff8d6e9b03f9670b1af6ea9395.tar.bz2 | |
arm64/sve: Skip flushing Z registers with 128 bit vectors
When the SVE vector length is 128 bits then there are no bits in the Z
registers which are not shared with the V registers so we can skip them
when zeroing state not shared with FPSIMD, this results in a minor
performance improvement.
Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20210512151131.27877-4-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64/kernel/entry-fpsimd.S')
| -rw-r--r-- | arch/arm64/kernel/entry-fpsimd.S | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/arm64/kernel/entry-fpsimd.S b/arch/arm64/kernel/entry-fpsimd.S index dd8382e5ce82..0a7a64753878 100644 --- a/arch/arm64/kernel/entry-fpsimd.S +++ b/arch/arm64/kernel/entry-fpsimd.S @@ -69,10 +69,18 @@ SYM_FUNC_START(sve_load_from_fpsimd_state) ret SYM_FUNC_END(sve_load_from_fpsimd_state) -/* Zero all SVE registers but the first 128-bits of each vector */ +/* + * Zero all SVE registers but the first 128-bits of each vector + * + * VQ must already be configured by caller, any further updates of VQ + * will need to ensure that the register state remains valid. + * + * x0 = VQ - 1 + */ SYM_FUNC_START(sve_flush_live) + cbz x0, 1f // A VQ-1 of 0 is 128 bits so no extra Z state sve_flush_z - sve_flush_p_ffr +1: sve_flush_p_ffr ret SYM_FUNC_END(sve_flush_live) |