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| author | Steven Price <steven.price@arm.com> | 2019-12-16 11:56:31 +0000 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2020-01-16 10:44:14 +0000 |
| commit | 275fa0ea2cf7a84450f9c0ec0d9e7ec168ed2e2d (patch) | |
| tree | 1a14bb38c7438a57a0f21266e1f81f5d0aed7186 /arch/arm64/kernel/cpu_errata.c | |
| parent | db0d46a58d34c7cd9d5ece98daf4b8afe3d770f8 (diff) | |
| download | linux-275fa0ea2cf7a84450f9c0ec0d9e7ec168ed2e2d.tar.bz2 | |
arm64: Workaround for Cortex-A55 erratum 1530923
Cortex-A55 erratum 1530923 allows TLB entries to be allocated as a
result of a speculative AT instruction. This may happen in the middle of
a guest world switch while the relevant VMSA configuration is in an
inconsistent state, leading to erroneous content being allocated into
TLBs.
The same workaround as is used for Cortex-A76 erratum 1165522
(WORKAROUND_SPECULATIVE_AT_VHE) can be used here. Note that this
mandates the use of VHE on affected parts.
Acked-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Steven Price <steven.price@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64/kernel/cpu_errata.c')
| -rw-r--r-- | arch/arm64/kernel/cpu_errata.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 0332fca5564a..0bd2867f3248 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -763,6 +763,10 @@ static const struct midr_range erratum_speculative_at_vhe_list[] = { /* Cortex A76 r0p0 to r2p0 */ MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0), #endif +#ifdef CONFIG_ARM64_ERRATUM_1530923 + /* Cortex A55 r0p0 to r2p0 */ + MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0), +#endif {}, }; #endif @@ -895,7 +899,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { #endif #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT_VHE { - .desc = "ARM erratum 1165522", + .desc = "ARM errata 1165522, 1530923", .capability = ARM64_WORKAROUND_SPECULATIVE_AT_VHE, ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_vhe_list), }, |