diff options
| author | Mark Brown <broonie@kernel.org> | 2022-09-10 17:33:52 +0100 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2022-09-16 12:38:58 +0100 |
| commit | e62a2d2610f0e6cf803027e3803c822140a2a407 (patch) | |
| tree | 5e4d2439b2b9a3c292e3fc5504e7ada616b1c17e /arch/arm64/include | |
| parent | 121a8fc088f13c64d9f3c9b3e7faa4c246e0a32c (diff) | |
| download | linux-e62a2d2610f0e6cf803027e3803c822140a2a407.tar.bz2 | |
arm64/sysreg: Convert ID_AA64FDR0_EL1 to automatic generation
Convert ID_AA64DFR0_EL1 to automatic generation as per DDI0487I.a, no
functional changes.
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220910163354.860255-5-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include')
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index aea3ec657c3f..943def0d28f2 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -190,7 +190,6 @@ #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) -#define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) @@ -698,29 +697,6 @@ #define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_48 #endif -/* id_aa64dfr0 */ -#define ID_AA64DFR0_EL1_MTPMU_SHIFT 48 -#define ID_AA64DFR0_EL1_TraceBuffer_SHIFT 44 -#define ID_AA64DFR0_EL1_TraceFilt_SHIFT 40 -#define ID_AA64DFR0_EL1_DoubleLock_SHIFT 36 -#define ID_AA64DFR0_EL1_PMSVer_SHIFT 32 -#define ID_AA64DFR0_EL1_CTX_CMPs_SHIFT 28 -#define ID_AA64DFR0_EL1_WRPs_SHIFT 20 -#define ID_AA64DFR0_EL1_BRPs_SHIFT 12 -#define ID_AA64DFR0_EL1_PMUVer_SHIFT 8 -#define ID_AA64DFR0_EL1_TraceVer_SHIFT 4 -#define ID_AA64DFR0_EL1_DebugVer_SHIFT 0 - -#define ID_AA64DFR0_EL1_PMUVer_IMP 0x1 -#define ID_AA64DFR0_EL1_PMUVer_V3P1 0x4 -#define ID_AA64DFR0_EL1_PMUVer_V3P4 0x5 -#define ID_AA64DFR0_EL1_PMUVer_V3P5 0x6 -#define ID_AA64DFR0_EL1_PMUVer_V3P7 0x7 -#define ID_AA64DFR0_EL1_PMUVer_IMP_DEF 0xf - -#define ID_AA64DFR0_EL1_PMSVer_IMP 0x1 -#define ID_AA64DFR0_EL1_PMSVer_V1P1 0x2 - #define ID_DFR0_PERFMON_SHIFT 24 #define ID_DFR0_PERFMON_8_0 0x3 |