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authorMarc Zyngier <marc.zyngier@arm.com>2014-01-15 12:50:23 +0000
committerMarc Zyngier <marc.zyngier@arm.com>2014-03-03 01:15:22 +0000
commit9d218a1fcf4c6b759d442ef702842fae92e1ea61 (patch)
tree1d94bc1753a84945ef1d31c4e162c660829c2875 /arch/arm64/include
parenta3c8bd31af260a17d626514f636849ee1cd1f63e (diff)
downloadlinux-9d218a1fcf4c6b759d442ef702842fae92e1ea61.tar.bz2
arm64: KVM: flush VM pages before letting the guest enable caches
When the guest runs with caches disabled (like in an early boot sequence, for example), all the writes are diectly going to RAM, bypassing the caches altogether. Once the MMU and caches are enabled, whatever sits in the cache becomes suddenly visible, which isn't what the guest expects. A way to avoid this potential disaster is to invalidate the cache when the MMU is being turned on. For this, we hook into the SCTLR_EL1 trapping code, and scan the stage-2 page tables, invalidating the pages/sections that have already been mapped in. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Diffstat (limited to 'arch/arm64/include')
-rw-r--r--arch/arm64/include/asm/kvm_mmu.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h
index 00c0cc8b8045..7d29847a893b 100644
--- a/arch/arm64/include/asm/kvm_mmu.h
+++ b/arch/arm64/include/asm/kvm_mmu.h
@@ -150,5 +150,7 @@ static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva,
#define kvm_virt_to_phys(x) __virt_to_phys((unsigned long)(x))
+void stage2_flush_vm(struct kvm *kvm);
+
#endif /* __ASSEMBLY__ */
#endif /* __ARM64_KVM_MMU_H__ */