diff options
| author | James Morse <james.morse@arm.com> | 2022-11-30 17:16:05 +0000 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2022-12-01 15:53:13 +0000 |
| commit | 816c8638d8c66991dd6dacd32e578293d10393f4 (patch) | |
| tree | ce46506767e84daffd918e56dee1100a7a4f8ee1 /arch/arm64/include/asm/sysreg.h | |
| parent | 3f08e378f00e1b1c14763fe225bf553b4733db67 (diff) | |
| download | linux-816c8638d8c66991dd6dacd32e578293d10393f4.tar.bz2 | |
arm64/sysreg: Standardise naming for ID_ISAR5_EL1
To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.
Ensure symbols for the ID_ISAR5_EL1 register have an _EL1 suffix.
No functional change.
Signed-off-by: James Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-7-james.morse@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64/include/asm/sysreg.h')
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 259756bad5fe..dbd376174223 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -718,12 +718,12 @@ #define ID_ISAR0_EL1_BitCount_SHIFT 4 #define ID_ISAR0_EL1_Swap_SHIFT 0 -#define ID_ISAR5_RDM_SHIFT 24 -#define ID_ISAR5_CRC32_SHIFT 16 -#define ID_ISAR5_SHA2_SHIFT 12 -#define ID_ISAR5_SHA1_SHIFT 8 -#define ID_ISAR5_AES_SHIFT 4 -#define ID_ISAR5_SEVL_SHIFT 0 +#define ID_ISAR5_EL1_RDM_SHIFT 24 +#define ID_ISAR5_EL1_CRC32_SHIFT 16 +#define ID_ISAR5_EL1_SHA2_SHIFT 12 +#define ID_ISAR5_EL1_SHA1_SHIFT 8 +#define ID_ISAR5_EL1_AES_SHIFT 4 +#define ID_ISAR5_EL1_SEVL_SHIFT 0 #define ID_ISAR6_I8MM_SHIFT 24 #define ID_ISAR6_BF16_SHIFT 20 |