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| author | James Morse <james.morse@arm.com> | 2022-11-30 17:16:00 +0000 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2022-12-01 15:53:13 +0000 |
| commit | 37622bae3db306ee472acb02fa55c48f14ddd5a1 (patch) | |
| tree | 2149046ae5931142f4821c8b18131ab7d3494dc3 /arch/arm64/include/asm/sysreg.h | |
| parent | f0c4d9fc9cc9462659728d168387191387e903cc (diff) | |
| download | linux-37622bae3db306ee472acb02fa55c48f14ddd5a1.tar.bz2 | |
arm64/sysreg: Standardise naming for ID_MMFR0_EL1
To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates. The scripts would like to follow exactly what is in the
arm-arm, which uses lower case for some of these feature names.
Ensure symbols for the ID_MMFR0_EL1 register have an _EL1 suffix,
and use lower case in feature names where the arm-arm does the same.
No functional change.
Signed-off-by: James Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-2-james.morse@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64/include/asm/sysreg.h')
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 7d301700d1a9..d757e518b08c 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -733,14 +733,14 @@ #define ID_ISAR6_DP_SHIFT 4 #define ID_ISAR6_JSCVT_SHIFT 0 -#define ID_MMFR0_INNERSHR_SHIFT 28 -#define ID_MMFR0_FCSE_SHIFT 24 -#define ID_MMFR0_AUXREG_SHIFT 20 -#define ID_MMFR0_TCM_SHIFT 16 -#define ID_MMFR0_SHARELVL_SHIFT 12 -#define ID_MMFR0_OUTERSHR_SHIFT 8 -#define ID_MMFR0_PMSA_SHIFT 4 -#define ID_MMFR0_VMSA_SHIFT 0 +#define ID_MMFR0_EL1_InnerShr_SHIFT 28 +#define ID_MMFR0_EL1_FCSE_SHIFT 24 +#define ID_MMFR0_EL1_AuxReg_SHIFT 20 +#define ID_MMFR0_EL1_TCM_SHIFT 16 +#define ID_MMFR0_EL1_ShareLvl_SHIFT 12 +#define ID_MMFR0_EL1_OuterShr_SHIFT 8 +#define ID_MMFR0_EL1_PMSA_SHIFT 4 +#define ID_MMFR0_EL1_VMSA_SHIFT 0 #define ID_MMFR4_EVT_SHIFT 28 #define ID_MMFR4_CCIDX_SHIFT 24 |