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| author | Dongjiu Geng <gengdongjiu@huawei.com> | 2018-01-15 19:39:06 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2018-01-16 15:09:47 +0000 |
| commit | 558daf693e0c7ea118dbfb9539aa5a72f34bad2e (patch) | |
| tree | 9c6f5b2b49bb6950b68356af2cfd6e283ca9f1e2 /arch/arm64/include/asm/kvm_arm.h | |
| parent | 0067df413bd9d7e9ee3a78ece1e1a93535378862 (diff) | |
| download | linux-558daf693e0c7ea118dbfb9539aa5a72f34bad2e.tar.bz2 | |
KVM: arm64: Emulate RAS error registers and set HCR_EL2's TERR & TEA
ARMv8.2 adds a new bit HCR_EL2.TEA which routes synchronous external
aborts to EL2, and adds a trap control bit HCR_EL2.TERR which traps
all Non-secure EL1&0 error record accesses to EL2.
This patch enables the two bits for the guest OS, guaranteeing that
KVM takes external aborts and traps attempts to access the physical
error registers.
ERRIDR_EL1 advertises the number of error records, we return
zero meaning we can treat all the other registers as RAZ/WI too.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
[removed specific emulation, use trap_raz_wi() directly for everything,
rephrased parts of the commit message]
Signed-off-by: James Morse <james.morse@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/kvm_arm.h')
| -rw-r--r-- | arch/arm64/include/asm/kvm_arm.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index 715d395ef45b..b0c84171e6a3 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -23,6 +23,8 @@ #include <asm/types.h> /* Hyp Configuration Register (HCR) bits */ +#define HCR_TEA (UL(1) << 37) +#define HCR_TERR (UL(1) << 36) #define HCR_E2H (UL(1) << 34) #define HCR_ID (UL(1) << 33) #define HCR_CD (UL(1) << 32) |