diff options
author | Suzuki K. Poulose <suzuki.poulose@arm.com> | 2015-01-21 12:43:11 +0000 |
---|---|---|
committer | Catalin Marinas <catalin.marinas@arm.com> | 2015-01-23 17:11:44 +0000 |
commit | 2d888f48e056119495847a269a435d5c3d9df349 (patch) | |
tree | d63ed442721b6ce1305b46105982554d340a0702 /arch/arm64/include/asm/cputype.h | |
parent | 736d474f0fafd1486f178570bc47660ee9dfdef8 (diff) | |
download | linux-2d888f48e056119495847a269a435d5c3d9df349.tar.bz2 |
arm64: Emulate SETEND for AArch32 tasks
Emulate deprecated 'setend' instruction for AArch32 bit tasks.
setend [le/be] - Sets the endianness of EL0
On systems with CPUs which support mixed endian at EL0, the hardware
support for the instruction can be enabled by setting the SCTLR_EL1.SED
bit. Like the other emulated instructions it is controlled by an entry in
/proc/sys/abi/. For more information see :
Documentation/arm64/legacy_instructions.txt
The instruction is emulated by setting/clearing the SPSR_EL1.E bit, which
will be reflected in the PSTATE.E in AArch32 context.
This patch also restores the native endianness for the execution of signal
handlers, since the process could have changed the endianness.
Note: All CPUs on the system must have mixed endian support at EL0. Once the
handler is registered, hotplugging a CPU which doesn't support mixed endian,
could lead to unexpected results/behavior in applications.
Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Punit Agrawal <punit.agrawal@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/cputype.h')
-rw-r--r-- | arch/arm64/include/asm/cputype.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 68732e9a02fb..a84ec605bed8 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -82,6 +82,7 @@ (((mmfr0) & ID_AA64MMFR0_BIGEND_MASK) >> ID_AA64MMFR0_BIGEND_SHIFT) #define SCTLR_EL1_CP15BEN (0x1 << 5) +#define SCTLR_EL1_SED (0x1 << 8) #ifndef __ASSEMBLY__ |