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| author | Suzuki K Poulose <suzuki.poulose@arm.com> | 2021-04-05 17:42:50 +0100 |
|---|---|---|
| committer | Mathieu Poirier <mathieu.poirier@linaro.org> | 2021-04-05 11:25:06 -0600 |
| commit | be96826942e8f82acef9902058d1b5e3edb83990 (patch) | |
| tree | 946aef65b34e75bf9ee68344dfc1e584a2da3d6a /arch/arm64/include/asm/barrier.h | |
| parent | 7dde51767ca5339ed33109056d92fdca05d56d8d (diff) | |
| download | linux-be96826942e8f82acef9902058d1b5e3edb83990.tar.bz2 | |
arm64: Add support for trace synchronization barrier
tsb csync synchronizes the trace operation of instructions.
The instruction is a nop when FEAT_TRF is not implemented.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20210405164307.1720226-4-suzuki.poulose@arm.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Diffstat (limited to 'arch/arm64/include/asm/barrier.h')
| -rw-r--r-- | arch/arm64/include/asm/barrier.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h index c3009b0e5239..5a8367a2b868 100644 --- a/arch/arm64/include/asm/barrier.h +++ b/arch/arm64/include/asm/barrier.h @@ -23,6 +23,7 @@ #define dsb(opt) asm volatile("dsb " #opt : : : "memory") #define psb_csync() asm volatile("hint #17" : : : "memory") +#define tsb_csync() asm volatile("hint #18" : : : "memory") #define csdb() asm volatile("hint #20" : : : "memory") #define spec_bar() asm volatile(ALTERNATIVE("dsb nsh\nisb\n", \ |