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| author | Jean-Philippe Brucker <jean-philippe.brucker@arm.com> | 2015-10-01 13:47:16 +0100 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2015-10-09 23:11:53 +0100 |
| commit | 72c971262f00185b4c6208812645c3feab4c77a3 (patch) | |
| tree | f7ad8284958cf10eaf5b009074e367aa5663b825 /arch/arm64/include/asm/arch_gicv3.h | |
| parent | f6c86a41e1dc2214363b00cc0eadb8a5401c892d (diff) | |
| download | linux-72c971262f00185b4c6208812645c3feab4c77a3.tar.bz2 | |
irqchip/gic-v3: Specialize readq and writeq accesses
On 32bit platforms, we cannot assure that an I/O ldrd or strd will be
done atomically. Besides, an hypervisor would be unable to emulate such
accesses.
In order to allow the AArch32 version of the driver to split them into
two 32bit accesses while keeping the requirement for atomic writes, this
patch specializes the IROUTER and TYPER accesses.
Since the latter is an ID register, it won't need to be read atomically,
but we still avoid future confusion by using gic_read_typer instead of a
generic gic_readq.
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/arch_gicv3.h')
| -rw-r--r-- | arch/arm64/include/asm/arch_gicv3.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h index 1aaa63551365..030cdcb46c6b 100644 --- a/arch/arm64/include/asm/arch_gicv3.h +++ b/arch/arm64/include/asm/arch_gicv3.h @@ -163,5 +163,8 @@ static inline void gic_write_sre(u32 val) isb(); } +#define gic_read_typer(c) readq_relaxed(c) +#define gic_write_irouter(v, c) writeq_relaxed(v, c) + #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARCH_GICV3_H */ |