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authorAndrew Davis <afd@ti.com>2022-10-17 14:25:29 -0500
committerNishanth Menon <nm@ti.com>2022-10-28 08:14:48 -0500
commitaa62d661247f180d0fc534e880cb6bc7fb50b4a1 (patch)
tree53959b4b9abc66ce3f838b4d299de0a96b680f1f /arch/arm64/boot
parent3e21ec289c76dbc88dc306802122214b6b053a99 (diff)
downloadlinux-aa62d661247f180d0fc534e880cb6bc7fb50b4a1.tar.bz2
arm64: dts: ti: k3-am64: MDIO pinmux should belong to the MDIO node
Although usually integrated as a child of an Ethernet controller, MDIO IP has an independent pinout. This pinout should be controlled by the MDIO node (so if it was to be disabled for instance, the pinmux state would reflect that). Move the MDIO pins pinmux to the MIDO nodes. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20221017192532.23825-8-afd@ti.com
Diffstat (limited to 'arch/arm64/boot')
-rw-r--r--arch/arm64/boot/dts/ti/k3-am642-evm.dts6
-rw-r--r--arch/arm64/boot/dts/ti/k3-am642-sk.dts6
2 files changed, 8 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index 2dec25d90240..2319ba4f5ae3 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -425,8 +425,7 @@
&cpsw3g {
pinctrl-names = "default";
- pinctrl-0 = <&mdio1_pins_default
- &rgmii1_pins_default
+ pinctrl-0 = <&rgmii1_pins_default
&rgmii2_pins_default>;
};
@@ -441,6 +440,9 @@
};
&cpsw3g_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio1_pins_default>;
+
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index 58c71608d925..c1d634647027 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -439,8 +439,7 @@
&cpsw3g {
pinctrl-names = "default";
- pinctrl-0 = <&mdio1_pins_default
- &rgmii1_pins_default
+ pinctrl-0 = <&rgmii1_pins_default
&rgmii2_pins_default>;
};
@@ -455,6 +454,9 @@
};
&cpsw3g_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio1_pins_default>;
+
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;