diff options
author | Govind Singh <govinds@codeaurora.org> | 2018-11-27 20:47:16 +0530 |
---|---|---|
committer | Andy Gross <andy.gross@linaro.org> | 2019-01-14 00:15:01 -0600 |
commit | 4bbbca1e7fea961084eaa0a58cd126f969dd3901 (patch) | |
tree | 8e762e27d176c12c750996ef99582f6ba241c59a /arch/arm64/boot/dts | |
parent | f72281126815389f63e88fb8916fdf64631d1caf (diff) | |
download | linux-4bbbca1e7fea961084eaa0a58cd126f969dd3901.tar.bz2 |
arm64: dts: qcom: qcs404: Add WCN3990 WLAN module device node
Add device node for the ath10k SNOC platform driver probe
and add resources required for WCN3990 on qcs404 soc.
Optional clock and regulator controls are not yet available in
upstream, hence add them once available.
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Govind Singh <govinds@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Diffstat (limited to 'arch/arm64/boot/dts')
-rw-r--r-- | arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 4 | ||||
-rw-r--r-- | arch/arm64/boot/dts/qcom/qcs404.dtsi | 20 |
2 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 2c2c9b00c022..ba4152318854 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -187,3 +187,7 @@ }; }; }; + +&wifi { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 9b5c16562bbe..f3d77e7ee0d2 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -346,6 +346,26 @@ status = "okay"; }; + wifi: wifi@a000000 { + compatible = "qcom,wcn3990-wifi"; + reg = <0xa000000 0x800000>; + reg-names = "membase"; + memory-region = <&wlan_msa_mem>; + interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; |