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authorGeert Uytterhoeven <geert+renesas@glider.be>2020-08-19 15:43:44 +0200
committerGeert Uytterhoeven <geert+renesas@glider.be>2020-11-10 09:29:47 +0100
commita5200e63af57d05ed8bf0ffd9a6ffefc40e01e89 (patch)
tree1af219dfe4258f69d2b0194cd4e799fe7cdea0b0 /arch/arm64/boot/dts/renesas/r8a774b1.dtsi
parent9b81018185965a306158b471db75ba0aca90ec9f (diff)
downloadlinux-a5200e63af57d05ed8bf0ffd9a6ffefc40e01e89.tar.bz2
arm64: dts: renesas: rzg2: Convert EtherAVB to explicit delay handling
Some EtherAVB variants support internal clock delay configuration, which can add larger delays than the delays that are typically supported by the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps" properties). Historically, the EtherAVB driver configured these delays based on the "rgmii-*id" PHY mode. This was wrong, as these are meant solely for the PHY, not for the MAC. Hence properties were introduced for explicit configuration of these delays. Convert the RZ/G2 DTS files from the old to the new scheme: - Add default "rx-internal-delay-ps" and "tx-internal-delay-ps" properties to the SoC .dtsi files, to be overridden by board files where needed, - Convert board files from "rgmii-*id" PHY modes to "rgmii", adding the appropriate "rx-internal-delay-ps" and/or "tx-internal-delay-ps" overrides. Notes: - RZ/G2E does not support TX internal delay handling. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200819134344.27813-8-geert+renesas@glider.be
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a774b1.dtsi')
-rw-r--r--arch/arm64/boot/dts/renesas/r8a774b1.dtsi2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index 39a1a26ffb54..83523916d360 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -989,6 +989,8 @@
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
+ rx-internal-delay-ps = <0>;
+ tx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;