diff options
author | Andreas Färber <afaerber@suse.de> | 2017-10-16 03:05:30 +0200 |
---|---|---|
committer | Andreas Färber <afaerber@suse.de> | 2019-10-29 04:57:03 +0100 |
commit | 5133636e41a28c9be7b81c85e3029536650fc997 (patch) | |
tree | acf3a6772f549768f86fa81dcb80bc637f101e88 /arch/arm64/boot/dts/realtek/rtd1296.dtsi | |
parent | 1f3295994dc572b9928df748361df3bbbf2e68f3 (diff) | |
download | linux-5133636e41a28c9be7b81c85e3029536650fc997.tar.bz2 |
arm64: dts: realtek: Add RTD1296 and Synology DS418
Add Device Trees for RTD1296 SoC and Synology DiskStation DS418.
Cc: info@synology.com
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'arch/arm64/boot/dts/realtek/rtd1296.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/realtek/rtd1296.dtsi | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/realtek/rtd1296.dtsi b/arch/arm64/boot/dts/realtek/rtd1296.dtsi new file mode 100644 index 000000000000..0f9e59cac086 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1296.dtsi @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1296 SoC + * + * Copyright (c) 2017-2019 Andreas Färber + */ + +#include "rtd129x.dtsi" + +/ { + compatible = "realtek,rtd1296"; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + next-level-cache = <&l2>; + }; + + l2: l2-cache { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; + +&arm_pmu { + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +}; |