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| author | Lars Povlsen <lars.povlsen@microchip.com> | 2020-06-15 15:32:41 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2020-07-28 11:13:48 +0200 |
| commit | e4e06a50b04296d17a4cf098a515fb452106ecf0 (patch) | |
| tree | f01c7437b53f639c36dd96aae49ef5b4783d6ba2 /arch/arm64/boot/dts/microchip/sparx5_pcb125.dts | |
| parent | 39c8378a1cdf856a3671b6431f99352b75a07248 (diff) | |
| download | linux-e4e06a50b04296d17a4cf098a515fb452106ecf0.tar.bz2 | |
arm64: dts: sparx5: Add Sparx5 SoC DPLL clock
This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock
to misc peripherals, specifically the SDHCI/eMMC controller.
Link: https://lore.kernel.org/r/20200615133242.24911-10-lars.povlsen@microchip.com
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm64/boot/dts/microchip/sparx5_pcb125.dts')
0 files changed, 0 insertions, 0 deletions