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authorLars Povlsen <lars.povlsen@microchip.com>2020-08-24 22:30:10 +0200
committerLars Povlsen <lars.povlsen@microchip.com>2020-09-16 11:39:51 +0200
commit5df50128050d01d300f28d9bca4dd89d6d24de3d (patch)
tree105b4aa8847c9208795c574af14807b94fbc2cce /arch/arm64/boot/dts/microchip/sparx5_nand.dtsi
parentba4d1c074fd7e5f5d1a5b025b510fd542fc04da5 (diff)
downloadlinux-5df50128050d01d300f28d9bca4dd89d6d24de3d.tar.bz2
arm64: dts: sparx5: Add spi-nand devices
This patch add spi-nand DT nodes to the applicable Sparx5 boards. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200824203010.2033-7-lars.povlsen@microchip.com
Diffstat (limited to 'arch/arm64/boot/dts/microchip/sparx5_nand.dtsi')
-rw-r--r--arch/arm64/boot/dts/microchip/sparx5_nand.dtsi31
1 files changed, 31 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi b/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi
new file mode 100644
index 000000000000..03f107e427d7
--- /dev/null
+++ b/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+&gpio {
+ cs14_pins: cs14-pins {
+ pins = "GPIO_44";
+ function = "si";
+ };
+};
+
+&spi0 {
+ pinctrl-0 = <&si2_pins>;
+ pinctrl-names = "default";
+ spi@e {
+ compatible = "spi-mux";
+ mux-controls = <&mux>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <14>; /* CS14 */
+ spi-flash@6 {
+ compatible = "spi-nand";
+ pinctrl-0 = <&cs14_pins>;
+ pinctrl-names = "default";
+ reg = <0x6>; /* SPI2 */
+ spi-max-frequency = <42000000>;
+ rx-sample-delay-ns = <7>; /* Tune for speed */
+ };
+ };
+};