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| author | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2012-10-12 17:59:48 +0200 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2012-11-21 17:07:49 +0100 |
| commit | 722202e10b488c14e93c428743a0e476093949e3 (patch) | |
| tree | 204a0b63402b8d21dcc95699a7ce95de666d3919 /arch/arm/plat-orion/include/plat | |
| parent | 87b54e786afda828984645a8364a228ae8ac71f4 (diff) | |
| download | linux-722202e10b488c14e93c428743a0e476093949e3.tar.bz2 | |
arm: plat-orion: Add coherency attribute when setup mbus target
Recent SoC such as Armada 370/XP came with the possibility to deal
with the I/O coherency by hardware. In this case the transaction
attribute of the window must be flagged as "Shared transaction". Once
this flag is set, then the transactions will be forced to be sent
through the coherency block, in other case transaction is driven
directly to DRAM.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Yehuda Yitschak <yehuday@marvell.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Diffstat (limited to 'arch/arm/plat-orion/include/plat')
| -rw-r--r-- | arch/arm/plat-orion/include/plat/addr-map.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h index ec63e4a627d0..b76c06569fe5 100644 --- a/arch/arm/plat-orion/include/plat/addr-map.h +++ b/arch/arm/plat-orion/include/plat/addr-map.h @@ -17,6 +17,7 @@ struct orion_addr_map_cfg { const int num_wins; /* Total number of windows */ const int remappable_wins; void __iomem *bridge_virt_base; + int hw_io_coherency; /* If NULL, the default cpu_win_can_remap will be used, using the value in remappable_wins */ |