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| author | Benjamin Gaignard <benjamin.gaignard@linaro.org> | 2019-05-21 10:17:39 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@armlinux.org.uk> | 2019-06-21 09:06:06 +0100 |
| commit | 779eb41ccb2e8cc91b63ad5172dfaadcf663f1fa (patch) | |
| tree | 92ea74f3a895ea73546c2bd85e7b5009840c7e55 /arch/arm/mm/cache-v7.S | |
| parent | e6c4375f7c9293ffa65469d16f8ebd2586cb03f2 (diff) | |
| download | linux-779eb41ccb2e8cc91b63ad5172dfaadcf663f1fa.tar.bz2 | |
ARM: 8862/1: errata: 814220-B-Cache maintenance by set/way operations can execute out of order
The v7 ARM states that all cache and branch predictor maintenance operations
that do not specify an address execute, relative to each other, in program
order. However, because of this erratum, an L2 set/way cache maintenance
operation can overtake an L1 set/way cache maintenance operation, this would
cause the data corruption.
This ERRATA affected the Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5.
This patch is the SW workaround by adding a DSB before changing cache levels as
the ARM ERRATA: ARM/MP: 814220 told in the ARM ERRATA documentation.
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'arch/arm/mm/cache-v7.S')
| -rw-r--r-- | arch/arm/mm/cache-v7.S | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index db3986708c8a..ea05d6fd53a1 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -171,6 +171,9 @@ loop2: skip: add r10, r10, #2 @ increment cache number cmp r3, r10 +#ifdef CONFIG_ARM_ERRATA_814220 + dsb +#endif bgt flush_levels finished: mov r10, #0 @ switch back to cache level 0 |