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authorCatalin Marinas <catalin.marinas@arm.com>2010-08-31 13:05:22 +0100
committerSantosh Shilimkar <santosh.shilimkar@ti.com>2010-10-26 11:39:54 +0530
commit9a6655e49fd98f3748bb80da20705448aad9ee57 (patch)
treedb5aba3a886712f54f4816137c4cea08b954f5c6 /arch/arm/mm/Kconfig
parent899611ee7d373e5eeda08e9a8632684e1ebbbf00 (diff)
downloadlinux-9a6655e49fd98f3748bb80da20705448aad9ee57.tar.bz2
ARM: Improve the L2 cache performance when PL310 is used
With this L2 cache controller, the cache maintenance by PA and sync operations are atomic and do not require a "wait" loop. This patch conditionally defines the cache_wait() function. Since L2x0 cache controllers do not work with ARMv7 CPUs, the patch automatically enables CACHE_PL310 when only CPU_V7 is defined. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/mm/Kconfig')
-rw-r--r--arch/arm/mm/Kconfig8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index a0a2928ae4dd..4414a01e1e8a 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -779,6 +779,14 @@ config CACHE_L2X0
help
This option enables the L2x0 PrimeCell.
+config CACHE_PL310
+ bool
+ depends on CACHE_L2X0
+ default y if CPU_V7 && !CPU_V6
+ help
+ This option enables optimisations for the PL310 cache
+ controller.
+
config CACHE_TAUROS2
bool "Enable the Tauros2 L2 cache controller"
depends on (ARCH_DOVE || ARCH_MMP)