diff options
author | Heiko Stuebner <heiko@sntech.de> | 2011-10-14 15:08:57 +0900 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-10-14 15:15:53 +0900 |
commit | 33ccedfd1b79a7cf649b2991e95bae415c013240 (patch) | |
tree | a5210ff54f370adb3dd852cb1a99abaa0a7e2e27 /arch/arm/mach-s3c2443/clock.c | |
parent | 866a1c8c354e613c2bf378a1cd562756d4a32e75 (diff) | |
download | linux-33ccedfd1b79a7cf649b2991e95bae415c013240.tar.bz2 |
ARM: S3C24XX: use clk_get_rate to init fclk in common_setup_clocks
Previously the fclk rate was calculated by dividing the pll through
the divider value of the armdiv. With a real armdiv clk in place it's
possible to simply read its value, which does essentially the same.
This change makes the whole fdiv_fn function pointers supplied to
s3c2443_common_init_clocks and s3c2443_common_setup_clocks
obsolete, so remove it too.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s3c2443/clock.c')
-rw-r--r-- | arch/arm/mach-s3c2443/clock.c | 11 |
1 files changed, 2 insertions, 9 deletions
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index 6fda4bf09cdd..b93cb96f57a5 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c @@ -76,13 +76,6 @@ static unsigned int armdiv[16] = { [S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16, }; -static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0) -{ - clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK; - - return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]; -} - /* hsspi * * high-speed spi clock, sourced from esysclk @@ -191,7 +184,7 @@ static struct clk *clks[] __initdata = { void __init_or_cpufreq s3c2443_setup_clocks(void) { - s3c2443_common_setup_clocks(s3c2443_get_mpll, s3c2443_fclk_div); + s3c2443_common_setup_clocks(s3c2443_get_mpll); } void __init s3c2443_init_clocks(int xtal) @@ -202,7 +195,7 @@ void __init s3c2443_init_clocks(int xtal) clk_epll.rate = s3c2443_get_epll(epllcon, xtal); clk_epll.parent = &clk_epllref.clk; - s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, s3c2443_fclk_div, + s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, armdiv, ARRAY_SIZE(armdiv), S3C2443_CLKDIV0_ARMDIV_MASK); |