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authorTero Kristo <t-kristo@ti.com>2020-04-29 17:30:01 +0300
committerTony Lindgren <tony@atomide.com>2020-05-05 11:16:06 -0700
commitf18e314a6bf1b7bdbc6f5af1d6dbda11bc2dd35b (patch)
treeee4b76632fba4929e66eac9d22cbfdcdeba68d99 /arch/arm/mach-omap2
parent189a8739cc7235f1a6da141439aa8ece72c9f4d2 (diff)
downloadlinux-f18e314a6bf1b7bdbc6f5af1d6dbda11bc2dd35b.tar.bz2
ARM: OMAP4: Make L4SEC clock domain SWSUP only
Commit c2ce5fb3f3f5 ('ARM: OMAP: DRA7xx: Make L4SEC clock domain SWSUP only') made DRA7 SoC L4SEC clock domain SWSUP only because of power state transition issues detected with HWSUP mode. Based on experimentation similar issue exists on OMAP4, so do the same change for OMAP4 also. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/clockdomains44xx_data.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index 6005c4ed3bc6..8285be7c1eab 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -214,7 +214,7 @@ static struct clockdomain l4_secure_44xx_clkdm = {
.dep_bit = OMAP4430_L4SEC_STATDEP_SHIFT,
.wkdep_srcs = l4_secure_wkup_sleep_deps,
.sleepdep_srcs = l4_secure_wkup_sleep_deps,
- .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain l4_per_44xx_clkdm = {