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authorRussell King <rmk+kernel@arm.linux.org.uk>2014-04-11 00:48:25 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2014-05-30 00:49:42 +0100
commit72ecbed1c5fe96ca5238c0c333fee3b5a858b6fb (patch)
treed88ba530692e8f5dccf7c13637cb509709225f32 /arch/arm/mach-omap2
parentdeb125abad130fc1200782048a79079f5a41af05 (diff)
downloadlinux-72ecbed1c5fe96ca5238c0c333fee3b5a858b6fb.tar.bz2
ARM: l2c: omap2: remove explicit non-secure access bits
Since we now always enable NS access to the unlock registers, this can be removed from OMAP4. Remove the NS access bit for the interrupt registers from OMAP4 as well - nothing in the kernel accesses that yet, and we can add it in core code when we have the need. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/omap4-common.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 06c6a181d6ad..df3f53195c57 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -214,17 +214,15 @@ static int __init omap_l2_cache_init(void)
/* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */
aux_ctrl = L310_AUX_CTRL_CACHE_REPLACE_RR |
- L310_AUX_CTRL_NS_LOCKDOWN |
- L310_AUX_CTRL_NS_INT_CTRL |
L2C_AUX_CTRL_SHARED_OVERRIDE |
L310_AUX_CTRL_DATA_PREFETCH |
L310_AUX_CTRL_INSTR_PREFETCH;
outer_cache.write_sec = omap4_l2c310_write_sec;
if (of_have_populated_dt())
- l2x0_of_init(aux_ctrl, 0xc19fffff);
+ l2x0_of_init(aux_ctrl, 0xcd9fffff);
else
- l2x0_init(l2cache_base, aux_ctrl, 0xc19fffff);
+ l2x0_init(l2cache_base, aux_ctrl, 0xcd9fffff);
return 0;
}