diff options
author | Paul Walmsley <paul@pwsan.com> | 2012-09-14 23:18:20 -0600 |
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committer | Paul Walmsley <paul@pwsan.com> | 2012-11-12 19:10:18 -0700 |
commit | 7a2bd1cc3926327c0393deb52e8300af75b1c9e1 (patch) | |
tree | 0e075412a394f2de3270104e2689f39cfda18a5c /arch/arm/mach-omap2/clkt2xxx_apll.c | |
parent | ed1ebc4948fdfe4c68865e5543b4a68e5a55973b (diff) | |
download | linux-7a2bd1cc3926327c0393deb52e8300af75b1c9e1.tar.bz2 |
ARM: OMAP2xxx: clock: add APLL rate recalculation functions
OMAP2420 and OMAP2430 chips each have two on-chip APLLs. When locked,
one APLL generates a 96 MHz rate; the other, a 54 MHz rate.
Previously we treated these clocks as fixed-rate clocks at the locked
rates, but this isn't quite right. The locked rate should be returned
when the APLL is locked, and a zero rate should be returned when the
APLL is stopped. This patch adds the infrastructure that will be used
by the CCF changes.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mike Turquette <mturquette@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/clkt2xxx_apll.c')
-rw-r--r-- | arch/arm/mach-omap2/clkt2xxx_apll.c | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c index 1bd15275dbf9..76a958c6e5bc 100644 --- a/arch/arm/mach-omap2/clkt2xxx_apll.c +++ b/arch/arm/mach-omap2/clkt2xxx_apll.c @@ -39,6 +39,27 @@ /* Private functions */ #ifdef CONFIG_COMMON_CLK +/** + * omap2xxx_clk_apll_locked - is the APLL locked? + * @hw: struct clk_hw * of the APLL to check + * + * If the APLL IP block referred to by @hw indicates that it's locked, + * return true; otherwise, return false. + */ +static bool omap2xxx_clk_apll_locked(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + u32 r, apll_mask; + + apll_mask = EN_APLL_LOCKED << clk->enable_bit; + + r = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); + + return ((r & apll_mask) == apll_mask) ? true : false; +} +#endif + +#ifdef CONFIG_COMMON_CLK int omap2_clk_apll96_enable(struct clk_hw *hw) #else static int _apll96_enable(struct clk *clk) @@ -110,6 +131,20 @@ static void _apll54_disable(struct clk *clk) omap2xxx_cm_apll54_disable(); } +#ifdef CONFIG_COMMON_CLK +unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw, + unsigned long parent_rate) +{ + return (omap2xxx_clk_apll_locked(hw)) ? 54000000 : 0; +} + +unsigned long omap2_clk_apll96_recalc(struct clk_hw *hw, + unsigned long parent_rate) +{ + return (omap2xxx_clk_apll_locked(hw)) ? 96000000 : 0; +} +#endif + /* Public data */ #ifdef CONFIG_COMMON_CLK const struct clk_hw_omap_ops clkhwops_apll54 = { |