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authorHaojian Zhuang <haojian.zhuang@marvell.com>2010-02-03 10:01:18 -0500
committerEric Miao <eric.y.miao@gmail.com>2010-03-02 07:40:57 +0800
commitdf0c382436df5bdd74030baafa294b75c231ec8c (patch)
treedbcf772218fcc1dde83ebb08395f1d1fa6326e51 /arch/arm/mach-mmp/mmp2.c
parentce0ac4235972cc2533e4e2095396208b59117c57 (diff)
downloadlinux-df0c382436df5bdd74030baafa294b75c231ec8c.tar.bz2
[ARM] mmp2: add handling on PMIC IRQ
Since PMIC INT pin is a special pin of CPU, the status of PMIC INT pin needs to be cleared after PMIC IRQ occured. Now append the clear operation in irq chip handler. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Diffstat (limited to 'arch/arm/mach-mmp/mmp2.c')
-rw-r--r--arch/arm/mach-mmp/mmp2.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index 0f1c441cc898..72eb9daeea99 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -37,6 +37,16 @@ static struct mfp_addr_map mmp2_addr_map[] __initdata = {
MFP_ADDR_END,
};
+void mmp2_clear_pmic_int(void)
+{
+ unsigned long mfpr_pmic, data;
+
+ mfpr_pmic = APB_VIRT_BASE + 0x1e000 + 0x2c4;
+ data = __raw_readl(mfpr_pmic);
+ __raw_writel(data | (1 << 6), mfpr_pmic);
+ __raw_writel(data, mfpr_pmic);
+}
+
static void __init mmp2_init_gpio(void)
{
int i;