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authorsedji gaouaou <sedji.gaouaou@atmel.com>2008-07-10 10:15:35 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-07-10 12:13:47 +0100
commit613526677a74c2b3d1b1696ea7334b2cf35155b3 (patch)
tree785ec10351bceedc278bba66a54c212f8e3d5f54 /arch/arm/mach-at91/clock.c
parent16074b669ea97e2bef494ec7cceb475566f763e3 (diff)
downloadlinux-613526677a74c2b3d1b1696ea7334b2cf35155b3.tar.bz2
[ARM] 5130/4: Support for the at91sam9g20
Support for the at91sam9g20 : Atmel 400Mhz ARM 926ej-s SOC. AT91sam9g20 is an evolution of the at91sam9260 with a faster clock speed. We created a new board for this device but based the chip support directly on 9260 files with little updates. Here is the chip page on Atmel wabsite: http://atmel.com/dyn/products/product_card.asp?part_id=4337 Signed-off-by: Sedji Gaouaou <sedji.gaouaou@atmel.com> Signed-off-by: Justin Waters <justin.waters@timesys.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-at91/clock.c')
-rw-r--r--arch/arm/mach-at91/clock.c19
1 files changed, 15 insertions, 4 deletions
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index e8ce8f0f3eda..464bdbbf74df 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -515,14 +515,19 @@ static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
/*
* PLL input between 1MHz and 32MHz per spec, but lower
* frequences seem necessary in some cases so allow 100K.
+ * Warning: some newer products need 2MHz min.
*/
input = main_freq / i;
+ if (cpu_is_at91sam9g20() && input < 2000000)
+ continue;
if (input < 100000)
continue;
if (input > 32000000)
continue;
mul1 = out_freq / input;
+ if (cpu_is_at91sam9g20() && mul > 63)
+ continue;
if (mul1 > 2048)
continue;
if (mul1 < 2)
@@ -582,7 +587,8 @@ int __init at91_clock_init(unsigned long main_clock)
/* report if PLLA is more than mildly overclocked */
plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
- if (plla.rate_hz > 209000000)
+ if ((!cpu_is_at91sam9g20() && plla.rate_hz > 209000000)
+ || (cpu_is_at91sam9g20() && plla.rate_hz > 800000000))
pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
/*
@@ -597,7 +603,7 @@ int __init at91_clock_init(unsigned long main_clock)
uhpck.pmc_mask = AT91RM9200_PMC_UHP;
udpck.pmc_mask = AT91RM9200_PMC_UDP;
at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
- } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263()) {
+ } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) {
uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
udpck.pmc_mask = AT91SAM926x_PMC_UDP;
} else if (cpu_is_at91cap9()) {
@@ -629,8 +635,13 @@ int __init at91_clock_init(unsigned long main_clock)
freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */
if (cpu_is_at91rm9200())
mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
- else
- mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
+ else if (cpu_is_at91sam9g20()) {
+ mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
+ freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
+ if (mckr & AT91_PMC_PDIV)
+ freq /= 2; /* processor clock division */
+ } else
+ mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
/* Register the PMC's standard clocks */
for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)