diff options
| author | Christoph Niedermaier <cniedermaier@dh-electronics.com> | 2021-07-14 23:07:02 +0200 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2021-07-23 12:02:42 +0800 |
| commit | cd35bf9dd94c3d071bb0d9eea20966e043ac1e9e (patch) | |
| tree | 1eb88b92cfd6d661c42aaf271f28b422820955f9 /arch/arm/boot | |
| parent | e0dff0fe0bb9cd9fcbd9b65e131e88a31e476539 (diff) | |
| download | linux-cd35bf9dd94c3d071bb0d9eea20966e043ac1e9e.tar.bz2 | |
ARM: dts: imx6q-dhcom: Adding Wake pin to the PCIe pinctrl
The pin CSI0_DATA_EN is reserved for PCIe Wake. Move this pin to
the SoM devicetree. Add PCIe Reset GPIO to the board devicetree.
Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: kernel@dh-electronics.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/imx6q-dhcom-pdk2.dts | 7 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx6q-dhcom-som.dtsi | 11 |
2 files changed, 14 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts index a685b1c3208f..6c5eaeefa22e 100644 --- a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts +++ b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts @@ -232,9 +232,9 @@ >; }; - pinctrl_pcie: pcie-grp { + pinctrl_pcie_reset: pcie-reset-grp { fsl,pins = < - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x120b0 >; }; }; @@ -244,8 +244,7 @@ }; &pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; + pinctrl-0 = <&pinctrl_pcie &pinctrl_pcie_reset>; reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi index d4a761b6b6aa..c5c060c6b9bf 100644 --- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi +++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi @@ -450,6 +450,12 @@ >; }; + pinctrl_pcie: pcie-grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* Wake */ + >; + }; + pinctrl_uart1: uart1-grp { fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 @@ -568,6 +574,11 @@ }; }; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; +}; + ®_arm { vin-supply = <&sw3_reg>; }; |