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| author | Maxime Ripard <maxime.ripard@bootlin.com> | 2018-11-20 22:03:28 +0100 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2018-11-28 15:14:22 +0100 |
| commit | 93870e414d511bbf91a30c052ef291fc8af18eb8 (patch) | |
| tree | 20ce29be23cd5476735e2c5500e77c5f42fd1479 /arch/arm/boot | |
| parent | 438a44ce7e51ce571f942433c6c7cb87c4c0effd (diff) | |
| download | linux-93870e414d511bbf91a30c052ef291fc8af18eb8.tar.bz2 | |
ARM: dts: sun8i: v3s: Provide default muxing for relevant controllers
The MMC0 controllers have only one muxing option in the SoC. In such a
case, we can just move the muxing into the DTSI, and remove it from
the DTS.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/sun8i-v3s.dtsi | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts index 333df90e8037..99c8cf7bb86c 100644 --- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts +++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts @@ -78,8 +78,6 @@ }; &mmc0 { - pinctrl-0 = <&mmc0_pins>; - pinctrl-names = "default"; broken-cd; bus-width = <4>; vmmc-supply = <®_vcc3v3>; diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 92fcb756a08a..21e1806ca509 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -192,6 +192,8 @@ resets = <&ccu RST_BUS_MMC0>; reset-names = "ahb"; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; |