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authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>2010-01-26 22:18:09 +0100
committerUwe Kleine-König <u.kleine-koenig@pengutronix.de>2010-06-17 11:10:03 +0200
commit63fa71872bdec70f4a82e562fc34f8d87e174774 (patch)
treecb39d230589ee6451ecb45151e5b0069e27bf02f /arch/arm/boot
parent4a8d57a54fb21f32ee17e0a61ca54c7a6f8f83da (diff)
downloadlinux-63fa71872bdec70f4a82e562fc34f8d87e174774.tar.bz2
ARM: zImage: __armv3_mpu_cache_flush: respect should-be-zero specification
Probably the register content for cache operations is "don't care" in practice, but as r1 is explicitly zeroed, use that one. Acked-by: Eric Miao <eric.miao@canonical.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/compressed/head.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 7b7d95c84641..2366613ad502 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -994,7 +994,7 @@ no_cache_id:
__armv3_mmu_cache_flush:
__armv3_mpu_cache_flush:
mov r1, #0
- mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
+ mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
mov pc, lr
/*