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authorMiquel Raynal <miquel.raynal@bootlin.com>2019-04-08 09:41:47 +0200
committerMaxime Ripard <maxime.ripard@bootlin.com>2019-04-08 10:42:29 +0200
commitdccd30ea59922d1eacff925400acd66afcd05cff (patch)
tree832fe463b03367ac40039387ae5c2507c98e791b /arch/arm/boot/dts/sun8i-a23-a33.dtsi
parent41eb0df1926aa7e8cbd621e66533d8bc35e82a26 (diff)
downloadlinux-dccd30ea59922d1eacff925400acd66afcd05cff.tar.bz2
ARM: dts: sunxi: Improve A33 NAND transfers by using DMA
In the current state, A33 NAND controllers use PIO during transfers. Throughput can be increased thanks to the use of DMA (mostly during reads, because of the ECC pipelining feature). Besides the usual addition of DMA DT properties, because the A33 NAND DMA handling is different than for older SoCs, we must also update the compatible which has recently been introduced for this purpose. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'arch/arm/boot/dts/sun8i-a23-a33.dtsi')
-rw-r--r--arch/arm/boot/dts/sun8i-a23-a33.dtsi4
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index c17bd7677ffb..f76aad0c5d4d 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -162,13 +162,15 @@
};
nfc: nand-controller@1c03000 {
- compatible = "allwinner,sun4i-a10-nand";
+ compatible = "allwinner,sun8i-a23-nand-controller";
reg = <0x01c03000 0x1000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
clock-names = "ahb", "mod";
resets = <&ccu RST_BUS_NAND>;
reset-names = "ahb";
+ dmas = <&dma 5>;
+ dma-names = "rxtx";
pinctrl-names = "default";
pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;
status = "disabled";