diff options
author | Rob Herring <robh@kernel.org> | 2017-10-13 12:54:51 -0500 |
---|---|---|
committer | Arnd Bergmann <arnd@arndb.de> | 2017-10-20 00:37:54 +0200 |
commit | 8dccafaa281aa1d240a58bbcdff338aec114a021 (patch) | |
tree | 0c45508c73bd447b350aef253119a09ae4a1e4e9 /arch/arm/boot/dts/sun7i-a20.dtsi | |
parent | 59b630878df1a02b6930077c6ce91bcfb19df761 (diff) | |
download | linux-8dccafaa281aa1d240a58bbcdff338aec114a021.tar.bz2 |
arm: dts: fix unit-address leading 0s
Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using
the following command:
perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*'
Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some
occurrences of uppercase hex.
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/boot/dts/sun7i-a20.dtsi')
-rw-r--r-- | arch/arm/boot/dts/sun7i-a20.dtsi | 228 |
1 files changed, 114 insertions, 114 deletions
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 96bee776e145..08bea4f5616d 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -181,7 +181,7 @@ #size-cells = <1>; ranges; - osc24M: clk@01c20050 { + osc24M: clk@1c20050 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-osc-clk"; reg = <0x01c20050 0x4>; @@ -205,7 +205,7 @@ clock-output-names = "osc32k"; }; - pll1: clk@01c20000 { + pll1: clk@1c20000 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-pll1-clk"; reg = <0x01c20000 0x4>; @@ -213,7 +213,7 @@ clock-output-names = "pll1"; }; - pll2: clk@01c20008 { + pll2: clk@1c20008 { #clock-cells = <1>; compatible = "allwinner,sun4i-a10-pll2-clk"; reg = <0x01c20008 0x8>; @@ -222,7 +222,7 @@ "pll2-4x", "pll2-8x"; }; - pll3: clk@01c20010 { + pll3: clk@1c20010 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-pll3-clk"; reg = <0x01c20010 0x4>; @@ -239,7 +239,7 @@ clock-output-names = "pll3-2x"; }; - pll4: clk@01c20018 { + pll4: clk@1c20018 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-pll4-clk"; reg = <0x01c20018 0x4>; @@ -247,7 +247,7 @@ clock-output-names = "pll4"; }; - pll5: clk@01c20020 { + pll5: clk@1c20020 { #clock-cells = <1>; compatible = "allwinner,sun4i-a10-pll5-clk"; reg = <0x01c20020 0x4>; @@ -255,7 +255,7 @@ clock-output-names = "pll5_ddr", "pll5_other"; }; - pll6: clk@01c20028 { + pll6: clk@1c20028 { #clock-cells = <1>; compatible = "allwinner,sun4i-a10-pll6-clk"; reg = <0x01c20028 0x4>; @@ -264,7 +264,7 @@ "pll6_div_4"; }; - pll7: clk@01c20030 { + pll7: clk@1c20030 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-pll3-clk"; reg = <0x01c20030 0x4>; @@ -281,7 +281,7 @@ clock-output-names = "pll7-2x"; }; - pll8: clk@01c20040 { + pll8: clk@1c20040 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-pll4-clk"; reg = <0x01c20040 0x4>; @@ -289,7 +289,7 @@ clock-output-names = "pll8"; }; - cpu: cpu@01c20054 { + cpu: cpu@1c20054 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-cpu-clk"; reg = <0x01c20054 0x4>; @@ -297,7 +297,7 @@ clock-output-names = "cpu"; }; - axi: axi@01c20054 { + axi: axi@1c20054 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-axi-clk"; reg = <0x01c20054 0x4>; @@ -305,7 +305,7 @@ clock-output-names = "axi"; }; - ahb: ahb@01c20054 { + ahb: ahb@1c20054 { #clock-cells = <0>; compatible = "allwinner,sun5i-a13-ahb-clk"; reg = <0x01c20054 0x4>; @@ -319,7 +319,7 @@ assigned-clock-parents = <&pll6 3>; }; - ahb_gates: clk@01c20060 { + ahb_gates: clk@1c20060 { #clock-cells = <1>; compatible = "allwinner,sun7i-a20-ahb-gates-clk"; reg = <0x01c20060 0x8>; @@ -352,7 +352,7 @@ "ahb_mali"; }; - apb0: apb0@01c20054 { + apb0: apb0@1c20054 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-apb0-clk"; reg = <0x01c20054 0x4>; @@ -360,7 +360,7 @@ clock-output-names = "apb0"; }; - apb0_gates: clk@01c20068 { + apb0_gates: clk@1c20068 { #clock-cells = <1>; compatible = "allwinner,sun7i-a20-apb0-gates-clk"; reg = <0x01c20068 0x4>; @@ -375,7 +375,7 @@ "apb0_i2s2", "apb0_keypad"; }; - apb1: clk@01c20058 { + apb1: clk@1c20058 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-apb1-clk"; reg = <0x01c20058 0x4>; @@ -383,7 +383,7 @@ clock-output-names = "apb1"; }; - apb1_gates: clk@01c2006c { + apb1_gates: clk@1c2006c { #clock-cells = <1>; compatible = "allwinner,sun7i-a20-apb1-gates-clk"; reg = <0x01c2006c 0x4>; @@ -402,7 +402,7 @@ "apb1_uart5", "apb1_uart6", "apb1_uart7"; }; - nand_clk: clk@01c20080 { + nand_clk: clk@1c20080 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20080 0x4>; @@ -410,7 +410,7 @@ clock-output-names = "nand"; }; - ms_clk: clk@01c20084 { + ms_clk: clk@1c20084 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20084 0x4>; @@ -418,7 +418,7 @@ clock-output-names = "ms"; }; - mmc0_clk: clk@01c20088 { + mmc0_clk: clk@1c20088 { #clock-cells = <1>; compatible = "allwinner,sun4i-a10-mmc-clk"; reg = <0x01c20088 0x4>; @@ -428,7 +428,7 @@ "mmc0_sample"; }; - mmc1_clk: clk@01c2008c { + mmc1_clk: clk@1c2008c { #clock-cells = <1>; compatible = "allwinner,sun4i-a10-mmc-clk"; reg = <0x01c2008c 0x4>; @@ -438,7 +438,7 @@ "mmc1_sample"; }; - mmc2_clk: clk@01c20090 { + mmc2_clk: clk@1c20090 { #clock-cells = <1>; compatible = "allwinner,sun4i-a10-mmc-clk"; reg = <0x01c20090 0x4>; @@ -448,7 +448,7 @@ "mmc2_sample"; }; - mmc3_clk: clk@01c20094 { + mmc3_clk: clk@1c20094 { #clock-cells = <1>; compatible = "allwinner,sun4i-a10-mmc-clk"; reg = <0x01c20094 0x4>; @@ -458,7 +458,7 @@ "mmc3_sample"; }; - ts_clk: clk@01c20098 { + ts_clk: clk@1c20098 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20098 0x4>; @@ -466,7 +466,7 @@ clock-output-names = "ts"; }; - ss_clk: clk@01c2009c { + ss_clk: clk@1c2009c { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2009c 0x4>; @@ -474,7 +474,7 @@ clock-output-names = "ss"; }; - spi0_clk: clk@01c200a0 { + spi0_clk: clk@1c200a0 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a0 0x4>; @@ -482,7 +482,7 @@ clock-output-names = "spi0"; }; - spi1_clk: clk@01c200a4 { + spi1_clk: clk@1c200a4 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a4 0x4>; @@ -490,7 +490,7 @@ clock-output-names = "spi1"; }; - spi2_clk: clk@01c200a8 { + spi2_clk: clk@1c200a8 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a8 0x4>; @@ -498,7 +498,7 @@ clock-output-names = "spi2"; }; - pata_clk: clk@01c200ac { + pata_clk: clk@1c200ac { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200ac 0x4>; @@ -506,7 +506,7 @@ clock-output-names = "pata"; }; - ir0_clk: clk@01c200b0 { + ir0_clk: clk@1c200b0 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200b0 0x4>; @@ -514,7 +514,7 @@ clock-output-names = "ir0"; }; - ir1_clk: clk@01c200b4 { + ir1_clk: clk@1c200b4 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200b4 0x4>; @@ -522,7 +522,7 @@ clock-output-names = "ir1"; }; - i2s0_clk: clk@01c200b8 { + i2s0_clk: clk@1c200b8 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod1-clk"; reg = <0x01c200b8 0x4>; @@ -533,7 +533,7 @@ clock-output-names = "i2s0"; }; - ac97_clk: clk@01c200bc { + ac97_clk: clk@1c200bc { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod1-clk"; reg = <0x01c200bc 0x4>; @@ -544,7 +544,7 @@ clock-output-names = "ac97"; }; - spdif_clk: clk@01c200c0 { + spdif_clk: clk@1c200c0 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod1-clk"; reg = <0x01c200c0 0x4>; @@ -555,7 +555,7 @@ clock-output-names = "spdif"; }; - keypad_clk: clk@01c200c4 { + keypad_clk: clk@1c200c4 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200c4 0x4>; @@ -563,7 +563,7 @@ clock-output-names = "keypad"; }; - usb_clk: clk@01c200cc { + usb_clk: clk@1c200cc { #clock-cells = <1>; #reset-cells = <1>; compatible = "allwinner,sun4i-a10-usb-clk"; @@ -573,7 +573,7 @@ "usb_phy"; }; - spi3_clk: clk@01c200d4 { + spi3_clk: clk@1c200d4 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200d4 0x4>; @@ -581,7 +581,7 @@ clock-output-names = "spi3"; }; - i2s1_clk: clk@01c200d8 { + i2s1_clk: clk@1c200d8 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod1-clk"; reg = <0x01c200d8 0x4>; @@ -592,7 +592,7 @@ clock-output-names = "i2s1"; }; - i2s2_clk: clk@01c200dc { + i2s2_clk: clk@1c200dc { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod1-clk"; reg = <0x01c200dc 0x4>; @@ -603,7 +603,7 @@ clock-output-names = "i2s2"; }; - dram_gates: clk@01c20100 { + dram_gates: clk@1c20100 { #clock-cells = <1>; compatible = "allwinner,sun4i-a10-dram-gates-clk"; reg = <0x01c20100 0x4>; @@ -628,7 +628,7 @@ "dram_de_mp", "dram_ace"; }; - de_be0_clk: clk@01c20104 { + de_be0_clk: clk@1c20104 { #clock-cells = <0>; #reset-cells = <0>; compatible = "allwinner,sun4i-a10-display-clk"; @@ -637,7 +637,7 @@ clock-output-names = "de-be0"; }; - de_be1_clk: clk@01c20108 { + de_be1_clk: clk@1c20108 { #clock-cells = <0>; #reset-cells = <0>; compatible = "allwinner,sun4i-a10-display-clk"; @@ -646,7 +646,7 @@ clock-output-names = "de-be1"; }; - de_fe0_clk: clk@01c2010c { + de_fe0_clk: clk@1c2010c { #clock-cells = <0>; #reset-cells = <0>; compatible = "allwinner,sun4i-a10-display-clk"; @@ -655,7 +655,7 @@ clock-output-names = "de-fe0"; }; - de_fe1_clk: clk@01c20110 { + de_fe1_clk: clk@1c20110 { #clock-cells = <0>; #reset-cells = <0>; compatible = "allwinner,sun4i-a10-display-clk"; @@ -664,7 +664,7 @@ clock-output-names = "de-fe1"; }; - tcon0_ch0_clk: clk@01c20118 { + tcon0_ch0_clk: clk@1c20118 { #clock-cells = <0>; #reset-cells = <1>; compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; @@ -674,7 +674,7 @@ }; - tcon1_ch0_clk: clk@01c2011c { + tcon1_ch0_clk: clk@1c2011c { #clock-cells = <0>; #reset-cells = <1>; compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; @@ -684,7 +684,7 @@ }; - tcon0_ch1_clk: clk@01c2012c { + tcon0_ch1_clk: clk@1c2012c { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; reg = <0x01c2012c 0x4>; @@ -693,7 +693,7 @@ }; - tcon1_ch1_clk: clk@01c20130 { + tcon1_ch1_clk: clk@1c20130 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; reg = <0x01c20130 0x4>; @@ -702,7 +702,7 @@ }; - ve_clk: clk@01c2013c { + ve_clk: clk@1c2013c { #clock-cells = <0>; #reset-cells = <0>; compatible = "allwinner,sun4i-a10-ve-clk"; @@ -711,7 +711,7 @@ clock-output-names = "ve"; }; - codec_clk: clk@01c20140 { + codec_clk: clk@1c20140 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-codec-clk"; reg = <0x01c20140 0x4>; @@ -719,7 +719,7 @@ clock-output-names = "codec"; }; - mbus_clk: clk@01c2015c { + mbus_clk: clk@1c2015c { #clock-cells = <0>; compatible = "allwinner,sun5i-a13-mbus-clk"; reg = <0x01c2015c 0x4>; @@ -750,7 +750,7 @@ clock-output-names = "gmac_int_tx"; }; - gmac_tx_clk: clk@01c20164 { + gmac_tx_clk: clk@1c20164 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-gmac-clk"; reg = <0x01c20164 0x4>; @@ -770,7 +770,7 @@ clock-output-names = "osc24M_32k"; }; - clk_out_a: clk@01c201f0 { + clk_out_a: clk@1c201f0 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-out-clk"; reg = <0x01c201f0 0x4>; @@ -778,7 +778,7 @@ clock-output-names = "clk_out_a"; }; - clk_out_b: clk@01c201f4 { + clk_out_b: clk@1c201f4 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-out-clk"; reg = <0x01c201f4 0x4>; @@ -787,20 +787,20 @@ }; }; - soc@01c00000 { + soc@1c00000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; - sram-controller@01c00000 { + sram-controller@1c00000 { compatible = "allwinner,sun4i-a10-sram-controller"; reg = <0x01c00000 0x30>; #address-cells = <1>; #size-cells = <1>; ranges; - sram_a: sram@00000000 { + sram_a: sram@0 { compatible = "mmio-sram"; reg = <0x00000000 0xc000>; #address-cells = <1>; @@ -814,14 +814,14 @@ }; }; - sram_d: sram@00010000 { + sram_d: sram@10000 { compatible = "mmio-sram"; reg = <0x00010000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x00010000 0x1000>; - otg_sram: sram-section@0000 { + otg_sram: sram-section@0 { compatible = "allwinner,sun4i-a10-sram-d"; reg = <0x0000 0x1000>; status = "disabled"; @@ -829,7 +829,7 @@ }; }; - nmi_intc: interrupt-controller@01c00030 { + nmi_intc: interrupt-controller@1c00030 { compatible = "allwinner,sun7i-a20-sc-nmi"; interrupt-controller; #interrupt-cells = <2>; @@ -837,7 +837,7 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; }; - dma: dma-controller@01c02000 { + dma: dma-controller@1c02000 { compatible = "allwinner,sun4i-a10-dma"; reg = <0x01c02000 0x1000>; interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; @@ -845,7 +845,7 @@ #dma-cells = <2>; }; - nfc: nand@01c03000 { + nfc: nand@1c03000 { compatible = "allwinner,sun4i-a10-nand"; reg = <0x01c03000 0x1000>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; @@ -858,7 +858,7 @@ #size-cells = <0>; }; - spi0: spi@01c05000 { + spi0: spi@1c05000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c05000 0x1000>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; @@ -873,7 +873,7 @@ num-cs = <4>; }; - spi1: spi@01c06000 { + spi1: spi@1c06000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c06000 0x1000>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; @@ -888,7 +888,7 @@ num-cs = <1>; }; - emac: ethernet@01c0b000 { + emac: ethernet@1c0b000 { compatible = "allwinner,sun4i-a10-emac"; reg = <0x01c0b000 0x1000>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; @@ -897,7 +897,7 @@ status = "disabled"; }; - mdio: mdio@01c0b080 { + mdio: mdio@1c0b080 { compatible = "allwinner,sun4i-a10-mdio"; reg = <0x01c0b080 0x14>; status = "disabled"; @@ -905,7 +905,7 @@ #size-cells = <0>; }; - mmc0: mmc@01c0f000 { + mmc0: mmc@1c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; clocks = <&ahb_gates 8>, @@ -922,7 +922,7 @@ #size-cells = <0>; }; - mmc1: mmc@01c10000 { + mmc1: mmc@1c10000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c10000 0x1000>; clocks = <&ahb_gates 9>, @@ -939,7 +939,7 @@ #size-cells = <0>; }; - mmc2: mmc@01c11000 { + mmc2: mmc@1c11000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c11000 0x1000>; clocks = <&ahb_gates 10>, @@ -956,7 +956,7 @@ #size-cells = <0>; }; - mmc3: mmc@01c12000 { + mmc3: mmc@1c12000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c12000 0x1000>; clocks = <&ahb_gates 11>, @@ -973,7 +973,7 @@ #size-cells = <0>; }; - usb_otg: usb@01c13000 { + usb_otg: usb@1c13000 { compatible = "allwinner,sun4i-a10-musb"; reg = <0x01c13000 0x0400>; clocks = <&ahb_gates 0>; @@ -986,7 +986,7 @@ status = "disabled"; }; - usbphy: phy@01c13400 { + usbphy: phy@1c13400 { #phy-cells = <1>; compatible = "allwinner,sun7i-a20-usb-phy"; reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; @@ -998,7 +998,7 @@ status = "disabled"; }; - ehci0: usb@01c14000 { + ehci0: usb@1c14000 { compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; reg = <0x01c14000 0x100>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; @@ -1008,7 +1008,7 @@ status = "disabled"; }; - ohci0: usb@01c14400 { + ohci0: usb@1c14400 { compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; reg = <0x01c14400 0x100>; interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; @@ -1018,7 +1018,7 @@ status = "disabled"; }; - crypto: crypto-engine@01c15000 { + crypto: crypto-engine@1c15000 { compatible = "allwinner,sun7i-a20-crypto", "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; @@ -1027,7 +1027,7 @@ clock-names = "ahb", "mod"; }; - spi2: spi@01c17000 { + spi2: spi@1c17000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c17000 0x1000>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; @@ -1042,7 +1042,7 @@ num-cs = <1>; }; - ahci: sata@01c18000 { + ahci: sata@1c18000 { compatible = "allwinner,sun4i-a10-ahci"; reg = <0x01c18000 0x1000>; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; @@ -1050,7 +1050,7 @@ status = "disabled"; }; - ehci1: usb@01c1c000 { + ehci1: usb@1c1c000 { compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; reg = <0x01c1c000 0x100>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; @@ -1060,7 +1060,7 @@ status = "disabled"; }; - ohci1: usb@01c1c400 { + ohci1: usb@1c1c400 { compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; reg = <0x01c1c400 0x100>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; @@ -1070,7 +1070,7 @@ status = "disabled"; }; - spi3: spi@01c1f000 { + spi3: spi@1c1f000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c1f000 0x1000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; @@ -1085,7 +1085,7 @@ num-cs = <1>; }; - pio: pinctrl@01c20800 { + pio: pinctrl@1c20800 { compatible = "allwinner,sun7i-a20-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; @@ -1324,7 +1324,7 @@ }; }; - timer@01c20c00 { + timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0x90>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, @@ -1336,18 +1336,18 @@ clocks = <&osc24M>; }; - wdt: watchdog@01c20c90 { + wdt: watchdog@1c20c90 { compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; }; - rtc: rtc@01c20d00 { + rtc: rtc@1c20d00 { compatible = "allwinner,sun7i-a20-rtc"; reg = <0x01c20d00 0x20>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; }; - pwm: pwm@01c20e00 { + pwm: pwm@1c20e00 { compatible = "allwinner,sun7i-a20-pwm"; reg = <0x01c20e00 0xc>; clocks = <&osc24M>; @@ -1355,7 +1355,7 @@ status = "disabled"; }; - spdif: spdif@01c21000 { + spdif: spdif@1c21000 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-spdif"; reg = <0x01c21000 0x400>; @@ -1368,7 +1368,7 @@ status = "disabled"; }; - ir0: ir@01c21800 { + ir0: ir@1c21800 { compatible = "allwinner,sun4i-a10-ir"; clocks = <&apb0_gates 6>, <&ir0_clk>; clock-names = "apb", "ir"; @@ -1377,7 +1377,7 @@ status = "disabled"; }; - ir1: ir@01c21c00 { + ir1: ir@1c21c00 { compatible = "allwinner,sun4i-a10-ir"; clocks = <&apb0_gates 7>, <&ir1_clk>; clock-names = "apb", "ir"; @@ -1386,7 +1386,7 @@ status = "disabled"; }; - i2s1: i2s@01c22000 { + i2s1: i2s@1c22000 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-i2s"; reg = <0x01c22000 0x400>; @@ -1399,7 +1399,7 @@ status = "disabled"; }; - i2s0: i2s@01c22400 { + i2s0: i2s@1c22400 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-i2s"; reg = <0x01c22400 0x400>; @@ -1412,14 +1412,14 @@ status = "disabled"; }; - lradc: lradc@01c22800 { + lradc: lradc@1c22800 { compatible = "allwinner,sun4i-a10-lradc-keys"; reg = <0x01c22800 0x100>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; - codec: codec@01c22c00 { + codec: codec@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun7i-a20-codec"; reg = <0x01c22c00 0x40>; @@ -1432,12 +1432,12 @@ status = "disabled"; }; - sid: eeprom@01c23800 { + sid: eeprom@1c23800 { compatible = "allwinner,sun7i-a20-sid"; reg = <0x01c23800 0x200>; }; - i2s2: i2s@01c24400 { + i2s2: i2s@1c24400 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-i2s"; reg = <0x01c24400 0x400>; @@ -1450,14 +1450,14 @@ status = "disabled"; }; - rtp: rtp@01c25000 { + rtp: rtp@1c25000 { compatible = "allwinner,sun5i-a13-ts"; reg = <0x01c25000 0x100>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; #thermal-sensor-cells = <0>; }; - uart0: serial@01c28000 { + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; @@ -1467,7 +1467,7 @@ status = "disabled"; }; - uart1: serial@01c28400 { + uart1: serial@1c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -1477,7 +1477,7 @@ status = "disabled"; }; - uart2: serial@01c28800 { + uart2: serial@1c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; @@ -1487,7 +1487,7 @@ status = "disabled"; }; - uart3: serial@01c28c00 { + uart3: serial@1c28c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c28c00 0x400>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; @@ -1497,7 +1497,7 @@ status = "disabled"; }; - uart4: serial@01c29000 { + uart4: serial@1c29000 { compatible = "snps,dw-apb-uart"; reg = <0x01c29000 0x400>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; @@ -1507,7 +1507,7 @@ status = "disabled"; }; - uart5: serial@01c29400 { + uart5: serial@1c29400 { compatible = "snps,dw-apb-uart"; reg = <0x01c29400 0x400>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; @@ -1517,7 +1517,7 @@ status = "disabled"; }; - uart6: serial@01c29800 { + uart6: serial@1c29800 { compatible = "snps,dw-apb-uart"; reg = <0x01c29800 0x400>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; @@ -1527,7 +1527,7 @@ status = "disabled"; }; - uart7: serial@01c29c00 { + uart7: serial@1c29c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c29c00 0x400>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; @@ -1537,7 +1537,7 @@ status = "disabled"; }; - ps20: ps2@01c2a000 { + ps20: ps2@1c2a000 { compatible = "allwinner,sun4i-a10-ps2"; reg = <0x01c2a000 0x400>; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; @@ -1545,7 +1545,7 @@ status = "disabled"; }; - ps21: ps2@01c2a400 { + ps21: ps2@1c2a400 { compatible = "allwinner,sun4i-a10-ps2"; reg = <0x01c2a400 0x400>; interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; @@ -1553,7 +1553,7 @@ status = "disabled"; }; - i2c0: i2c@01c2ac00 { + i2c0: i2c@1c2ac00 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2ac00 0x400>; @@ -1564,7 +1564,7 @@ #size-cells = <0>; }; - i2c1: i2c@01c2b000 { + i2c1: i2c@1c2b000 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2b000 0x400>; @@ -1575,7 +1575,7 @@ #size-cells = <0>; }; - i2c2: i2c@01c2b400 { + i2c2: i2c@1c2b400 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2b400 0x400>; @@ -1586,7 +1586,7 @@ #size-cells = <0>; }; - i2c3: i2c@01c2b800 { + i2c3: i2c@1c2b800 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2b800 0x400>; @@ -1597,7 +1597,7 @@ #size-cells = <0>; }; - can0: can@01c2bc00 { + can0: can@1c2bc00 { compatible = "allwinner,sun7i-a20-can", "allwinner,sun4i-a10-can"; reg = <0x01c2bc00 0x400>; @@ -1606,7 +1606,7 @@ status = "disabled"; }; - i2c4: i2c@01c2c000 { + i2c4: i2c@1c2c000 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2c000 0x400>; @@ -1617,7 +1617,7 @@ #size-cells = <0>; }; - gmac: ethernet@01c50000 { + gmac: ethernet@1c50000 { compatible = "allwinner,sun7i-a20-gmac"; reg = <0x01c50000 0x10000>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; @@ -1632,7 +1632,7 @@ #size-cells = <0>; }; - hstimer@01c60000 { + hstimer@1c60000 { compatible = "allwinner,sun7i-a20-hstimer"; reg = <0x01c60000 0x1000>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, @@ -1642,7 +1642,7 @@ clocks = <&ahb_gates 28>; }; - gic: interrupt-controller@01c81000 { + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, <0x01c82000 0x2000>, |