summaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/sh73a0.dtsi
diff options
context:
space:
mode:
authorGeert Uytterhoeven <geert+renesas@glider.be>2015-01-14 12:13:02 +0100
committerSimon Horman <horms+renesas@verge.net.au>2015-01-15 08:54:38 +0900
commit29828c87560dbdb567e759e4e6bb4ad0febfcf21 (patch)
tree78528efb51fcfea833c2958e098208f060f9da48 /arch/arm/boot/dts/sh73a0.dtsi
parentf4c6d004eac803cf90452c94ec5f3210c2d44c01 (diff)
downloadlinux-29828c87560dbdb567e759e4e6bb4ad0febfcf21.tar.bz2
ARM: shmobile: sh73a0 dtsi: Add memory-controller nodes
Add device nodes for the two SDRAM Bus State Controllers. The SBSCs are located in the A4BC0 resp. A4BC1 PM domains, which must not be powered down, else the system will crash. References to the A4BC0 and A4BC1 PM domains will be added later. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/sh73a0.dtsi')
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi16
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index d4cfb0662643..37c8a761aeab 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -42,6 +42,22 @@
<0xf0000100 0x100>;
};
+ sbsc2: memory-controller@fb400000 {
+ compatible = "renesas,sbsc-sh73a0";
+ reg = <0xfb400000 0x400>;
+ interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
+ <0 38 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "sec", "temp";
+ };
+
+ sbsc1: memory-controller@fe400000 {
+ compatible = "renesas,sbsc-sh73a0";
+ reg = <0xfe400000 0x400>;
+ interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,
+ <0 36 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "sec", "temp";
+ };
+
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>,