diff options
| author | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2021-11-26 12:35:18 +0530 |
|---|---|---|
| committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2021-11-30 21:32:43 -0600 |
| commit | 7cecfb53cad8e9f564fdf11e56502c7d8607b3a3 (patch) | |
| tree | 32a2fa9ad72f5587f2c6be9fada31db7a1b24c5f /arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts | |
| parent | e6b69813283f9babc6892c1324d2c3bd2a577d9c (diff) | |
| download | linux-7cecfb53cad8e9f564fdf11e56502c7d8607b3a3.tar.bz2 | |
ARM: dts: qcom: sdx55-fn980: Enable PCIe EP
Enable PCIe Endpoint controller on the Telit FN980 TLB board based
on Qualcomm SDX55 platform.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211126070520.28979-5-manivannan.sadhasivam@linaro.org
Diffstat (limited to 'arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts')
| -rw-r--r-- | arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts index e8b5327afbe7..01ac91738f34 100644 --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts +++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts @@ -243,6 +243,14 @@ vdda-pll-supply = <&vreg_l4e_bb_0p875>; }; +&pcie_ep { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default + &pcie_ep_wake_default>; +}; + &qpic_bam { status = "ok"; }; @@ -267,6 +275,44 @@ memory-region = <&mpss_adsp_mem>; }; +&tlmm { + pcie_ep_clkreq_default: pcie_ep_clkreq_default { + mux { + pins = "gpio56"; + function = "pcie_clkreq"; + }; + config { + pins = "gpio56"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie_ep_perst_default: pcie_ep_perst_default { + mux { + pins = "gpio57"; + function = "gpio"; + }; + config { + pins = "gpio57"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_wake_default: pcie_ep_wake_default { + mux { + pins = "gpio53"; + function = "gpio"; + }; + config { + pins = "gpio53"; + drive-strength = <2>; + bias-disable; + }; + }; +}; + &usb_hsphy { status = "okay"; vdda-pll-supply = <&vreg_l4e_bb_0p875>; |