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authorTony Lindgren <tony@atomide.com>2022-04-29 09:57:36 +0300
committerTony Lindgren <tony@atomide.com>2022-05-03 09:15:43 +0300
commit2d09a2a9d13163b9b401cc0d88c1166c6dd18b1c (patch)
tree10d85fe9290e854abe529569bd05766a273c8402 /arch/arm/boot/dts/omap3xxx-clocks.dtsi
parent89953638a83cb5b55193f720653de931fa92347c (diff)
downloadlinux-2d09a2a9d13163b9b401cc0d88c1166c6dd18b1c.tar.bz2
ARM: dts: Group omap3 CM_CLKSEL_DSS clocks
The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/omap3xxx-clocks.dtsi')
-rw-r--r--arch/arm/boot/dts/omap3xxx-clocks.dtsi42
1 files changed, 25 insertions, 17 deletions
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
index 5a192fc149c0..30f6847ef65e 100644
--- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -393,14 +393,31 @@
};
};
- dpll4_m3_ck: dpll4_m3_ck@e40 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll4_ck>;
- ti,bit-shift = <8>;
- ti,max-div = <32>;
- reg = <0x0e40>;
- ti,index-starts-at-one;
+ /* CM_CLKSEL_DSS */
+ clock@e40 {
+ compatible = "ti,clksel";
+ reg = <0xe40>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ dpll4_m3_ck: clock-dpll4-m3 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "dpll4_m3_ck";
+ clocks = <&dpll4_ck>;
+ ti,bit-shift = <8>;
+ ti,max-div = <32>;
+ ti,index-starts-at-one;
+ };
+
+ dpll4_m4_ck: clock-dpll4-m4 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "dpll4_m4_ck";
+ clocks = <&dpll4_ck>;
+ ti,max-div = <16>;
+ ti,index-starts-at-one;
+ };
};
dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
@@ -436,15 +453,6 @@
clock-div = <4>;
};
- dpll4_m4_ck: dpll4_m4_ck@e40 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll4_ck>;
- ti,max-div = <16>;
- reg = <0x0e40>;
- ti,index-starts-at-one;
- };
-
dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
#clock-cells = <0>;
compatible = "ti,fixed-factor-clock";