diff options
author | Emiliano Ingrassia <ingrassia@epigenesys.com> | 2018-01-19 02:49:17 +0100 |
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committer | Kevin Hilman <khilman@baylibre.com> | 2018-02-12 14:13:36 -0800 |
commit | 9c15795a4f96cb4f82a0e1503b46621251644bc2 (patch) | |
tree | 31e6939529f8208f48201043d722591fb3a7ce0e /arch/arm/boot/dts/meson8b-odroidc1.dts | |
parent | b96446541d8390ec22e6dc579282770453ec98a4 (diff) | |
download | linux-9c15795a4f96cb4f82a0e1503b46621251644bc2.tar.bz2 |
ARM: dts: meson8b-odroidc1: ethernet support
The Odroid-C1+ board is equipped with an RTL8211F ethernet PHY
which supports 10/100/1000 Mbps ethernet.
The PHY reset and interrupt lines are controlled by the SoC via
two GPIO lines (GPIOH_4 and GPIOH_3 respectively).
The PHY energy efficient ethernet (eee) mode is marked as broken
using "eee-broken-1000t" because, during tests, high packet losses
were experienced without it.
Signed-off-by: Emiliano Ingrassia <ingrassia@epigenesys.com>
Tested-by: Linus Lüssing <linus.luessing@c0d3.blue>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'arch/arm/boot/dts/meson8b-odroidc1.dts')
-rw-r--r-- | arch/arm/boot/dts/meson8b-odroidc1.dts | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index 9ff6ca4e20d0..d5e83051bb54 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -99,3 +99,33 @@ &usb1 { status = "okay"; }; + +ðmac { + status = "okay"; + + snps,reset-gpio = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 30000>; + + pinctrl-0 = <ð_rgmii_pins>; + pinctrl-names = "default"; + + phy-mode = "rgmii"; + phy-handle = <ð_phy>; + amlogic,tx-delay-ns = <4>; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + /* Realtek RTL8211F (0x001cc916) */ + eth_phy: ethernet-phy@0 { + reg = <0>; + eee-broken-1000t; + interrupt-parent = <&gpio_intc>; + /* GPIOH_3 */ + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; |