diff options
author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2018-09-13 22:29:16 +0200 |
---|---|---|
committer | Kevin Hilman <khilman@baylibre.com> | 2018-09-26 01:49:49 -0700 |
commit | 524d96083b66455a73ae88e40cbcb838da114416 (patch) | |
tree | e8c6d2f25c78ce74458c213385245b82013d88a1 /arch/arm/boot/dts/meson8b-odroidc1.dts | |
parent | bbedc1f1d90e33803001ceb8d9585b2f04fc10d0 (diff) | |
download | linux-524d96083b66455a73ae88e40cbcb838da114416.tar.bz2 |
ARM: dts: meson8b: odroidc1: add the CPU voltage regulator
The CPU voltage regulator is a "Monolithic Power Systems MP2161"
(according to the Odroid-C1+'s schematics). It is driven by PWM_C on
GPIODV_9.
Hardkernel's 3.10 kernel (based on the Amlogic GPL kernel sources)
defines a PWM voltage table with the following values:
- 0.86 volts = PWM register value 0x10f001b
- (more values in 0.1 volt increments)
- 1.14 volts = PWM register value 0x000012a
When using the XTAL (24MHz) as input this translates into a PWM period
of 12218ns with 0.86V using a duty cycle of 91% and 1.14V using a duty
cycle of 0%.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'arch/arm/boot/dts/meson8b-odroidc1.dts')
-rw-r--r-- | arch/arm/boot/dts/meson8b-odroidc1.dts | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index ef3177d3da3d..0557823cdd64 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -101,6 +101,25 @@ states = <3300000 0 1800000 1>; }; + + vcck: regulator-vcck { + /* Monolithic Power Systems MP2161 */ + compatible = "pwm-regulator"; + + regulator-name = "VCCK"; + regulator-min-microvolt = <860000>; + regulator-max-microvolt = <1140000>; + + pwms = <&pwm_cd 0 12218 0>; + pwm-dutycycle-range = <91 0>; + + regulator-boot-on; + regulator-always-on; + }; +}; + +&cpu0 { + cpu-supply = <&vcck>; }; ðmac { @@ -180,6 +199,14 @@ }; }; +&pwm_cd { + status = "okay"; + pinctrl-0 = <&pwm_c1_pins>; + pinctrl-names = "default"; + clocks = <&clkc CLKID_XTAL>; + clock-names = "clkin0"; +}; + &uart_AO { status = "okay"; pinctrl-0 = <&uart_ao_a_pins>; |