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author | Krzysztof Kozlowski <krzk@kernel.org> | 2019-06-21 20:02:03 +0200 |
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committer | Krzysztof Kozlowski <krzk@kernel.org> | 2019-06-24 20:03:42 +0200 |
commit | 13efd80acaa4cdb61fde52732178ff9eb4141104 (patch) | |
tree | 9c9914ac9aed3ea9aab6d135d503c5a0f1074ac3 /arch/arm/boot/dts/exynos4.dtsi | |
parent | 4a7bc07f5c04219067b328a3179bd3233fb0b7cd (diff) | |
download | linux-13efd80acaa4cdb61fde52732178ff9eb4141104.tar.bz2 |
ARM: dts: exynos: Add GPU/Mali 400 node to Exynos4
Add nodes for GPU (Mali 400) to Exynos4210 and Exynos4412. Describe the
GPU as much as possible however still few elements are missing:
1. Exynos4210 bus clock is not described in hardware manual therefore
the IP gate clock was provided,
2. Exynos4412: Not sure what to do with CLK_G3D clock responsible for
gating entire IP block (it is now being disabled as unused),
3. Regulator supplies on Trats board.
Limited testing on Odroid U3 (Exynos4412).
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/exynos4.dtsi')
-rw-r--r-- | arch/arm/boot/dts/exynos4.dtsi | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index dde27451faa8..6005cfbbed89 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -51,6 +51,42 @@ serial3 = &serial_3; }; + gpu: gpu@13000000 { + compatible = "samsung,exynos4210-mali", "arm,mali-400"; + reg = <0x13000000 0x10000>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3", + "pmu"; + /* + * CLK_G3D is not actually bus clock but a IP-level clock. + * The bus clock is not described in hardware manual. + */ + clocks = <&clock CLK_G3D>, + <&clock CLK_SCLK_G3D>; + clock-names = "bus", "core"; + power-domains = <&pd_g3d>; + status = "disabled"; + }; + pmu: pmu { compatible = "arm,cortex-a9-pmu"; interrupt-parent = <&combiner>; |