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authorRichard Schleich <rs@noreya.tech>2022-02-05 20:59:11 +0100
committerFlorian Fainelli <f.fainelli@gmail.com>2022-02-11 14:24:48 -0800
commit4c9b25077eb12534ab63dbefbab1ae6ff41c2144 (patch)
tree11ecb7e39b685fcf06f942bc70c02baca687212b /arch/arm/boot/dts/bcm2835.dtsi
parent618682b350990f8f1bee718949c4b3858711eb58 (diff)
downloadlinux-4c9b25077eb12534ab63dbefbab1ae6ff41c2144.tar.bz2
ARM: dts: bcm2835/6: Add the missing L1/L2 cache information
This patch adds the cache info for the BCM2835 and BCM2836. However, while testing I noticed that this is not implemented for ARMv6/7. Basically arch/arm/kernel/cacheinfo.c and other topology related code is missing. Since the work is already done and this has no negative effects, I am submitting it for future/documentation purposes. Signed-off-by: Richard Schleich <rs@noreya.tech> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Diffstat (limited to 'arch/arm/boot/dts/bcm2835.dtsi')
-rw-r--r--arch/arm/boot/dts/bcm2835.dtsi17
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index 0549686134ea..1c90e5a44283 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -14,6 +14,23 @@
device_type = "cpu";
compatible = "arm,arm1176jzf-s";
reg = <0x0>;
+ /* Source for d/i-cache-line-size and d/i-cache-sets
+ * https://developer.arm.com/documentation/ddi0301
+ * /h/level-one-memory-system/cache-organization?lang=en
+ *
+ * Source for d/i-cache-size
+ * https://forums.raspberrypi.com/viewtopic.php?t=98428
+ *
+ * NOTE: The BCM2835 has a L2 cache but it is dedicated to the GPU
+ * It can be shared with the CPU through fw settings,
+ * but this is not recommended.
+ */
+ d-cache-size = <0x4000>;
+ d-cache-line-size = <16>;
+ d-cache-sets = <256>; // 16KiB(size)/16(line-size)=1024ways/4-way set
+ i-cache-size = <0x4000>;
+ i-cache-line-size = <16>;
+ i-cache-sets = <256>; // 16KiB(size)/16(line-size)=1024ways/4-way set
};
};