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| author | Arnd Bergmann <arnd@arndb.de> | 2021-04-08 17:47:49 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2021-04-08 17:47:49 +0200 |
| commit | 0a8e73301d2b071a9e4ceb1901773502d50b897a (patch) | |
| tree | 7b0b6db7d93162af4a379024bd09cdeedd5ea0e6 /arch/arm/boot/dts/aspeed-g6.dtsi | |
| parent | f8e547f5285b8e4f862de90b0425a93999499e25 (diff) | |
| parent | d8d5cbc619e86b8f2167ae40d029a9d07e97b303 (diff) | |
| download | linux-0a8e73301d2b071a9e4ceb1901773502d50b897a.tar.bz2 | |
Merge tag 'memory-controller-drv-tegra-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers
Memory controller drivers for v5.13 - Tegra SoC
1. Few cleanups.
2. Add debug statistics to Tegra20 memory controller.
3. Update bindings and convert to dtschema. This update is not
backwards compatible (ABI break) however the broken part was added
recently (v5.11) and there are no users of it yet.
* tag 'memory-controller-drv-tegra-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
dt-bindings: memory: tegra20: mc: Convert to schema
dt-bindings: memory: tegra124: emc: Replace core regulator with power domain
dt-bindings: memory: tegra30: emc: Replace core regulator with power domain
dt-bindings: memory: tegra20: emc: Replace core regulator with power domain
memory: tegra: Print out info-level once per driver probe
memory: tegra20: Protect debug code with a lock
memory: tegra20: Correct comment to MC_STAT registers writes
memory: tegra20: Add debug statistics
memory: tegra: replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE
Link: https://lore.kernel.org/r/20210407161333.73013-2-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/boot/dts/aspeed-g6.dtsi')
0 files changed, 0 insertions, 0 deletions