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authorWill Deacon <will.deacon@arm.com>2011-02-28 18:15:16 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-03-09 21:40:12 +0000
commitfcbdc5fe6ebe07d502c9b652cb63376bcc4227ac (patch)
tree6472c243e21776c0fcac35d01b77924ed1c16e11 /arch/arm/Kconfig
parentf5412be599602124d2bdd49947b231dd77c0bf99 (diff)
downloadlinux-fcbdc5fe6ebe07d502c9b652cb63376bcc4227ac.tar.bz2
ARM: 6772/1: errata: possible fault MMU translations following an ASID switch
On the r2p* and r3p* versions of the Cortex-A9, a speculative memory access may cause a page table walk which starts prior to an ASID switch but completes afterwards. This can populate the micro-TLB with a stale entry which may be hit with the new ASID. This workaround places two dsb instructions in the mm switching code so that no page table walks can cross the ASID switch. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/Kconfig')
-rw-r--r--arch/arm/Kconfig11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 166efa2a19cd..ec0f6589af05 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1202,6 +1202,17 @@ config ARM_ERRATA_753970
This has the same effect as the cache sync operation: store buffer
drain and waiting for all buffers empty.
+config ARM_ERRATA_754322
+ bool "ARM errata: possible faulty MMU translations following an ASID switch"
+ depends on CPU_V7
+ help
+ This option enables the workaround for the 754322 Cortex-A9 (r2p*,
+ r3p*) erratum. A speculative memory access may cause a page table walk
+ which starts prior to an ASID switch but completes afterwards. This
+ can populate the micro-TLB with a stale entry which may be hit with
+ the new ASID. This workaround places two dsb instructions in the mm
+ switching code so that no page table walks can cross the ASID switch.
+
endmenu
source "arch/arm/common/Kconfig"