diff options
| author | Adam Buchbinder <adam.buchbinder@gmail.com> | 2016-02-23 15:24:55 -0800 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2016-03-11 14:59:53 +0530 |
| commit | 7423cc0caee7a42735ee2908f24ec69957c9bc85 (patch) | |
| tree | 7c93b6feff3331233bafd7236d8ab95e13eadfef /arch/arc/include | |
| parent | fc77dbd34c5c99bce46d40a2491937c3bcbd10af (diff) | |
| download | linux-7423cc0caee7a42735ee2908f24ec69957c9bc85.tar.bz2 | |
ARC: Fix misspellings in comments.
Signed-off-by: Adam Buchbinder <adam.buchbinder@gmail.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/include')
| -rw-r--r-- | arch/arc/include/asm/cmpxchg.h | 2 | ||||
| -rw-r--r-- | arch/arc/include/asm/entry-compact.h | 2 | ||||
| -rw-r--r-- | arch/arc/include/asm/pgtable.h | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/arch/arc/include/asm/cmpxchg.h b/arch/arc/include/asm/cmpxchg.h index af7a2db139c9..a444be67cd53 100644 --- a/arch/arc/include/asm/cmpxchg.h +++ b/arch/arc/include/asm/cmpxchg.h @@ -149,7 +149,7 @@ static inline unsigned long __xchg(unsigned long val, volatile void *ptr, * Since xchg() doesn't always do that, it would seem that following defintion * is incorrect. But here's the rationale: * SMP : Even xchg() takes the atomic_ops_lock, so OK. - * LLSC: atomic_ops_lock are not relevent at all (even if SMP, since LLSC + * LLSC: atomic_ops_lock are not relevant at all (even if SMP, since LLSC * is natively "SMP safe", no serialization required). * UP : other atomics disable IRQ, so no way a difft ctxt atomic_xchg() * could clobber them. atomic_xchg() itself would be 1 insn, so it diff --git a/arch/arc/include/asm/entry-compact.h b/arch/arc/include/asm/entry-compact.h index 1aff3be91075..1d8f57cd6057 100644 --- a/arch/arc/include/asm/entry-compact.h +++ b/arch/arc/include/asm/entry-compact.h @@ -231,7 +231,7 @@ /* free up r9 as scratchpad */ PROLOG_FREEUP_REG r9, @int\LVL\()_saved_reg - /* Which mode (user/kernel) was the system in when intr occured */ + /* Which mode (user/kernel) was the system in when intr occurred */ lr r9, [status32_l\LVL\()] SWITCH_TO_KERNEL_STK diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h index d426d4215513..ec2af62f5348 100644 --- a/arch/arc/include/asm/pgtable.h +++ b/arch/arc/include/asm/pgtable.h @@ -12,7 +12,7 @@ * - Utilise some unused free bits to confine PTE flags to 12 bits * This is a must for 4k pg-sz * - * vineetg: Mar 2011 - changes to accomodate MMU TLB Page Descriptor mods + * vineetg: Mar 2011 - changes to accommodate MMU TLB Page Descriptor mods * -TLB Locking never really existed, except for initial specs * -SILENT_xxx not needed for our port * -Per my request, MMU V3 changes the layout of some of the bits |