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| author | Vineet Gupta <vgupta@synopsys.com> | 2015-02-06 18:44:57 +0300 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2015-10-29 18:41:30 +0530 |
| commit | 5a364c2a1762e8a78721fafc93144509c0b6cb84 (patch) | |
| tree | dc74e67f8908cbfe0c5753515c8097339d55dc80 /arch/arc/include/asm/pgtable.h | |
| parent | 25d464183ca3522ae27ec1bbef5ddcbbbef65017 (diff) | |
| download | linux-5a364c2a1762e8a78721fafc93144509c0b6cb84.tar.bz2 | |
ARC: mm: PAE40 support
This is the first working implementation of 40-bit physical address
extension on ARCv2.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/include/asm/pgtable.h')
| -rw-r--r-- | arch/arc/include/asm/pgtable.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h index bd771351a1d1..57af2f05ae84 100644 --- a/arch/arc/include/asm/pgtable.h +++ b/arch/arc/include/asm/pgtable.h @@ -134,7 +134,12 @@ /* Masks for actual TLB "PD"s */ #define PTE_BITS_IN_PD0 (_PAGE_GLOBAL | _PAGE_PRESENT | _PAGE_HW_SZ) #define PTE_BITS_RWX (_PAGE_EXECUTE | _PAGE_WRITE | _PAGE_READ) + +#ifdef CONFIG_ARC_HAS_PAE40 +#define PTE_BITS_NON_RWX_IN_PD1 (0xff00000000 | PAGE_MASK | _PAGE_CACHEABLE) +#else #define PTE_BITS_NON_RWX_IN_PD1 (PAGE_MASK | _PAGE_CACHEABLE) +#endif /************************************************************************** * Mapping of vm_flags (Generic VM) to PTE flags (arch specific) @@ -272,7 +277,8 @@ static inline void pmd_set(pmd_t *pmdp, pte_t *ptep) #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) -#define pfn_pte(pfn, prot) (__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))) +#define pfn_pte(pfn, prot) (__pte(((pte_t)(pfn) << PAGE_SHIFT) | \ + pgprot_val(prot))) #define __pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) /* |