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authorHarvey Harrison <harvey.harrison@gmail.com>2009-01-06 14:56:29 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2009-01-06 18:10:27 -0800
commitdd8b72c0cc118196984f1bd23beed545d5087872 (patch)
tree25c27cc8ae7b6a936e4d6bfad8e6c317f1d3aa5d /arch/alpha
parentc6f09f0c32e5e30b91dea901f00251173fe997f4 (diff)
downloadlinux-dd8b72c0cc118196984f1bd23beed545d5087872.tar.bz2
alpha: introduce asm/swab.h
Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch/alpha')
-rw-r--r--arch/alpha/include/asm/Kbuild1
-rw-r--r--arch/alpha/include/asm/byteorder.h42
-rw-r--r--arch/alpha/include/asm/swab.h42
3 files changed, 44 insertions, 41 deletions
diff --git a/arch/alpha/include/asm/Kbuild b/arch/alpha/include/asm/Kbuild
index b7c8f188b313..4dad27360576 100644
--- a/arch/alpha/include/asm/Kbuild
+++ b/arch/alpha/include/asm/Kbuild
@@ -9,3 +9,4 @@ unifdef-y += console.h
unifdef-y += fpu.h
unifdef-y += sysinfo.h
unifdef-y += compiler.h
+unifdef-y += swab.h
diff --git a/arch/alpha/include/asm/byteorder.h b/arch/alpha/include/asm/byteorder.h
index 58e958fc7f1b..6772f3168701 100644
--- a/arch/alpha/include/asm/byteorder.h
+++ b/arch/alpha/include/asm/byteorder.h
@@ -1,47 +1,7 @@
#ifndef _ALPHA_BYTEORDER_H
#define _ALPHA_BYTEORDER_H
-#include <asm/types.h>
-#include <linux/compiler.h>
-#include <asm/compiler.h>
-
-#ifdef __GNUC__
-
-static inline __attribute_const__ __u32 __arch__swab32(__u32 x)
-{
- /*
- * Unfortunately, we can't use the 6 instruction sequence
- * on ev6 since the latency of the UNPKBW is 3, which is
- * pretty hard to hide. Just in case a future implementation
- * has a lower latency, here's the sequence (also by Mike Burrows)
- *
- * UNPKBW a0, v0 v0: 00AA00BB00CC00DD
- * SLL v0, 24, a0 a0: BB00CC00DD000000
- * BIS v0, a0, a0 a0: BBAACCBBDDCC00DD
- * EXTWL a0, 6, v0 v0: 000000000000BBAA
- * ZAP a0, 0xf3, a0 a0: 00000000DDCC0000
- * ADDL a0, v0, v0 v0: ssssssssDDCCBBAA
- */
-
- __u64 t0, t1, t2, t3;
-
- t0 = __kernel_inslh(x, 7); /* t0 : 0000000000AABBCC */
- t1 = __kernel_inswl(x, 3); /* t1 : 000000CCDD000000 */
- t1 |= t0; /* t1 : 000000CCDDAABBCC */
- t2 = t1 >> 16; /* t2 : 0000000000CCDDAA */
- t0 = t1 & 0xFF00FF00; /* t0 : 00000000DD00BB00 */
- t3 = t2 & 0x00FF00FF; /* t3 : 0000000000CC00AA */
- t1 = t0 + t3; /* t1 : ssssssssDDCCBBAA */
-
- return t1;
-}
-
-#define __arch__swab32 __arch__swab32
-
-#endif /* __GNUC__ */
-
-#define __BYTEORDER_HAS_U64__
-
+#include <asm/swab.h>
#include <linux/byteorder/little_endian.h>
#endif /* _ALPHA_BYTEORDER_H */
diff --git a/arch/alpha/include/asm/swab.h b/arch/alpha/include/asm/swab.h
new file mode 100644
index 000000000000..68e7089e02d5
--- /dev/null
+++ b/arch/alpha/include/asm/swab.h
@@ -0,0 +1,42 @@
+#ifndef _ALPHA_SWAB_H
+#define _ALPHA_SWAB_H
+
+#include <asm/types.h>
+#include <linux/compiler.h>
+#include <asm/compiler.h>
+
+#ifdef __GNUC__
+
+static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
+{
+ /*
+ * Unfortunately, we can't use the 6 instruction sequence
+ * on ev6 since the latency of the UNPKBW is 3, which is
+ * pretty hard to hide. Just in case a future implementation
+ * has a lower latency, here's the sequence (also by Mike Burrows)
+ *
+ * UNPKBW a0, v0 v0: 00AA00BB00CC00DD
+ * SLL v0, 24, a0 a0: BB00CC00DD000000
+ * BIS v0, a0, a0 a0: BBAACCBBDDCC00DD
+ * EXTWL a0, 6, v0 v0: 000000000000BBAA
+ * ZAP a0, 0xf3, a0 a0: 00000000DDCC0000
+ * ADDL a0, v0, v0 v0: ssssssssDDCCBBAA
+ */
+
+ __u64 t0, t1, t2, t3;
+
+ t0 = __kernel_inslh(x, 7); /* t0 : 0000000000AABBCC */
+ t1 = __kernel_inswl(x, 3); /* t1 : 000000CCDD000000 */
+ t1 |= t0; /* t1 : 000000CCDDAABBCC */
+ t2 = t1 >> 16; /* t2 : 0000000000CCDDAA */
+ t0 = t1 & 0xFF00FF00; /* t0 : 00000000DD00BB00 */
+ t3 = t2 & 0x00FF00FF; /* t3 : 0000000000CC00AA */
+ t1 = t0 + t3; /* t1 : ssssssssDDCCBBAA */
+
+ return t1;
+}
+#define __arch_swab32 __arch_swab32
+
+#endif /* __GNUC__ */
+
+#endif /* _ALPHA_SWAB_H */