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authorStephen Boyd <sboyd@codeaurora.org>2016-09-14 11:06:47 -0700
committerStephen Boyd <sboyd@codeaurora.org>2016-09-14 11:06:47 -0700
commit3db385ea144daea9c6e1a15f98eacafaec9ad9f1 (patch)
tree25316f2cb4f42674bcd127d3b812e17cbfe536eb /MAINTAINERS
parent7348b6ce94019548f64d54c6934d5ace3f2b50a9 (diff)
parentbe95d2c7d918b2b7b973378a1e92bdc6559c21f9 (diff)
downloadlinux-3db385ea144daea9c6e1a15f98eacafaec9ad9f1.tar.bz2
Merge tag 'clk-v4.9-samsung' of git://linuxtv.org/snawrocki/samsung into clk-next
Pull samsung clk driver updates from Sylwester Nawrocki: In addition to a few clean up and code consolidation patches this includes: - addition of sound subsystem related clocks for Exynos5410 SoC (EPLL, PDMA) and support for "samsung,exynos5410-audss-clock" compatible in the clk-exynos-audss driver, - addition of DRAM controller related clocks for exynos5420, - MAINTAINERS update adding Chanwoo Choi as the Samsung SoC clock drivers co-maintainer. * tag 'clk-v4.9-samsung' of git://linuxtv.org/snawrocki/samsung: clk: samsung: Add support for EPLL on exynos5410 clk: samsung: clk-exynos-audss: Whitespace and debug trace cleanup clk: samsung: clk-exynos-audss: Add exynos5410 compatible clk: samsung: clk-exynos-audss: controller variant handling rework clk: samsung: Use common registration function for pll2550x clk: samsung: exynos5410: Expose the peripheral DMA gate clocks clk: samsung: exynos5420: Add clocks for CMU_CDREX domain clk: samsung: exynos5410: Use samsung_cmu_register_one() to simplify code clk: samsung: exynos5260: Move struct samsung_cmu_info to init section MAINTAINERS: Add myself as Samsung SoC clock drivers co-maintainer clk: samsung: exynos5410: Add clock IDs for PDMA and EPLL clocks clk: samsung: Add clock IDs for the CMU_CDREX (DRAM Express Controller)
Diffstat (limited to 'MAINTAINERS')
-rw-r--r--MAINTAINERS3
1 files changed, 3 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 69e3ce4f693b..d695e65cb168 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10240,9 +10240,12 @@ F: drivers/nfc/s3fwrn5
SAMSUNG SOC CLOCK DRIVERS
M: Sylwester Nawrocki <s.nawrocki@samsung.com>
M: Tomasz Figa <tomasz.figa@gmail.com>
+M: Chanwoo Choi <cw00.choi@samsung.com>
S: Supported
L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
F: drivers/clk/samsung/
+F: include/dt-bindings/clock/exynos*.h
+F: Documentation/devicetree/bindings/clock/exynos*.txt
SAMSUNG SXGBE DRIVERS
M: Byungho An <bh74.an@samsung.com>