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| author | zain wang <wzz@rock-chips.com> | 2018-04-23 12:49:50 +0200 |
|---|---|---|
| committer | Andrzej Hajda <a.hajda@samsung.com> | 2018-04-24 08:34:41 +0200 |
| commit | ac0c0b611d5aef4f259625f4be44ed9e2d03b711 (patch) | |
| tree | c2964be2ca14c7b5b0a30b91da8cd0e2c66bf673 /Kconfig | |
| parent | 2a7b44c524d17d79f57d3fdb00c1c122ab720a7b (diff) | |
| download | linux-ac0c0b611d5aef4f259625f4be44ed9e2d03b711.tar.bz2 | |
drm/bridge: analogix_dp: Don't use ANALOGIX_DP_PLL_CTL to control pll
There is no register named ANALOGIX_DP_PLL_CTL in Rockchip edp phy reg
list. We should use BIT_4 in ANALOGIX_DP_PD to control the pll power
instead of ANALOGIX_DP_PLL_CTL.
Cc: Douglas Anderson <dianders@chromium.org>
Signed-off-by: zain wang <wzz@rock-chips.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180423105003.9004-15-enric.balletbo@collabora.com
Diffstat (limited to 'Kconfig')
0 files changed, 0 insertions, 0 deletions