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| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2022-07-03 01:12:21 +0200 |
|---|---|---|
| committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2022-09-20 10:06:47 +0200 |
| commit | 9fac2a193e4553d6ce093a626ef5920c362d0753 (patch) | |
| tree | e58a694a3ad3444344aa4379cee35cafba3afa99 /Documentation | |
| parent | c6d7ce0a7e0562846431dc3c7c390dde7d0c0c42 (diff) | |
| download | linux-9fac2a193e4553d6ce093a626ef5920c362d0753.tar.bz2 | |
dt-bindings: mtd: intel: lgm-nand: Fix maximum chip select value
The Intel LGM NAND IP only supports two chip selects: There's only two
CS and ADDR_SEL register sets. Fix the maximum allowed chip select value
according to the dt-bindings.
Fixes: 2f9cea8eae44f5 ("dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC")
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20220702231227.1579176-3-martin.blumenstingl@googlemail.com
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/mtd/intel,lgm-ebunand.yaml | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/mtd/intel,lgm-ebunand.yaml b/Documentation/devicetree/bindings/mtd/intel,lgm-ebunand.yaml index 763ee3e1faf3..04f26196c4c1 100644 --- a/Documentation/devicetree/bindings/mtd/intel,lgm-ebunand.yaml +++ b/Documentation/devicetree/bindings/mtd/intel,lgm-ebunand.yaml @@ -51,7 +51,7 @@ patternProperties: properties: reg: minimum: 0 - maximum: 7 + maximum: 1 nand-ecc-mode: true |