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authorBjorn Helgaas <bhelgaas@google.com>2017-09-07 13:24:07 -0500
committerBjorn Helgaas <bhelgaas@google.com>2017-09-07 13:24:07 -0500
commit68e8fa46d185894b6d1fe7f2f71a8a83b442c633 (patch)
treeb27856d10e273c1e3680d0eeacc65f49f220f87f /Documentation
parent3d499a955a30ef1bb9b2176ecb1d3a6be8e3ef9c (diff)
parent81edd471a61474de1ea772f27a3c734a68a09cc6 (diff)
downloadlinux-68e8fa46d185894b6d1fe7f2f71a8a83b442c633.tar.bz2
Merge branch 'pci/host-rockchip' into next
* pci/host-rockchip: PCI: rockchip: Fix platform_get_irq() error handling PCI: rockchip: Umap IO space if probe fails PCI: rockchip: Remove IRQ domain if probe fails PCI: rockchip: Disable vpcie0v9 if resume_noirq fails PCI: rockchip: Clean up PHY if driver probe or resume fails PCI: rockchip: Factor out rockchip_pcie_deinit_phys() PCI: rockchip: Factor out rockchip_pcie_disable_clocks() PCI: rockchip: Factor out rockchip_pcie_enable_clocks() PCI: rockchip: Factor out rockchip_pcie_setup_irq() PCI: rockchip: Use gpiod_set_value_cansleep() to allow reset via expanders PCI: rockchip: Use PCI_NUM_INTX PCI: rockchip: Explicitly request exclusive reset control dt-bindings: phy-rockchip-pcie: Convert to per-lane PHY model dt-bindings: PCI: rockchip: Convert to per-lane PHY model arm64: dts: rockchip: convert PCIe to use per-lane PHYs for rk3339 PCI: rockchip: Idle inactive PHY(s) phy: rockchip-pcie: Reconstruct driver to support per-lane PHYs PCI: rockchip: Add per-lane PHY support PCI: rockchip: Factor out rockchip_pcie_get_phys() PCI: rockchip: Control optional 12v power supply dt-bindings: PCI: rockchip: Add vpcie12v-supply for Rockchip PCIe controller
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/pci/rockchip-pcie.txt26
-rw-r--r--Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt7
2 files changed, 30 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
index 1453a734c2f5..5678be82530d 100644
--- a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
@@ -19,8 +19,6 @@ Required properties:
- "pm"
- msi-map: Maps a Requester ID to an MSI controller and associated
msi-specifier data. See ./pci-msi.txt
-- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
-- phy-names: MUST be "pcie-phy".
- interrupts: Three interrupt entries must be specified.
- interrupt-names: Must include the following names
- "sys"
@@ -42,11 +40,24 @@ Required properties:
interrupt source. The value must be 1.
- interrupt-map-mask and interrupt-map: standard PCI properties
+Required properties for legacy PHY model (deprecated):
+- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
+- phy-names: MUST be "pcie-phy".
+
+Required properties for per-lane PHY model (preferred):
+- phys: Must contain an phandle to a PHY for each entry in phy-names.
+- phy-names: Must include 4 entries for all 4 lanes even if some of
+ them won't be used for your cases. Entries are of the form "pcie-phy-N":
+ where N ranges from 0 to 3.
+ (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
+ for changing the #phy-cells of phy node to support it)
+
Optional Property:
- aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
using 24MHz OSC for RC's PHY.
- ep-gpios: contain the entry for pre-reset gpio
- num-lanes: number of lanes to use
+- vpcie12v-supply: The phandle to the 12v regulator to use for PCIe.
- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
- vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
- vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.
@@ -95,6 +106,7 @@ pcie0: pcie@f8000000 {
<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
"pm", "pclk", "aclk";
+ /* deprecated legacy PHY model */
phys = <&pcie_phy>;
phy-names = "pcie-phy";
pinctrl-names = "default";
@@ -111,3 +123,13 @@ pcie0: pcie@f8000000 {
#interrupt-cells = <1>;
};
};
+
+pcie0: pcie@f8000000 {
+ ...
+
+ /* preferred per-lane PHY model */
+ phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
+ phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
+
+ ...
+};
diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
index 0f6222a672ce..b496042f1f44 100644
--- a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
+++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
@@ -3,7 +3,6 @@ Rockchip PCIE PHY
Required properties:
- compatible: rockchip,rk3399-pcie-phy
- - #phy-cells: must be 0
- clocks: Must contain an entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must be "refclk"
@@ -11,6 +10,12 @@ Required properties:
See ../reset/reset.txt for details.
- reset-names: Must be "phy"
+Required properties for legacy PHY mode (deprecated):
+ - #phy-cells: must be 0
+
+Required properties for per-lane PHY mode (preferred):
+ - #phy-cells: must be 1
+
Example:
grf: syscon@ff770000 {