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authorLinus Torvalds <torvalds@linux-foundation.org>2022-03-26 12:46:08 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2022-03-26 12:46:08 -0700
commit5627ecb8374a00163d90bc92c33f829ac27895b2 (patch)
tree2fde352c8f5412d1ed70655c44beb8c919967257 /Documentation
parenta060c9409e25d573c23fccb8e02f098aa33f812e (diff)
parent1a22aabf20adf89cb216f566913196128766f25b (diff)
downloadlinux-5627ecb8374a00163d90bc92c33f829ac27895b2.tar.bz2
Merge branch 'i2c/for-mergewindow' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
Pull i2c updates from Wolfram Sang: - tracepoints when Linux acts as an I2C client - added support for AMD PSP - whole subsystem now uses generic_handle_irq_safe() - piix4 driver gained MMIO access enabling so far missed controllers with AMD chipsets - a bulk of device driver updates, refactorization, and fixes. * 'i2c/for-mergewindow' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (61 commits) i2c: mux: demux-pinctrl: do not deactivate a master that is not active i2c: meson: Fix wrong speed use from probe i2c: add tracepoints for I2C slave events i2c: designware: Remove code duplication i2c: cros-ec-tunnel: Fix syntax errors in comments MAINTAINERS: adjust XLP9XX I2C DRIVER after removing the devicetree binding i2c: designware: Mark dw_i2c_plat_{suspend,resume}() as __maybe_unused i2c: mediatek: Add i2c compatible for Mediatek MT8168 dt-bindings: i2c: update bindings for MT8168 SoC i2c: mt65xx: Simplify with clk-bulk i2c: i801: Drop two outdated comments i2c: xiic: Make bus names unique i2c: i801: Add support for the Process Call command i2c: i801: Drop useless masking in i801_access i2c: tegra: Add SMBus block read function i2c: designware: Use the i2c_mark_adapter_suspended/resumed() helpers i2c: designware: Lock the adapter while setting the suspended flag i2c: mediatek: remove redundant null check i2c: mediatek: modify bus speed calculation formula i2c: designware: Fix improper usage of readl ...
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt2
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt4
-rw-r--r--Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml56
-rw-r--r--Documentation/devicetree/bindings/i2c/renesas,rcar-i2c.yaml6
-rw-r--r--Documentation/firmware-guide/acpi/enumeration.rst39
-rw-r--r--Documentation/i2c/busses/i2c-i801.rst1
6 files changed, 107 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt
index 5ea216ae7084..026985b8f61a 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt
@@ -12,8 +12,10 @@ Required properties:
"mediatek,mt7622-i2c": for MediaTek MT7622
"mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623
"mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629
+ "mediatek,mt8168-i2c": for MediaTek MT8168
"mediatek,mt8173-i2c": for MediaTek MT8173
"mediatek,mt8183-i2c": for MediaTek MT8183
+ "mediatek,mt8186-i2c": for MediaTek MT8186
"mediatek,mt8192-i2c": for MediaTek MT8192
"mediatek,mt8195-i2c", "mediatek,mt8192-i2c": for MediaTek MT8195
"mediatek,mt8516-i2c", "mediatek,mt2712-i2c": for MediaTek MT8516
diff --git a/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt b/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt
index 7b9fc0c22eaf..924ad8c03464 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt
@@ -10,6 +10,7 @@ PROPERTIES:
"qcom,msm8996-cci"
"qcom,sdm845-cci"
"qcom,sm8250-cci"
+ "qcom,sm8450-cci"
- reg
Usage: required
@@ -43,7 +44,8 @@ PROPERTIES:
SUBNODES:
The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8996,
-sdm845 and sm8250), described as subdevices named "i2c-bus@0" and "i2c-bus@1".
+sdm845, sm8250 and sm8450), described as subdevices named "i2c-bus@0" and
+"i2c-bus@1".
PROPERTIES:
diff --git a/Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml b/Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml
new file mode 100644
index 000000000000..7bad4b946a34
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/microchip,corei2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MPFS I2C Controller Device Tree Bindings
+
+maintainers:
+ - Daire McNamara <daire.mcnamara@microchip.com>
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs
+ - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
+ - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-frequency:
+ description: |
+ Desired I2C bus clock frequency in Hz. As only Standard and Fast
+ modes are supported, possible values are 100000 and 400000.
+ enum: [100000, 400000]
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ i2c@2010a000 {
+ compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
+ reg = <0x2010a000 0x1000>;
+ clocks = <&clkcfg 15>;
+ interrupt-parent = <&plic>;
+ interrupts = <58>;
+ clock-frequency = <100000>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/i2c/renesas,rcar-i2c.yaml b/Documentation/devicetree/bindings/i2c/renesas,rcar-i2c.yaml
index 052aad44e781..c30107833a51 100644
--- a/Documentation/devicetree/bindings/i2c/renesas,rcar-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/renesas,rcar-i2c.yaml
@@ -49,6 +49,11 @@ properties:
- renesas,i2c-r8a779a0 # R-Car V3U
- const: renesas,rcar-gen3-i2c # R-Car Gen3 and RZ/G2
+ - items:
+ - enum:
+ - renesas,i2c-r8a779f0 # R-Car S4-8
+ - const: renesas,rcar-gen4-i2c # R-Car Gen4
+
reg:
maxItems: 1
@@ -132,6 +137,7 @@ allOf:
enum:
- renesas,rcar-gen2-i2c
- renesas,rcar-gen3-i2c
+ - renesas,rcar-gen4-i2c
then:
required:
- resets
diff --git a/Documentation/firmware-guide/acpi/enumeration.rst b/Documentation/firmware-guide/acpi/enumeration.rst
index c414646a1bb4..47fb4d6d4557 100644
--- a/Documentation/firmware-guide/acpi/enumeration.rst
+++ b/Documentation/firmware-guide/acpi/enumeration.rst
@@ -142,6 +142,45 @@ In robust cases the client unfortunately needs to call
acpi_dma_request_slave_chan_by_index() directly and therefore choose the
specific FixedDMA resource by its index.
+Named Interrupts
+================
+
+Drivers enumerated via ACPI can have names to interrupts in the ACPI table
+which can be used to get the IRQ number in the driver.
+
+The interrupt name can be listed in _DSD as 'interrupt-names'. The names
+should be listed as an array of strings which will map to the Interrupt()
+resource in the ACPI table corresponding to its index.
+
+The table below shows an example of its usage::
+
+ Device (DEV0) {
+ ...
+ Name (_CRS, ResourceTemplate() {
+ ...
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+ 0x20,
+ 0x24
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"interrupt-names",
+ Package (2) {"default", "alert"}},
+ }
+ ...
+ })
+ }
+
+The interrupt name 'default' will correspond to 0x20 in Interrupt()
+resource and 'alert' to 0x24. Note that only the Interrupt() resource
+is mapped and not GpioInt() or similar.
+
+The driver can call the function - fwnode_irq_get_byname() with the fwnode
+and interrupt name as arguments to get the corresponding IRQ number.
+
SPI serial bus support
======================
diff --git a/Documentation/i2c/busses/i2c-i801.rst b/Documentation/i2c/busses/i2c-i801.rst
index 42bbdd6e7fd8..cad59170b2ad 100644
--- a/Documentation/i2c/busses/i2c-i801.rst
+++ b/Documentation/i2c/busses/i2c-i801.rst
@@ -45,6 +45,7 @@ Supported adapters:
* Intel Jasper Lake (SOC)
* Intel Emmitsburg (PCH)
* Intel Alder Lake (PCH)
+ * Intel Raptor Lake (PCH)
Datasheets: Publicly available at the Intel website