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| author | Paolo Bonzini <pbonzini@redhat.com> | 2020-05-13 12:14:05 -0400 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2020-05-13 12:14:05 -0400 |
| commit | 4aef2ec9022b217f74d0f4c9b84081f07cc223d9 (patch) | |
| tree | edf9bb9ca1f8ab6345c156a7e87aaed28939f66c /Documentation | |
| parent | 7c67f54661fcc8d141fb11abbab1739f32e13b03 (diff) | |
| parent | 37486135d3a7b03acc7755b63627a130437f066a (diff) | |
| download | linux-4aef2ec9022b217f74d0f4c9b84081f07cc223d9.tar.bz2 | |
Merge branch 'kvm-amd-fixes' into HEAD
Diffstat (limited to 'Documentation')
532 files changed, 21078 insertions, 10324 deletions
diff --git a/Documentation/.gitignore b/Documentation/.gitignore index e74fec8693b2..d6dc7c9b8e25 100644 --- a/Documentation/.gitignore +++ b/Documentation/.gitignore @@ -1,2 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only output *.pyc diff --git a/Documentation/ABI/obsolete/sysfs-kernel-fadump_enabled b/Documentation/ABI/obsolete/sysfs-kernel-fadump_enabled new file mode 100644 index 000000000000..e9c2de8b3688 --- /dev/null +++ b/Documentation/ABI/obsolete/sysfs-kernel-fadump_enabled @@ -0,0 +1,9 @@ +This ABI is renamed and moved to a new location /sys/kernel/fadump/enabled. + +What: /sys/kernel/fadump_enabled +Date: Feb 2012 +Contact: linuxppc-dev@lists.ozlabs.org +Description: read only + Primarily used to identify whether the FADump is enabled in + the kernel or not. +User: Kdump service diff --git a/Documentation/ABI/obsolete/sysfs-kernel-fadump_registered b/Documentation/ABI/obsolete/sysfs-kernel-fadump_registered new file mode 100644 index 000000000000..0360be39c98e --- /dev/null +++ b/Documentation/ABI/obsolete/sysfs-kernel-fadump_registered @@ -0,0 +1,10 @@ +This ABI is renamed and moved to a new location /sys/kernel/fadump/registered.¬ + +What: /sys/kernel/fadump_registered +Date: Feb 2012 +Contact: linuxppc-dev@lists.ozlabs.org +Description: read/write + Helps to control the dump collect feature from userspace. + Setting 1 to this file enables the system to collect the + dump and 0 to disable it. +User: Kdump service diff --git a/Documentation/ABI/obsolete/sysfs-kernel-fadump_release_mem b/Documentation/ABI/obsolete/sysfs-kernel-fadump_release_mem new file mode 100644 index 000000000000..6ce0b129ab12 --- /dev/null +++ b/Documentation/ABI/obsolete/sysfs-kernel-fadump_release_mem @@ -0,0 +1,10 @@ +This ABI is renamed and moved to a new location /sys/kernel/fadump/release_mem.¬ + +What: /sys/kernel/fadump_release_mem +Date: Feb 2012 +Contact: linuxppc-dev@lists.ozlabs.org +Description: write only + This is a special sysfs file and only available when + the system is booted to capture the vmcore using FADump. + It is used to release the memory reserved by FADump to + save the crash dump. diff --git a/Documentation/ABI/removed/sysfs-kernel-fadump_release_opalcore b/Documentation/ABI/removed/sysfs-kernel-fadump_release_opalcore new file mode 100644 index 000000000000..a8d46cd0f4e6 --- /dev/null +++ b/Documentation/ABI/removed/sysfs-kernel-fadump_release_opalcore @@ -0,0 +1,9 @@ +This ABI is moved to /sys/firmware/opal/mpipl/release_core. + +What: /sys/kernel/fadump_release_opalcore +Date: Sep 2019 +Contact: linuxppc-dev@lists.ozlabs.org +Description: write only + The sysfs file is available when the system is booted to + collect the dump on OPAL based machine. It used to release + the memory used to collect the opalcore. diff --git a/Documentation/ABI/testing/debugfs-driver-habanalabs b/Documentation/ABI/testing/debugfs-driver-habanalabs index f0ac14b70ecb..a73601c5121e 100644 --- a/Documentation/ABI/testing/debugfs-driver-habanalabs +++ b/Documentation/ABI/testing/debugfs-driver-habanalabs @@ -43,6 +43,20 @@ Description: Allows the root user to read or write directly through the If the IOMMU is disabled, it also allows the root user to read or write from the host a device VA of a host mapped memory +What: /sys/kernel/debug/habanalabs/hl<n>/data64 +Date: Jan 2020 +KernelVersion: 5.6 +Contact: oded.gabbay@gmail.com +Description: Allows the root user to read or write 64 bit data directly + through the device's PCI bar. Writing to this file generates a + write transaction while reading from the file generates a read + transaction. This custom interface is needed (instead of using + the generic Linux user-space PCI mapping) because the DDR bar + is very small compared to the DDR memory and only the driver can + move the bar before and after the transaction. + If the IOMMU is disabled, it also allows the root user to read + or write from the host a device VA of a host mapped memory + What: /sys/kernel/debug/habanalabs/hl<n>/device Date: Jan 2019 KernelVersion: 5.1 diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti b/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti new file mode 100644 index 000000000000..9d11502b4390 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti @@ -0,0 +1,241 @@ +What: /sys/bus/coresight/devices/<cti-name>/enable +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (RW) Enable/Disable the CTI hardware. + +What: /sys/bus/coresight/devices/<cti-name>/powered +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (R) Indicate if the CTI hardware is powered. + +What: /sys/bus/coresight/devices/<cti-name>/ctmid +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (R) Display the associated CTM ID + +What: /sys/bus/coresight/devices/<cti-name>/nr_trigger_cons +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (R) Number of devices connected to triggers on this CTI + +What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/name +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (R) Name of connected device <N> + +What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/in_signals +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (R) Input trigger signals from connected device <N> + +What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/in_types +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (R) Functional types for the input trigger signals + from connected device <N> + +What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/out_signals +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (R) Output trigger signals to connected device <N> + +What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/out_types +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (R) Functional types for the output trigger signals + to connected device <N> + +What: /sys/bus/coresight/devices/<cti-name>/regs/inout_sel +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (RW) Select the index for inen and outen registers. + +What: /sys/bus/coresight/devices/<cti-name>/regs/inen +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (RW) Read or write the CTIINEN register selected by inout_sel. + +What: /sys/bus/coresight/devices/<cti-name>/regs/outen +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (RW) Read or write the CTIOUTEN register selected by inout_sel. + +What: /sys/bus/coresight/devices/<cti-name>/regs/gate +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (RW) Read or write CTIGATE register. + +What: /sys/bus/coresight/devices/<cti-name>/regs/asicctl +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (RW) Read or write ASICCTL register. + +What: /sys/bus/coresight/devices/<cti-name>/regs/intack +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (W) Write the INTACK register. + +What: /sys/bus/coresight/devices/<cti-name>/regs/appset +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (RW) Set CTIAPPSET register to activate channel. Read back to + determine current value of register. + +What: /sys/bus/coresight/devices/<cti-name>/regs/appclear +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (W) Write APPCLEAR register to deactivate channel. + +What: /sys/bus/coresight/devices/<cti-name>/regs/apppulse +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (W) Write APPPULSE to pulse a channel active for one clock + cycle. + +What: /sys/bus/coresight/devices/<cti-name>/regs/chinstatus +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (R) Read current status of channel inputs. + +What: /sys/bus/coresight/devices/<cti-name>/regs/choutstatus +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (R) read current status of channel outputs. + +What: /sys/bus/coresight/devices/<cti-name>/regs/triginstatus +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (R) read current status of input trigger signals + +What: /sys/bus/coresight/devices/<cti-name>/regs/trigoutstatus +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (R) read current status of output trigger signals. + +What: /sys/bus/coresight/devices/<cti-name>/channels/trigin_attach +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (W) Attach a CTI input trigger to a CTM channel. + +What: /sys/bus/coresight/devices/<cti-name>/channels/trigin_detach +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (W) Detach a CTI input trigger from a CTM channel. + +What: /sys/bus/coresight/devices/<cti-name>/channels/trigout_attach +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (W) Attach a CTI output trigger to a CTM channel. + +What: /sys/bus/coresight/devices/<cti-name>/channels/trigout_detach +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (W) Detach a CTI output trigger from a CTM channel. + +What: /sys/bus/coresight/devices/<cti-name>/channels/chan_gate_enable +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (RW) Enable CTIGATE for single channel (W) or list enabled + channels through the gate (R). + +What: /sys/bus/coresight/devices/<cti-name>/channels/chan_gate_disable +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (W) Disable CTIGATE for single channel. + +What: /sys/bus/coresight/devices/<cti-name>/channels/chan_set +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (W) Activate a single channel. + +What: /sys/bus/coresight/devices/<cti-name>/channels/chan_clear +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (W) Deactivate a single channel. + +What: /sys/bus/coresight/devices/<cti-name>/channels/chan_pulse +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (W) Pulse a single channel - activate for a single clock cycle. + +What: /sys/bus/coresight/devices/<cti-name>/channels/trigout_filtered +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (R) List of output triggers filtered across all connections. + +What: /sys/bus/coresight/devices/<cti-name>/channels/trig_filter_enable +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (RW) Enable or disable trigger output signal filtering. + +What: /sys/bus/coresight/devices/<cti-name>/channels/chan_inuse +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (R) show channels with at least one attached trigger signal. + +What: /sys/bus/coresight/devices/<cti-name>/channels/chan_free +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (R) show channels with no attached trigger signals. + +What: /sys/bus/coresight/devices/<cti-name>/channels/chan_xtrigs_sel +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (RW) Write channel number to select a channel to view, read to + see selected channel number. + +What: /sys/bus/coresight/devices/<cti-name>/channels/chan_xtrigs_in +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (R) Read to see input triggers connected to selected view + channel. + +What: /sys/bus/coresight/devices/<cti-name>/channels/chan_xtrigs_out +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (R) Read to see output triggers connected to selected view + channel. + +What: /sys/bus/coresight/devices/<cti-name>/channels/chan_xtrigs_reset +Date: March 2020 +KernelVersion 5.7 +Contact: Mike Leach or Mathieu Poirier +Description: (W) Clear all channel / trigger programming. diff --git a/Documentation/ABI/testing/sysfs-bus-intel_th-devices-msc b/Documentation/ABI/testing/sysfs-bus-intel_th-devices-msc index 456cb62b384c..7fd2601c2831 100644 --- a/Documentation/ABI/testing/sysfs-bus-intel_th-devices-msc +++ b/Documentation/ABI/testing/sysfs-bus-intel_th-devices-msc @@ -40,3 +40,11 @@ Description: (RW) Trigger window switch for the MSC's buffer, in triggering a window switch for the buffer. Returns an error in any other operating mode or attempts to write something other than "1". +What: /sys/bus/intel_th/devices/<intel_th_id>-msc<msc-id>/stop_on_full +Date: March 2020 +KernelVersion: 5.7 +Contact: Alexander Shishkin <alexander.shishkin@linux.intel.com> +Description: (RW) Configure whether trace stops when the last available window + becomes full (1/y/Y) or wraps around and continues until the next + window becomes available again (0/n/N). + diff --git a/Documentation/ABI/testing/sysfs-driver-jz4780-efuse b/Documentation/ABI/testing/sysfs-driver-jz4780-efuse new file mode 100644 index 000000000000..bb6f5d6ceea0 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-jz4780-efuse @@ -0,0 +1,16 @@ +What: /sys/devices/*/<our-device>/nvmem +Date: December 2017 +Contact: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com> +Description: read-only access to the efuse on the Ingenic JZ4780 SoC + The SoC has a one time programmable 8K efuse that is + split into segments. The driver supports read only. + The segments are + 0x000 64 bit Random Number + 0x008 128 bit Ingenic Chip ID + 0x018 128 bit Customer ID + 0x028 3520 bit Reserved + 0x1E0 8 bit Protect Segment + 0x1E1 2296 bit HDMI Key + 0x300 2048 bit Security boot key +Users: any user space application which wants to read the Chip + and Customer ID diff --git a/Documentation/ABI/testing/sysfs-firmware-opal-sensor-groups b/Documentation/ABI/testing/sysfs-firmware-opal-sensor-groups new file mode 100644 index 000000000000..3a2dfe542e8c --- /dev/null +++ b/Documentation/ABI/testing/sysfs-firmware-opal-sensor-groups @@ -0,0 +1,21 @@ +What: /sys/firmware/opal/sensor_groups +Date: August 2017 +Contact: Linux for PowerPC mailing list <linuxppc-dev@ozlabs.org> +Description: Sensor groups directory for POWER9 powernv servers + + Each folder in this directory contains a sensor group + which are classified based on type of the sensor + like power, temperature, frequency, current, etc. They + can also indicate the group of sensors belonging to + different owners like CSM, Profiler, Job-Scheduler + +What: /sys/firmware/opal/sensor_groups/<sensor_group_name>/clear +Date: August 2017 +Contact: Linux for PowerPC mailing list <linuxppc-dev@ozlabs.org> +Description: Sysfs file to clear the min-max of all the sensors + belonging to the group. + + Writing 1 to this file will clear the minimum and + maximum values of all the sensors in the group. + In POWER9, the min-max of a sensor is the historical minimum + and maximum value of the sensor cached by OCC. diff --git a/Documentation/ABI/testing/sysfs-fs-f2fs b/Documentation/ABI/testing/sysfs-fs-f2fs index 1a6cd5397129..bd8a0d19abe6 100644 --- a/Documentation/ABI/testing/sysfs-fs-f2fs +++ b/Documentation/ABI/testing/sysfs-fs-f2fs @@ -318,3 +318,8 @@ Date: September 2019 Contact: "Hridya Valsaraju" <hridya@google.com> Description: Average number of valid blocks. Available when CONFIG_F2FS_STAT_FS=y. + +What: /sys/fs/f2fs/<disk>/mounted_time_sec +Date: February 2020 +Contact: "Jaegeuk Kim" <jaegeuk@kernel.org> +Description: Show the mounted time in secs of this partition. diff --git a/Documentation/ABI/testing/sysfs-kernel-fadump b/Documentation/ABI/testing/sysfs-kernel-fadump new file mode 100644 index 000000000000..8f7a64a81783 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-kernel-fadump @@ -0,0 +1,40 @@ +What: /sys/kernel/fadump/* +Date: Dec 2019 +Contact: linuxppc-dev@lists.ozlabs.org +Description: + The /sys/kernel/fadump/* is a collection of FADump sysfs + file provide information about the configuration status + of Firmware Assisted Dump (FADump). + +What: /sys/kernel/fadump/enabled +Date: Dec 2019 +Contact: linuxppc-dev@lists.ozlabs.org +Description: read only + Primarily used to identify whether the FADump is enabled in + the kernel or not. +User: Kdump service + +What: /sys/kernel/fadump/registered +Date: Dec 2019 +Contact: linuxppc-dev@lists.ozlabs.org +Description: read/write + Helps to control the dump collect feature from userspace. + Setting 1 to this file enables the system to collect the + dump and 0 to disable it. +User: Kdump service + +What: /sys/kernel/fadump/release_mem +Date: Dec 2019 +Contact: linuxppc-dev@lists.ozlabs.org +Description: write only + This is a special sysfs file and only available when + the system is booted to capture the vmcore using FADump. + It is used to release the memory reserved by FADump to + save the crash dump. + +What: /sys/kernel/fadump/mem_reserved +Date: Dec 2019 +Contact: linuxppc-dev@lists.ozlabs.org +Description: read only + Provide information about the amount of memory reserved by + FADump to save the crash dump in bytes. diff --git a/Documentation/ABI/testing/sysfs-platform-dell-laptop b/Documentation/ABI/testing/sysfs-platform-dell-laptop index 8c6a0b8e1131..9b917c7453de 100644 --- a/Documentation/ABI/testing/sysfs-platform-dell-laptop +++ b/Documentation/ABI/testing/sysfs-platform-dell-laptop @@ -2,7 +2,7 @@ What: /sys/class/leds/dell::kbd_backlight/als_enabled Date: December 2014 KernelVersion: 3.19 Contact: Gabriele Mazzotta <gabriele.mzt@gmail.com>, - Pali Rohár <pali.rohar@gmail.com> + Pali Rohár <pali@kernel.org> Description: This file allows to control the automatic keyboard illumination mode on some systems that have an ambient @@ -13,7 +13,7 @@ What: /sys/class/leds/dell::kbd_backlight/als_setting Date: December 2014 KernelVersion: 3.19 Contact: Gabriele Mazzotta <gabriele.mzt@gmail.com>, - Pali Rohár <pali.rohar@gmail.com> + Pali Rohár <pali@kernel.org> Description: This file allows to specifiy the on/off threshold value, as reported by the ambient light sensor. @@ -22,7 +22,7 @@ What: /sys/class/leds/dell::kbd_backlight/start_triggers Date: December 2014 KernelVersion: 3.19 Contact: Gabriele Mazzotta <gabriele.mzt@gmail.com>, - Pali Rohár <pali.rohar@gmail.com> + Pali Rohár <pali@kernel.org> Description: This file allows to control the input triggers that turn on the keyboard backlight illumination that is @@ -45,7 +45,7 @@ What: /sys/class/leds/dell::kbd_backlight/stop_timeout Date: December 2014 KernelVersion: 3.19 Contact: Gabriele Mazzotta <gabriele.mzt@gmail.com>, - Pali Rohár <pali.rohar@gmail.com> + Pali Rohár <pali@kernel.org> Description: This file allows to specify the interval after which the keyboard illumination is disabled because of inactivity. diff --git a/Documentation/PCI/boot-interrupts.rst b/Documentation/PCI/boot-interrupts.rst new file mode 100644 index 000000000000..d078ef3eb192 --- /dev/null +++ b/Documentation/PCI/boot-interrupts.rst @@ -0,0 +1,155 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=============== +Boot Interrupts +=============== + +:Author: - Sean V Kelley <sean.v.kelley@linux.intel.com> + +Overview +======== + +On PCI Express, interrupts are represented with either MSI or inbound +interrupt messages (Assert_INTx/Deassert_INTx). The integrated IO-APIC in a +given Core IO converts the legacy interrupt messages from PCI Express to +MSI interrupts. If the IO-APIC is disabled (via the mask bits in the +IO-APIC table entries), the messages are routed to the legacy PCH. This +in-band interrupt mechanism was traditionally necessary for systems that +did not support the IO-APIC and for boot. Intel in the past has used the +term "boot interrupts" to describe this mechanism. Further, the PCI Express +protocol describes this in-band legacy wire-interrupt INTx mechanism for +I/O devices to signal PCI-style level interrupts. The subsequent paragraphs +describe problems with the Core IO handling of INTx message routing to the +PCH and mitigation within BIOS and the OS. + + +Issue +===== + +When in-band legacy INTx messages are forwarded to the PCH, they in turn +trigger a new interrupt for which the OS likely lacks a handler. When an +interrupt goes unhandled over time, they are tracked by the Linux kernel as +Spurious Interrupts. The IRQ will be disabled by the Linux kernel after it +reaches a specific count with the error "nobody cared". This disabled IRQ +now prevents valid usage by an existing interrupt which may happen to share +the IRQ line. + + irq 19: nobody cared (try booting with the "irqpoll" option) + CPU: 0 PID: 2988 Comm: irq/34-nipalk Tainted: 4.14.87-rt49-02410-g4a640ec-dirty #1 + Hardware name: National Instruments NI PXIe-8880/NI PXIe-8880, BIOS 2.1.5f1 01/09/2020 + Call Trace: + <IRQ> + ? dump_stack+0x46/0x5e + ? __report_bad_irq+0x2e/0xb0 + ? note_interrupt+0x242/0x290 + ? nNIKAL100_memoryRead16+0x8/0x10 [nikal] + ? handle_irq_event_percpu+0x55/0x70 + ? handle_irq_event+0x4f/0x80 + ? handle_fasteoi_irq+0x81/0x180 + ? handle_irq+0x1c/0x30 + ? do_IRQ+0x41/0xd0 + ? common_interrupt+0x84/0x84 + </IRQ> + + handlers: + irq_default_primary_handler threaded usb_hcd_irq + Disabling IRQ #19 + + +Conditions +========== + +The use of threaded interrupts is the most likely condition to trigger +this problem today. Threaded interrupts may not be reenabled after the IRQ +handler wakes. These "one shot" conditions mean that the threaded interrupt +needs to keep the interrupt line masked until the threaded handler has run. +Especially when dealing with high data rate interrupts, the thread needs to +run to completion; otherwise some handlers will end up in stack overflows +since the interrupt of the issuing device is still active. + +Affected Chipsets +================= + +The legacy interrupt forwarding mechanism exists today in a number of +devices including but not limited to chipsets from AMD/ATI, Broadcom, and +Intel. Changes made through the mitigations below have been applied to +drivers/pci/quirks.c + +Starting with ICX there are no longer any IO-APICs in the Core IO's +devices. IO-APIC is only in the PCH. Devices connected to the Core IO's +PCIe Root Ports will use native MSI/MSI-X mechanisms. + +Mitigations +=========== + +The mitigations take the form of PCI quirks. The preference has been to +first identify and make use of a means to disable the routing to the PCH. +In such a case a quirk to disable boot interrupt generation can be +added.[1] + + Intel® 6300ESB I/O Controller Hub + Alternate Base Address Register: + BIE: Boot Interrupt Enable + 0 = Boot interrupt is enabled. + 1 = Boot interrupt is disabled. + + Intel® Sandy Bridge through Sky Lake based Xeon servers: + Coherent Interface Protocol Interrupt Control + dis_intx_route2pch/dis_intx_route2ich/dis_intx_route2dmi2: + When this bit is set. Local INTx messages received from the + Intel® Quick Data DMA/PCI Express ports are not routed to legacy + PCH - they are either converted into MSI via the integrated IO-APIC + (if the IO-APIC mask bit is clear in the appropriate entries) + or cause no further action (when mask bit is set) + +In the absence of a way to directly disable the routing, another approach +has been to make use of PCI Interrupt pin to INTx routing tables for +purposes of redirecting the interrupt handler to the rerouted interrupt +line by default. Therefore, on chipsets where this INTx routing cannot be +disabled, the Linux kernel will reroute the valid interrupt to its legacy +interrupt. This redirection of the handler will prevent the occurrence of +the spurious interrupt detection which would ordinarily disable the IRQ +line due to excessive unhandled counts.[2] + +The config option X86_REROUTE_FOR_BROKEN_BOOT_IRQS exists to enable (or +disable) the redirection of the interrupt handler to the PCH interrupt +line. The option can be overridden by either pci=ioapicreroute or +pci=noioapicreroute.[3] + + +More Documentation +================== + +There is an overview of the legacy interrupt handling in several datasheets +(6300ESB and 6700PXH below). While largely the same, it provides insight +into the evolution of its handling with chipsets. + +Example of disabling of the boot interrupt +------------------------------------------ + +Intel® 6300ESB I/O Controller Hub (Document # 300641-004US) + 5.7.3 Boot Interrupt + https://www.intel.com/content/dam/doc/datasheet/6300esb-io-controller-hub-datasheet.pdf + +Intel® Xeon® Processor E5-1600/2400/2600/4600 v3 Product Families +Datasheet - Volume 2: Registers (Document # 330784-003) + 6.6.41 cipintrc Coherent Interface Protocol Interrupt Control + https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e5-v3-datasheet-vol-2.pdf + +Example of handler rerouting +---------------------------- + +Intel® 6700PXH 64-bit PCI Hub (Document # 302628) + 2.15.2 PCI Express Legacy INTx Support and Boot Interrupt + https://www.intel.com/content/dam/doc/datasheet/6700pxh-64-bit-pci-hub-datasheet.pdf + + +If you have any legacy PCI interrupt questions that aren't answered, email me. + +Cheers, + Sean V Kelley + sean.v.kelley@linux.intel.com + +[1] https://lore.kernel.org/r/12131949181903-git-send-email-sassmann@suse.de/ +[2] https://lore.kernel.org/r/12131949182094-git-send-email-sassmann@suse.de/ +[3] https://lore.kernel.org/r/487C8EA7.6020205@suse.de/ diff --git a/Documentation/PCI/index.rst b/Documentation/PCI/index.rst index 6768305e4c26..8f66feaafd4f 100644 --- a/Documentation/PCI/index.rst +++ b/Documentation/PCI/index.rst @@ -16,3 +16,4 @@ Linux PCI Bus Subsystem pci-error-recovery pcieaer-howto endpoint/index + boot-interrupts diff --git a/Documentation/PCI/pcieaer-howto.rst b/Documentation/PCI/pcieaer-howto.rst index 18bdefaafd1a..0b36b9ebfa4b 100644 --- a/Documentation/PCI/pcieaer-howto.rst +++ b/Documentation/PCI/pcieaer-howto.rst @@ -156,12 +156,6 @@ default reset_link function, but different upstream ports might have different specifications to reset pci express link, so all upstream ports should provide their own reset_link functions. -In struct pcie_port_service_driver, a new pointer, reset_link, is -added. -:: - - pci_ers_result_t (*reset_link) (struct pci_dev *dev); - Section 3.2.2.2 provides more detailed info on when to call reset_link. @@ -212,15 +206,10 @@ error_detected(dev, pci_channel_io_frozen) to all drivers within a hierarchy in question. Then, performing link reset at upstream is necessary. As different kinds of devices might use different approaches to reset link, AER port service driver is required to provide the -function to reset link. Firstly, kernel looks for if the upstream -component has an aer driver. If it has, kernel uses the reset_link -callback of the aer driver. If the upstream component has no aer driver -and the port is downstream port, we will perform a hot reset as the -default by setting the Secondary Bus Reset bit of the Bridge Control -register associated with the downstream port. As for upstream ports, -they should provide their own aer service drivers with reset_link -function. If error_detected returns PCI_ERS_RESULT_CAN_RECOVER and -reset_link returns PCI_ERS_RESULT_RECOVERED, the error handling goes +function to reset link via callback parameter of pcie_do_recovery() +function. If reset_link is not NULL, recovery function will use it +to reset the link. If error_detected returns PCI_ERS_RESULT_CAN_RECOVER +and reset_link returns PCI_ERS_RESULT_RECOVERED, the error handling goes to mmio_enabled. helper functions @@ -243,9 +232,9 @@ messages to root port when an error is detected. :: - int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev);` + int pci_aer_clear_nonfatal_status(struct pci_dev *dev);` -pci_cleanup_aer_uncorrect_error_status cleanups the uncorrectable +pci_aer_clear_nonfatal_status clears non-fatal errors in the uncorrectable error status register. Frequent Asked Questions diff --git a/Documentation/admin-guide/binderfs.rst b/Documentation/admin-guide/binderfs.rst index c009671f8434..8243af9b3510 100644 --- a/Documentation/admin-guide/binderfs.rst +++ b/Documentation/admin-guide/binderfs.rst @@ -33,6 +33,12 @@ max a per-instance limit. If ``max=<count>`` is set then only ``<count>`` number of binder devices can be allocated in this binderfs instance. +stats + Using ``stats=global`` enables global binder statistics. + ``stats=global`` is only available for a binderfs instance mounted in the + initial user namespace. An attempt to use the option to mount a binderfs + instance in another user namespace will return a permission error. + Allocating binder Devices ------------------------- diff --git a/Documentation/admin-guide/cgroup-v1/cpusets.rst b/Documentation/admin-guide/cgroup-v1/cpusets.rst index 86a6ae995d54..7ade3abd342a 100644 --- a/Documentation/admin-guide/cgroup-v1/cpusets.rst +++ b/Documentation/admin-guide/cgroup-v1/cpusets.rst @@ -223,6 +223,17 @@ cpu_online_mask using a CPU hotplug notifier, and the mems file automatically tracks the value of node_states[N_MEMORY]--i.e., nodes with memory--using the cpuset_track_online_nodes() hook. +The cpuset.effective_cpus and cpuset.effective_mems files are +normally read-only copies of cpuset.cpus and cpuset.mems files +respectively. If the cpuset cgroup filesystem is mounted with the +special "cpuset_v2_mode" option, the behavior of these files will become +similar to the corresponding files in cpuset v2. In other words, hotplug +events will not change cpuset.cpus and cpuset.mems. Those events will +only affect cpuset.effective_cpus and cpuset.effective_mems which show +the actual cpus and memory nodes that are currently used by this cpuset. +See Documentation/admin-guide/cgroup-v2.rst for more information about +cpuset v2 behavior. + 1.4 What are exclusive cpusets ? -------------------------------- diff --git a/Documentation/admin-guide/dynamic-debug-howto.rst b/Documentation/admin-guide/dynamic-debug-howto.rst index 252e5ef324e5..0dc2eb8e44e5 100644 --- a/Documentation/admin-guide/dynamic-debug-howto.rst +++ b/Documentation/admin-guide/dynamic-debug-howto.rst @@ -54,6 +54,9 @@ If you make a mistake with the syntax, the write will fail thus:: <debugfs>/dynamic_debug/control -bash: echo: write error: Invalid argument +Note, for systems without 'debugfs' enabled, the control file can be +found in ``/proc/dynamic_debug/control``. + Viewing Dynamic Debug Behaviour =============================== diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 4d5a4fe22703..f2a93c8679e8 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -22,11 +22,13 @@ default: 0 acpi_backlight= [HW,ACPI] - acpi_backlight=vendor - acpi_backlight=video - If set to vendor, prefer vendor specific driver + { vendor | video | native | none } + If set to vendor, prefer vendor-specific driver (e.g. thinkpad_acpi, sony_acpi, etc.) instead of the ACPI video.ko driver. + If set to video, use the ACPI video.ko driver. + If set to native, use the device's native backlight mode. + If set to none, disable the ACPI backlight interface. acpi_force_32bit_fadt_addr force FADT to use 32 bit addresses rather than the @@ -683,7 +685,7 @@ coredump_filter= [KNL] Change the default value for /proc/<pid>/coredump_filter. - See also Documentation/filesystems/proc.txt. + See also Documentation/filesystems/proc.rst. coresight_cpu_debug.enable [ARM,ARM64] @@ -960,7 +962,7 @@ edid/1680x1050.bin, or edid/1920x1080.bin is given and no file with the same name exists. Details and instructions how to build your own EDID data are - available in Documentation/driver-api/edid.rst. An EDID + available in Documentation/admin-guide/edid.rst. An EDID data set will only be used for a particular connector, if its name and a colon are prepended to the EDID name. Each connector may use a unique EDID data @@ -990,10 +992,6 @@ Documentation/admin-guide/dynamic-debug-howto.rst for details. - nompx [X86] Disables Intel Memory Protection Extensions. - See Documentation/x86/intel_mpx.rst for more - information about the feature. - nopku [X86] Disable Memory Protection Keys CPU feature found in some Intel CPUs. @@ -1473,6 +1471,14 @@ hpet_mmap= [X86, HPET_MMAP] Allow userspace to mmap HPET registers. Default set by CONFIG_HPET_MMAP_DEFAULT. + hugetlb_cma= [HW] The size of a cma area used for allocation + of gigantic hugepages. + Format: nn[KMGTPE] + + Reserve a cma area of given size and allocate gigantic + hugepages using the cma allocator. If enabled, the + boot-time allocation of gigantic hugepages is skipped. + hugepages= [HW,X86-32,IA-64] HugeTLB pages to allocate at boot. hugepagesz= [HW,IA-64,PPC,X86-64] The size of the HugeTLB pages. On x86-64 and powerpc, this option can be specified @@ -2571,13 +2577,22 @@ For details see: Documentation/admin-guide/hw-vuln/mds.rst mem=nn[KMG] [KNL,BOOT] Force usage of a specific amount of memory - Amount of memory to be used when the kernel is not able - to see the whole system memory or for test. + Amount of memory to be used in cases as follows: + + 1 for test; + 2 when the kernel is not able to see the whole system memory; + 3 memory that lies after 'mem=' boundary is excluded from + the hypervisor, then assigned to KVM guests. + [X86] Work as limiting max address. Use together with memmap= to avoid physical address space collisions. Without memmap= PCI devices could be placed at addresses belonging to unused RAM. + Note that this only takes effects during boot time since + in above case 3, memory may need be hot added after boot + if system memory of hypervisor is not sufficient. + mem=nopentium [BUGS=X86-32] Disable usage of 4MB pages for kernel memory. @@ -3720,6 +3735,9 @@ Override pmtimer IOPort with a hex value. e.g. pmtmr=0x508 + pm_debug_messages [SUSPEND,KNL] + Enable suspend/resume debug messages during boot up. + pnp.debug=1 [PNP] Enable PNP debug messages (depends on the CONFIG_PNP_DEBUG_MESSAGES option). Change at run-time diff --git a/Documentation/admin-guide/mm/transhuge.rst b/Documentation/admin-guide/mm/transhuge.rst index bd5714547cee..2f31de8f7c74 100644 --- a/Documentation/admin-guide/mm/transhuge.rst +++ b/Documentation/admin-guide/mm/transhuge.rst @@ -310,6 +310,11 @@ thp_fault_fallback is incremented if a page fault fails to allocate a huge page and instead falls back to using small pages. +thp_fault_fallback_charge + is incremented if a page fault fails to charge a huge page and + instead falls back to using small pages even though the + allocation was successful. + thp_collapse_alloc_failed is incremented if khugepaged found a range of pages that should be collapsed into one huge page but failed @@ -319,6 +324,15 @@ thp_file_alloc is incremented every time a file huge page is successfully allocated. +thp_file_fallback + is incremented if a file huge page is attempted to be allocated + but fails and instead falls back to using small pages. + +thp_file_fallback_charge + is incremented if a file huge page cannot be charged and instead + falls back to using small pages even though the allocation was + successful. + thp_file_mapped is incremented every time a file huge page is mapped into user address space. diff --git a/Documentation/admin-guide/mm/userfaultfd.rst b/Documentation/admin-guide/mm/userfaultfd.rst index 5048cf661a8a..c30176e67900 100644 --- a/Documentation/admin-guide/mm/userfaultfd.rst +++ b/Documentation/admin-guide/mm/userfaultfd.rst @@ -108,6 +108,57 @@ UFFDIO_COPY. They're atomic as in guaranteeing that nothing can see an half copied page since it'll keep userfaulting until the copy has finished. +Notes: + +- If you requested UFFDIO_REGISTER_MODE_MISSING when registering then + you must provide some kind of page in your thread after reading from + the uffd. You must provide either UFFDIO_COPY or UFFDIO_ZEROPAGE. + The normal behavior of the OS automatically providing a zero page on + an annonymous mmaping is not in place. + +- None of the page-delivering ioctls default to the range that you + registered with. You must fill in all fields for the appropriate + ioctl struct including the range. + +- You get the address of the access that triggered the missing page + event out of a struct uffd_msg that you read in the thread from the + uffd. You can supply as many pages as you want with UFFDIO_COPY or + UFFDIO_ZEROPAGE. Keep in mind that unless you used DONTWAKE then + the first of any of those IOCTLs wakes up the faulting thread. + +- Be sure to test for all errors including (pollfd[0].revents & + POLLERR). This can happen, e.g. when ranges supplied were + incorrect. + +Write Protect Notifications +--------------------------- + +This is equivalent to (but faster than) using mprotect and a SIGSEGV +signal handler. + +Firstly you need to register a range with UFFDIO_REGISTER_MODE_WP. +Instead of using mprotect(2) you use ioctl(uffd, UFFDIO_WRITEPROTECT, +struct *uffdio_writeprotect) while mode = UFFDIO_WRITEPROTECT_MODE_WP +in the struct passed in. The range does not default to and does not +have to be identical to the range you registered with. You can write +protect as many ranges as you like (inside the registered range). +Then, in the thread reading from uffd the struct will have +msg.arg.pagefault.flags & UFFD_PAGEFAULT_FLAG_WP set. Now you send +ioctl(uffd, UFFDIO_WRITEPROTECT, struct *uffdio_writeprotect) again +while pagefault.mode does not have UFFDIO_WRITEPROTECT_MODE_WP set. +This wakes up the thread which will continue to run with writes. This +allows you to do the bookkeeping about the write in the uffd reading +thread before the ioctl. + +If you registered with both UFFDIO_REGISTER_MODE_MISSING and +UFFDIO_REGISTER_MODE_WP then you need to think about the sequence in +which you supply a page and undo write protect. Note that there is a +difference between writes into a WP area and into a !WP area. The +former will have UFFD_PAGEFAULT_FLAG_WP set, the latter +UFFD_PAGEFAULT_FLAG_WRITE. The latter did not fail on protection but +you still need to supply a page when UFFDIO_REGISTER_MODE_MISSING was +used. + QEMU/KVM ======== diff --git a/Documentation/admin-guide/pm/suspend-flows.rst b/Documentation/admin-guide/pm/suspend-flows.rst new file mode 100644 index 000000000000..c479d7462647 --- /dev/null +++ b/Documentation/admin-guide/pm/suspend-flows.rst @@ -0,0 +1,270 @@ +.. SPDX-License-Identifier: GPL-2.0 +.. include:: <isonum.txt> + +========================= +System Suspend Code Flows +========================= + +:Copyright: |copy| 2020 Intel Corporation + +:Author: Rafael J. Wysocki <rafael.j.wysocki@intel.com> + +At least one global system-wide transition needs to be carried out for the +system to get from the working state into one of the supported +:doc:`sleep states <sleep-states>`. Hibernation requires more than one +transition to occur for this purpose, but the other sleep states, commonly +referred to as *system-wide suspend* (or simply *system suspend*) states, need +only one. + +For those sleep states, the transition from the working state of the system into +the target sleep state is referred to as *system suspend* too (in the majority +of cases, whether this means a transition or a sleep state of the system should +be clear from the context) and the transition back from the sleep state into the +working state is referred to as *system resume*. + +The kernel code flows associated with the suspend and resume transitions for +different sleep states of the system are quite similar, but there are some +significant differences between the :ref:`suspend-to-idle <s2idle>` code flows +and the code flows related to the :ref:`suspend-to-RAM <s2ram>` and +:ref:`standby <standby>` sleep states. + +The :ref:`suspend-to-RAM <s2ram>` and :ref:`standby <standby>` sleep states +cannot be implemented without platform support and the difference between them +boils down to the platform-specific actions carried out by the suspend and +resume hooks that need to be provided by the platform driver to make them +available. Apart from that, the suspend and resume code flows for these sleep +states are mostly identical, so they both together will be referred to as +*platform-dependent suspend* states in what follows. + + +.. _s2idle_suspend: + +Suspend-to-idle Suspend Code Flow +================================= + +The following steps are taken in order to transition the system from the working +state to the :ref:`suspend-to-idle <s2idle>` sleep state: + + 1. Invoking system-wide suspend notifiers. + + Kernel subsystems can register callbacks to be invoked when the suspend + transition is about to occur and when the resume transition has finished. + + That allows them to prepare for the change of the system state and to clean + up after getting back to the working state. + + 2. Freezing tasks. + + Tasks are frozen primarily in order to avoid unchecked hardware accesses + from user space through MMIO regions or I/O registers exposed directly to + it and to prevent user space from entering the kernel while the next step + of the transition is in progress (which might have been problematic for + various reasons). + + All user space tasks are intercepted as though they were sent a signal and + put into uninterruptible sleep until the end of the subsequent system resume + transition. + + The kernel threads that choose to be frozen during system suspend for + specific reasons are frozen subsequently, but they are not intercepted. + Instead, they are expected to periodically check whether or not they need + to be frozen and to put themselves into uninterruptible sleep if so. [Note, + however, that kernel threads can use locking and other concurrency controls + available in kernel space to synchronize themselves with system suspend and + resume, which can be much more precise than the freezing, so the latter is + not a recommended option for kernel threads.] + + 3. Suspending devices and reconfiguring IRQs. + + Devices are suspended in four phases called *prepare*, *suspend*, + *late suspend* and *noirq suspend* (see :ref:`driverapi_pm_devices` for more + information on what exactly happens in each phase). + + Every device is visited in each phase, but typically it is not physically + accessed in more than two of them. + + The runtime PM API is disabled for every device during the *late* suspend + phase and high-level ("action") interrupt handlers are prevented from being + invoked before the *noirq* suspend phase. + + Interrupts are still handled after that, but they are only acknowledged to + interrupt controllers without performing any device-specific actions that + would be triggered in the working state of the system (those actions are + deferred till the subsequent system resume transition as described + `below <s2idle_resume_>`_). + + IRQs associated with system wakeup devices are "armed" so that the resume + transition of the system is started when one of them signals an event. + + 4. Freezing the scheduler tick and suspending timekeeping. + + When all devices have been suspended, CPUs enter the idle loop and are put + into the deepest available idle state. While doing that, each of them + "freezes" its own scheduler tick so that the timer events associated with + the tick do not occur until the CPU is woken up by another interrupt source. + + The last CPU to enter the idle state also stops the timekeeping which + (among other things) prevents high resolution timers from triggering going + forward until the first CPU that is woken up restarts the timekeeping. + That allows the CPUs to stay in the deep idle state relatively long in one + go. + + From this point on, the CPUs can only be woken up by non-timer hardware + interrupts. If that happens, they go back to the idle state unless the + interrupt that woke up one of them comes from an IRQ that has been armed for + system wakeup, in which case the system resume transition is started. + + +.. _s2idle_resume: + +Suspend-to-idle Resume Code Flow +================================ + +The following steps are taken in order to transition the system from the +:ref:`suspend-to-idle <s2idle>` sleep state into the working state: + + 1. Resuming timekeeping and unfreezing the scheduler tick. + + When one of the CPUs is woken up (by a non-timer hardware interrupt), it + leaves the idle state entered in the last step of the preceding suspend + transition, restarts the timekeeping (unless it has been restarted already + by another CPU that woke up earlier) and the scheduler tick on that CPU is + unfrozen. + + If the interrupt that has woken up the CPU was armed for system wakeup, + the system resume transition begins. + + 2. Resuming devices and restoring the working-state configuration of IRQs. + + Devices are resumed in four phases called *noirq resume*, *early resume*, + *resume* and *complete* (see :ref:`driverapi_pm_devices` for more + information on what exactly happens in each phase). + + Every device is visited in each phase, but typically it is not physically + accessed in more than two of them. + + The working-state configuration of IRQs is restored after the *noirq* resume + phase and the runtime PM API is re-enabled for every device whose driver + supports it during the *early* resume phase. + + 3. Thawing tasks. + + Tasks frozen in step 2 of the preceding `suspend <s2idle_suspend_>`_ + transition are "thawed", which means that they are woken up from the + uninterruptible sleep that they went into at that time and user space tasks + are allowed to exit the kernel. + + 4. Invoking system-wide resume notifiers. + + This is analogous to step 1 of the `suspend <s2idle_suspend_>`_ transition + and the same set of callbacks is invoked at this point, but a different + "notification type" parameter value is passed to them. + + +Platform-dependent Suspend Code Flow +==================================== + +The following steps are taken in order to transition the system from the working +state to platform-dependent suspend state: + + 1. Invoking system-wide suspend notifiers. + + This step is the same as step 1 of the suspend-to-idle suspend transition + described `above <s2idle_suspend_>`_. + + 2. Freezing tasks. + + This step is the same as step 2 of the suspend-to-idle suspend transition + described `above <s2idle_suspend_>`_. + + 3. Suspending devices and reconfiguring IRQs. + + This step is analogous to step 3 of the suspend-to-idle suspend transition + described `above <s2idle_suspend_>`_, but the arming of IRQs for system + wakeup generally does not have any effect on the platform. + + There are platforms that can go into a very deep low-power state internally + when all CPUs in them are in sufficiently deep idle states and all I/O + devices have been put into low-power states. On those platforms, + suspend-to-idle can reduce system power very effectively. + + On the other platforms, however, low-level components (like interrupt + controllers) need to be turned off in a platform-specific way (implemented + in the hooks provided by the platform driver) to achieve comparable power + reduction. + + That usually prevents in-band hardware interrupts from waking up the system, + which must be done in a special platform-dependent way. Then, the + configuration of system wakeup sources usually starts when system wakeup + devices are suspended and is finalized by the platform suspend hooks later + on. + + 4. Disabling non-boot CPUs. + + On some platforms the suspend hooks mentioned above must run in a one-CPU + configuration of the system (in particular, the hardware cannot be accessed + by any code running in parallel with the platform suspend hooks that may, + and often do, trap into the platform firmware in order to finalize the + suspend transition). + + For this reason, the CPU offline/online (CPU hotplug) framework is used + to take all of the CPUs in the system, except for one (the boot CPU), + offline (typically, the CPUs that have been taken offline go into deep idle + states). + + This means that all tasks are migrated away from those CPUs and all IRQs are + rerouted to the only CPU that remains online. + + 5. Suspending core system components. + + This prepares the core system components for (possibly) losing power going + forward and suspends the timekeeping. + + 6. Platform-specific power removal. + + This is expected to remove power from all of the system components except + for the memory controller and RAM (in order to preserve the contents of the + latter) and some devices designated for system wakeup. + + In many cases control is passed to the platform firmware which is expected + to finalize the suspend transition as needed. + + +Platform-dependent Resume Code Flow +=================================== + +The following steps are taken in order to transition the system from a +platform-dependent suspend state into the working state: + + 1. Platform-specific system wakeup. + + The platform is woken up by a signal from one of the designated system + wakeup devices (which need not be an in-band hardware interrupt) and + control is passed back to the kernel (the working configuration of the + platform may need to be restored by the platform firmware before the + kernel gets control again). + + 2. Resuming core system components. + + The suspend-time configuration of the core system components is restored and + the timekeeping is resumed. + + 3. Re-enabling non-boot CPUs. + + The CPUs disabled in step 4 of the preceding suspend transition are taken + back online and their suspend-time configuration is restored. + + 4. Resuming devices and restoring the working-state configuration of IRQs. + + This step is the same as step 2 of the suspend-to-idle suspend transition + described `above <s2idle_resume_>`_. + + 5. Thawing tasks. + + This step is the same as step 3 of the suspend-to-idle suspend transition + described `above <s2idle_resume_>`_. + + 6. Invoking system-wide resume notifiers. + + This step is the same as step 4 of the suspend-to-idle suspend transition + described `above <s2idle_resume_>`_. diff --git a/Documentation/admin-guide/pm/system-wide.rst b/Documentation/admin-guide/pm/system-wide.rst index 2b1f987b34f0..1a1924d71006 100644 --- a/Documentation/admin-guide/pm/system-wide.rst +++ b/Documentation/admin-guide/pm/system-wide.rst @@ -8,3 +8,4 @@ System-Wide Power Management :maxdepth: 2 sleep-states + suspend-flows diff --git a/Documentation/admin-guide/sysctl/kernel.rst b/Documentation/admin-guide/sysctl/kernel.rst index 335696d3360d..0d427fd10941 100644 --- a/Documentation/admin-guide/sysctl/kernel.rst +++ b/Documentation/admin-guide/sysctl/kernel.rst @@ -390,9 +390,17 @@ When ``kptr_restrict`` is set to 2, kernel pointers printed using modprobe ======== -This gives the full path of the modprobe command which the kernel will -use to load modules. This can be used to debug module loading -requests:: +The full path to the usermode helper for autoloading kernel modules, +by default "/sbin/modprobe". This binary is executed when the kernel +requests a module. For example, if userspace passes an unknown +filesystem type to mount(), then the kernel will automatically request +the corresponding filesystem module by executing this usermode helper. +This usermode helper should insert the needed module into the kernel. + +This sysctl only affects module autoloading. It has no effect on the +ability to explicitly insert modules. + +This sysctl can be used to debug module loading requests:: echo '#! /bin/sh' > /tmp/modprobe echo 'echo "$@" >> /tmp/modprobe.log' >> /tmp/modprobe @@ -400,10 +408,15 @@ requests:: chmod a+x /tmp/modprobe echo /tmp/modprobe > /proc/sys/kernel/modprobe -This only applies when the *kernel* is requesting that the module be -loaded; it won't have any effect if the module is being loaded -explicitly using ``modprobe`` from userspace. +Alternatively, if this sysctl is set to the empty string, then module +autoloading is completely disabled. The kernel will not try to +execute a usermode helper at all, nor will it call the +kernel_module_request LSM hook. +If CONFIG_STATIC_USERMODEHELPER=y is set in the kernel configuration, +then the configured static usermode helper overrides this sysctl, +except that the empty string is still accepted to completely disable +module autoloading as described above. modules_disabled ================ @@ -446,7 +459,6 @@ Notes: successful IPC object allocation. If an IPC object allocation syscall fails, it is undefined if the value remains unmodified or is reset to -1. - nmi_watchdog ============ diff --git a/Documentation/admin-guide/sysctl/user.rst b/Documentation/admin-guide/sysctl/user.rst index 650eaa03f15e..c45824589339 100644 --- a/Documentation/admin-guide/sysctl/user.rst +++ b/Documentation/admin-guide/sysctl/user.rst @@ -65,6 +65,12 @@ max_pid_namespaces The maximum number of pid namespaces that any user in the current user namespace may create. +max_time_namespaces +=================== + + The maximum number of time namespaces that any user in the current + user namespace may create. + max_user_namespaces =================== diff --git a/Documentation/admin-guide/sysrq.rst b/Documentation/admin-guide/sysrq.rst index 72b2cfb066f4..a46209f4636c 100644 --- a/Documentation/admin-guide/sysrq.rst +++ b/Documentation/admin-guide/sysrq.rst @@ -48,9 +48,10 @@ always allowed (by a user with admin privileges). How do I use the magic SysRq key? ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -On x86 - You press the key combo :kbd:`ALT-SysRq-<command key>`. +On x86 + You press the key combo :kbd:`ALT-SysRq-<command key>`. -.. note:: + .. note:: Some keyboards may not have a key labeled 'SysRq'. The 'SysRq' key is also known as the 'Print Screen' key. Also some keyboards cannot @@ -58,14 +59,15 @@ On x86 - You press the key combo :kbd:`ALT-SysRq-<command key>`. have better luck with press :kbd:`Alt`, press :kbd:`SysRq`, release :kbd:`SysRq`, press :kbd:`<command key>`, release everything. -On SPARC - You press :kbd:`ALT-STOP-<command key>`, I believe. +On SPARC + You press :kbd:`ALT-STOP-<command key>`, I believe. On the serial console (PC style standard serial ports only) You send a ``BREAK``, then within 5 seconds a command key. Sending ``BREAK`` twice is interpreted as a normal BREAK. On PowerPC - Press :kbd:`ALT - Print Screen` (or :kbd:`F13`) - :kbd:`<command key>`, + Press :kbd:`ALT - Print Screen` (or :kbd:`F13`) - :kbd:`<command key>`. :kbd:`Print Screen` (or :kbd:`F13`) - :kbd:`<command key>` may suffice. On other @@ -73,7 +75,7 @@ On other let me know so I can add them to this section. On all - write a character to /proc/sysrq-trigger. e.g.:: + Write a character to /proc/sysrq-trigger. e.g.:: echo t > /proc/sysrq-trigger @@ -282,7 +284,7 @@ Just ask them on the linux-kernel mailing list: Credits ~~~~~~~ -Written by Mydraal <vulpyne@vulpyne.net> -Updated by Adam Sulmicki <adam@cfar.umd.edu> -Updated by Jeremy M. Dolan <jmd@turbogeek.org> 2001/01/28 10:15:59 -Added to by Crutcher Dunnavant <crutcher+kernel@datastacks.com> +- Written by Mydraal <vulpyne@vulpyne.net> +- Updated by Adam Sulmicki <adam@cfar.umd.edu> +- Updated by Jeremy M. Dolan <jmd@turbogeek.org> 2001/01/28 10:15:59 +- Added to by Crutcher Dunnavant <crutcher+kernel@datastacks.com> diff --git a/Documentation/core-api/timekeeping.rst b/Documentation/core-api/timekeeping.rst index c0ffa30c7c37..729e24864fe7 100644 --- a/Documentation/core-api/timekeeping.rst +++ b/Documentation/core-api/timekeeping.rst @@ -154,9 +154,9 @@ architectures. These are the recommended replacements: Use ktime_get() or ktime_get_ts64() instead. -.. c:function:: struct timeval do_gettimeofday( void ) - struct timespec getnstimeofday( void ) - struct timespec64 getnstimeofday64( void ) +.. c:function:: void do_gettimeofday( struct timeval * ) + void getnstimeofday( struct timespec * ) + void getnstimeofday64( struct timespec64 * ) void ktime_get_real_ts( struct timespec * ) ktime_get_real_ts64() is a direct replacement, but consider using diff --git a/Documentation/devicetree/bindings/.gitignore b/Documentation/devicetree/bindings/.gitignore index 57afa1533a5f..5c6d8ea1a09c 100644 --- a/Documentation/devicetree/bindings/.gitignore +++ b/Documentation/devicetree/bindings/.gitignore @@ -1,2 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only *.example.dts processed-schema*.yaml diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml index e4131fa42b26..572381306681 100644 --- a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml @@ -21,6 +21,8 @@ properties: required: - compatible +additionalProperties: false + examples: - | clkmgr@ffd04000 { diff --git a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml index 853d7d2b56f5..66213bd95e6e 100644 --- a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml @@ -43,6 +43,8 @@ required: - compatible - reg +additionalProperties: false + examples: - | ao-secure@140 { diff --git a/Documentation/devicetree/bindings/arm/arm,integrator.yaml b/Documentation/devicetree/bindings/arm/arm,integrator.yaml new file mode 100644 index 000000000000..192ded470e32 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,integrator.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,integrator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Integrator Boards Device Tree Bindings + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +description: |+ + These were the first ARM platforms officially supported by ARM Ltd. + They are ARMv4, ARMv5 and ARMv6-capable using different core tiles, + so the system is modular and can host a variety of CPU tiles called + "core tiles" and referred to in the device tree as "core modules". + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: ARM Integrator Application Platform, this board has a PCI + host and several PCI slots, as well as a number of slots for logical + expansion modules, it is referred to as an "ASIC Development + Motherboard" and is extended with custom FPGA and is intended for + rapid prototyping. See ARM DUI 0098B. This board can physically come + pre-packaged in a PC Tower form factor called Integrator/PP1 or a + special metal fixture called Integrator/PP2, see ARM DUI 0169A. + items: + - const: arm,integrator-ap + - description: ARM Integrator Compact Platform (HBI-0086), this board has + a compact form factor and mainly consists of the bare minimum + peripherals to make use of the core module. See ARM DUI 0159B. + items: + - const: arm,integrator-cp + - description: ARM Integrator Standard Development Board (SDB) Platform, + this board is a PCI-based board conforming to the Microsoft SDB + (HARP) specification. See ARM DUI 0099A. + items: + - const: arm,integrator-sp + + core-module@10000000: + type: object + description: the root node in the Integrator platforms must contain + a core module child node. They are always at physical address + 0x10000000 in all the Integrator variants. + properties: + compatible: + items: + - const: arm,core-module-integrator + - const: syscon + - const: simple-mfd + reg: + maxItems: 1 + + required: + - compatible + - reg + +patternProperties: + "^syscon@[0-9a-f]+$": + description: All Integrator boards must provide a system controller as a + node in the root of the device tree. + type: object + properties: + compatible: + items: + - enum: + - arm,integrator-ap-syscon + - arm,integrator-cp-syscon + - arm,integrator-sp-syscon + - const: syscon + reg: + maxItems: 1 + + required: + - compatible + - reg + + +required: + - compatible + - core-module@10000000 + +... diff --git a/Documentation/devicetree/bindings/arm/arm,realview.yaml b/Documentation/devicetree/bindings/arm/arm,realview.yaml new file mode 100644 index 000000000000..d6e85d198afe --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,realview.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,realview.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM RealView Boards Device Tree Bindings + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +description: |+ + The ARM RealView series of reference designs were built to explore the ARM + 11, Cortex A-8 and Cortex A-9 CPUs. This included new features compared to + the earlier CPUs such as TrustZone and multicore (MPCore). + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: ARM RealView Emulation Baseboard (HBI-0140) was created + as a generic platform to test different FPGA designs, and has + pluggable CPU modules, see ARM DUI 0303E. + items: + - const: arm,realview-eb + - description: ARM RealView Platform Baseboard for ARM1176JZF-S + (HBI-0147) was created as a development board to test ARM TrustZone, + CoreSight and Intelligent Energy Management (IEM) see ARM DUI 0425F. + items: + - const: arm,realview-pb1176 + - description: ARM RealView Platform Baseboard for ARM 11 MPCore + (HBI-0159, HBI-0175 and HBI-0176) was created to showcase + multiprocessing with ARM11 using MPCore using symmetric + multiprocessing (SMP). See ARM DUI 0351E. + items: + - const: arm,realview-pb11mp + - description: ARM RealView Platform Baseboard for Cortex-A8 (HBI-0178, + HBI-0176 and HBI-0175) was the first reference platform for the + Cortex CPU family, including a Cortex-A8 test chip. + items: + - const: arm,realview-pba8 + - description: ARM RealView Platform Baseboard Explore for Cortex-A9 + (HBI-0182 and HBI-0183) was the reference platform for the Cortex-A9 + CPU. + items: + - const: arm,realview-pbx + + soc: + description: All RealView boards must provide a soc node in the root of the + device tree, representing the System-on-Chip since these test chips are + rather complex. + type: object + properties: + compatible: + oneOf: + - items: + - const: arm,realview-eb-soc + - const: simple-bus + - items: + - const: arm,realview-pb1176-soc + - const: simple-bus + - items: + - const: arm,realview-pb11mp-soc + - const: simple-bus + - items: + - const: arm,realview-pba8-soc + - const: simple-bus + - items: + - const: arm,realview-pbx-soc + - const: simple-bus + + patternProperties: + "^.*syscon@[0-9a-f]+$": + type: object + description: All RealView boards must provide a syscon system controller + node inside the soc node. + properties: + compatible: + oneOf: + - items: + - const: arm,realview-eb11mp-revb-syscon + - const: arm,realview-eb-syscon + - const: syscon + - const: simple-mfd + - items: + - const: arm,realview-eb11mp-revc-syscon + - const: arm,realview-eb-syscon + - const: syscon + - const: simple-mfd + - items: + - const: arm,realview-eb-syscon + - const: syscon + - const: simple-mfd + - items: + - const: arm,realview-pb1176-syscon + - const: syscon + - const: simple-mfd + - items: + - const: arm,realview-pb11mp-syscon + - const: syscon + - const: simple-mfd + - items: + - const: arm,realview-pba8-syscon + - const: syscon + - const: simple-mfd + - items: + - const: arm,realview-pbx-syscon + - const: syscon + - const: simple-mfd + + required: + - compatible + - reg + + required: + - compatible + +required: + - compatible + - soc + +... diff --git a/Documentation/devicetree/bindings/arm/arm,versatile.yaml b/Documentation/devicetree/bindings/arm/arm,versatile.yaml new file mode 100644 index 000000000000..06efd2a075c9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,versatile.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,versatile.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Versatile Boards Device Tree Bindings + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +description: |+ + The ARM Versatile boards are two variants of ARM926EJ-S evaluation boards + with various pluggable interface boards, in essence the Versatile PB version + is a superset of the Versatile AB version. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: The ARM Versatile Application Baseboard (HBI-0118) is an + evaluation board specifically for the ARM926EJ-S. It can be connected + to an IB1 interface board for a touchscreen-type use case or an IB2 + for a candybar phone-type use case. See ARM DUI 0225D. + items: + - const: arm,versatile-ab + - description: The ARM Versatile Platform Baseboard (HBI-0117) is an + extension of the Versatile Application Baseboard that includes a + PCI host controller. Like the sibling board, it is done specifically + for ARM926EJ-S. See ARM DUI 0224B. + items: + - const: arm,versatile-pb + + core-module@10000000: + type: object + description: the root node in the Versatile platforms must contain + a core module child node. They are always at physical address + 0x10000000 in all the Versatile variants. + properties: + compatible: + items: + - const: arm,core-module-versatile + - const: syscon + - const: simple-mfd + reg: + maxItems: 1 + + required: + - compatible + - reg + +patternProperties: + "^syscon@[0-9a-f]+$": + type: object + description: When fitted with the IB2 Interface Board, the Versatile + AB will present an optional system controller node which controls the + extra peripherals on the interface board. + properties: + compatible: + contains: + const: arm,versatile-ib2-syscon + required: + - compatible + - reg + +required: + - compatible + - core-module@10000000 + +... diff --git a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml new file mode 100644 index 000000000000..8c06a73f716c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml @@ -0,0 +1,223 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Versatile Express and Juno Boards Device Tree Bindings + +maintainers: + - Sudeep Holla <sudeep.holla@arm.com> + - Linus Walleij <linus.walleij@linaro.org> + +description: |+ + ARM's Versatile Express platform were built as reference designs for exploring + multicore Cortex-A class systems. The Versatile Express family contains both + 32 bit (Aarch32) and 64 bit (Aarch64) systems. + + The board consist of a motherboard and one or more daughterboards (tiles). The + motherboard provides a set of peripherals. Processor and RAM "live" on the + tiles. + + The motherboard and each core tile should be described by a separate Device + Tree source file, with the tile's description including the motherboard file + using an include directive. As the motherboard can be initialized in one of + two different configurations ("memory maps"), care must be taken to include + the correct one. + + When a new generation of boards were introduced under the name "Juno", these + shared to many common characteristics with the Versatile Express that the + "arm,vexpress" compatible was retained in the root node, and these are + included in this binding schema as well. + + The root node indicates the CPU SoC on the core tile, and this + is a daughterboard to the main motherboard. The name used in the compatible + string shall match the name given in the core tile's technical reference + manual, followed by "arm,vexpress" as an additional compatible value. If + further subvariants are released of the core tile, even more fine-granular + compatible strings with up to three compatible strings are used. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores + in MPCore configuration in a test chip on the core tile. See ARM + DUI 0448I. This was the first Versatile Express platform. + items: + - const: arm,vexpress,v2p-ca9 + - const: arm,vexpress + - description: CoreTile Express A5x2 (V2P-CA5s) has 2 Cortex A5 CPU cores + in a test chip on the core tile. It is intended to evaluate NEON, FPU + and Jazelle support in the Cortex A5 family. See ARM DUI 0541C. + items: + - const: arm,vexpress,v2p-ca5s + - const: arm,vexpress + - description: Coretile Express A15x2 (V2P-CA15) has 2 Cortex A15 CPU + cores in a MPCore configuration in a test chip on the core tile. See + ARM DUI 0604F. + items: + - const: arm,vexpress,v2p-ca15 + - const: arm,vexpress + - description: CoreTile Express A15x4 (V2P-CA15, HBI-0237A) has 4 Cortex + A15 CPU cores in a test chip on the core tile. This is the first test + chip called "TC1". + items: + - const: arm,vexpress,v2p-ca15,tc1 + - const: arm,vexpress,v2p-ca15 + - const: arm,vexpress + - description: Coretile Express A15x2 A7x3 (V2P-CA15_A7) has 2 Cortex A15 + CPU cores and 3 Cortex A7 cores in a big.LITTLE MPCore configuration + in a test chip on the core tile. See ARM DDI 0503I. + items: + - const: arm,vexpress,v2p-ca15_a7 + - const: arm,vexpress + - description: LogicTile Express 20MG (V2F-1XV7) has 2 Cortex A53 CPU + cores in a test chip on the core tile. See ARM DDI 0498D. + items: + - const: arm,vexpress,v2f-1xv7,ca53x2 + - const: arm,vexpress,v2f-1xv7 + - const: arm,vexpress + - description: Arm Versatile Express Juno "r0" (the first Juno board, + V2M-Juno) was introduced as a vehicle for evaluating big.LITTLE on + AArch64 CPU cores. It has 2 Cortex A57 CPU cores and 4 Cortex A53 + cores in a big.LITTLE configuration. It also features the MALI T624 + GPU. See ARM document 100113_0000_07_en. + items: + - const: arm,juno + - const: arm,vexpress + - description: Arm Versatile Express Juno r1 Development Platform + (V2M-Juno r1) was introduced mainly aimed at development of PCIe + based systems. Juno r1 also has support for AXI masters placed on + the TLX connectors to join the coherency domain. Otherwise it is the + same configuration as Juno r0. See ARM document 100122_0100_06_en. + items: + - const: arm,juno-r1 + - const: arm,juno + - const: arm,vexpress + - description: Arm Versatile Express Juno r2 Development Platform + (V2M-Juno r2). It has the same feature set as Juno r0 and r1. See + ARM document 100114_0200_04_en. + items: + - const: arm,juno-r2 + - const: arm,juno + - const: arm,vexpress + - description: Arm AEMv8a Versatile Express Real-Time System Model + (VE RTSM) is a programmers view of the Versatile Express with Arm + v8A hardware. See ARM DUI 0575D. + items: + - const: arm,rtsm_ve,aemv8a + - const: arm,vexpress + - description: Arm FVP (Fixed Virtual Platform) base model revision C + See ARM Document 100964_1190_00_en. + items: + - const: arm,fvp-base-revc + - const: arm,vexpress + - description: Arm Foundation model for Aarch64 + items: + - const: arm,foundation-aarch64 + - const: arm,vexpress + + arm,hbi: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: This indicates the ARM HBI (Hardware Board ID), this is + ARM's unique board model ID, visible on the PCB's silkscreen. + + arm,vexpress,site: + description: As Versatile Express can be configured in number of physically + different setups, the device tree should describe platform topology. + For this reason the root node and main motherboard node must define this + property, describing the physical location of the children nodes. + 0 means motherboard site, while 1 and 2 are daughterboard sites, and + 0xf means "sisterboard" which is the site containing the main CPU tile. + allOf: + - $ref: '/schemas/types.yaml#/definitions/uint32' + - minimum: 0 + maximum: 15 + + arm,vexpress,position: + description: When daughterboards are stacked on one site, their position + in the stack be be described this attribute. + allOf: + - $ref: '/schemas/types.yaml#/definitions/uint32' + - minimum: 0 + maximum: 3 + + arm,vexpress,dcc: + description: When describing tiles consisting of more than one DCC, its + number can be specified with this attribute. + allOf: + - $ref: '/schemas/types.yaml#/definitions/uint32' + - minimum: 0 + maximum: 3 + +patternProperties: + "^bus@[0-9a-f]+$": + description: Static Memory Bus (SMB) node, if this exists it describes + the connection between the motherboard and any tiles. Sometimes the + compatible is placed directly under this node, sometimes it is placed + in a subnode named "motherboard". Sometimes the compatible includes + "arm,vexpress,v2?-p1" sometimes (on software models) is is just + "simple-bus". If the compatible is placed in the "motherboard" node, + it is stricter and always has two compatibles. + type: object + allOf: + - $ref: '/schemas/simple-bus.yaml' + + properties: + compatible: + oneOf: + - items: + - enum: + - arm,vexpress,v2m-p1 + - arm,vexpress,v2p-p1 + - const: simple-bus + - const: simple-bus + motherboard: + type: object + description: The motherboard description provides a single "motherboard" + node using 2 address cells corresponding to the Static Memory Bus + used between the motherboard and the tile. The first cell defines the + Chip Select (CS) line number, the second cell address offset within + the CS. All interrupt lines between the motherboard and the tile + are active high and are described using single cell. + properties: + "#address-cells": + const: 2 + "#size-cells": + const: 1 + compatible: + items: + - enum: + - arm,vexpress,v2m-p1 + - arm,vexpress,v2p-p1 + - const: simple-bus + arm,v2m-memory-map: + description: This describes the memory map type. + allOf: + - $ref: '/schemas/types.yaml#/definitions/string' + - enum: + - rs1 + - rs2 + required: + - compatible + required: + - compatible + +allOf: + - if: + properties: + compatible: + contains: + enum: + - arm,vexpress,v2p-ca9 + - arm,vexpress,v2p-ca5s + - arm,vexpress,v2p-ca15 + - arm,vexpress,v2p-ca15_a7 + - arm,vexpress,v2f-1xv7,ca53x2 + then: + required: + - arm,hbi + +... diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards deleted file mode 100644 index 96b1dad58253..000000000000 --- a/Documentation/devicetree/bindings/arm/arm-boards +++ /dev/null @@ -1,237 +0,0 @@ -ARM Integrator/AP (Application Platform) and Integrator/CP (Compact Platform) ------------------------------------------------------------------------------ -ARM's oldest Linux-supported platform with connectors for different core -tiles of ARMv4, ARMv5 and ARMv6 type. - -Required properties (in root node): - compatible = "arm,integrator-ap"; /* Application Platform */ - compatible = "arm,integrator-cp"; /* Compact Platform */ - -FPGA type interrupt controllers, see the versatile-fpga-irq binding doc. - -Required nodes: - -- core-module: the root node to the Integrator platforms must have - a core-module with regs and the compatible string - "arm,core-module-integrator" -- external-bus-interface: the root node to the Integrator platforms - must have an external bus interface with regs and the - compatible-string "arm,external-bus-interface" - - Required properties for the core module: - - regs: the location and size of the core module registers, one - range of 0x200 bytes. - -- syscon: the root node of the Integrator platforms must have a - system controller node pointing to the control registers, - with the compatible string - "arm,integrator-ap-syscon" - "arm,integrator-cp-syscon" - respectively. - - Required properties for the system controller: - - regs: the location and size of the system controller registers, - one range of 0x100 bytes. - - Required properties for the AP system controller: - - interrupts: the AP syscon node must include the logical module - interrupts, stated in order of module instance <module 0>, - <module 1>, <module 2> ... for the CP system controller this - is not required not of any use. - -/dts-v1/; -/include/ "integrator.dtsi" - -/ { - model = "ARM Integrator/AP"; - compatible = "arm,integrator-ap"; - - core-module@10000000 { - compatible = "arm,core-module-integrator"; - reg = <0x10000000 0x200>; - }; - - ebi@12000000 { - compatible = "arm,external-bus-interface"; - reg = <0x12000000 0x100>; - }; - - syscon { - compatible = "arm,integrator-ap-syscon"; - reg = <0x11000000 0x100>; - interrupt-parent = <&pic>; - /* These are the logic module IRQs */ - interrupts = <9>, <10>, <11>, <12>; - }; -}; - - -ARM Versatile Application and Platform Baseboards -------------------------------------------------- -ARM's development hardware platform with connectors for customizable -core tiles. The hardware configuration of the Versatile boards is -highly customizable. - -Required properties (in root node): - compatible = "arm,versatile-ab"; /* Application baseboard */ - compatible = "arm,versatile-pb"; /* Platform baseboard */ - -Interrupt controllers: -- VIC required properties: - compatible = "arm,versatile-vic"; - interrupt-controller; - #interrupt-cells = <1>; - -- SIC required properties: - compatible = "arm,versatile-sic"; - interrupt-controller; - #interrupt-cells = <1>; - -Required nodes: - -- core-module: the root node to the Versatile platforms must have - a core-module with regs and the compatible strings - "arm,core-module-versatile", "syscon" - -Optional nodes: - -- arm,versatile-ib2-syscon : if the Versatile has an IB2 interface - board mounted, this has a separate system controller that is - defined in this node. - Required properties: - compatible = "arm,versatile-ib2-syscon", "syscon" - -ARM RealView Boards -------------------- -The RealView boards cover tailored evaluation boards that are used to explore -the ARM11 and Cortex A-8 and Cortex A-9 processors. - -Required properties (in root node): - /* RealView Emulation Baseboard */ - compatible = "arm,realview-eb"; - /* RealView Platform Baseboard for ARM1176JZF-S */ - compatible = "arm,realview-pb1176"; - /* RealView Platform Baseboard for ARM11 MPCore */ - compatible = "arm,realview-pb11mp"; - /* RealView Platform Baseboard for Cortex A-8 */ - compatible = "arm,realview-pba8"; - /* RealView Platform Baseboard Explore for Cortex A-9 */ - compatible = "arm,realview-pbx"; - -Required nodes: - -- soc: some node of the RealView platforms must be the SoC - node that contain the SoC-specific devices, with the compatible - string set to one of these tuples: - "arm,realview-eb-soc", "simple-bus" - "arm,realview-pb1176-soc", "simple-bus" - "arm,realview-pb11mp-soc", "simple-bus" - "arm,realview-pba8-soc", "simple-bus" - "arm,realview-pbx-soc", "simple-bus" - -- syscon: some subnode of the RealView SoC node must be a - system controller node pointing to the control registers, - with the compatible string set to one of these: - "arm,realview-eb11mp-revb-syscon", "arm,realview-eb-syscon", "syscon" - "arm,realview-eb11mp-revc-syscon", "arm,realview-eb-syscon", "syscon" - "arm,realview-eb-syscon", "syscon" - "arm,realview-pb1176-syscon", "syscon" - "arm,realview-pb11mp-syscon", "syscon" - "arm,realview-pba8-syscon", "syscon" - "arm,realview-pbx-syscon", "syscon" - - Required properties for the system controller: - - regs: the location and size of the system controller registers, - one range of 0x1000 bytes. - -Example: - -/dts-v1/; -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "ARM RealView PB1176 with device tree"; - compatible = "arm,realview-pb1176"; - #address-cells = <1>; - #size-cells = <1>; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "arm,realview-pb1176-soc", "simple-bus"; - ranges; - - syscon: syscon@10000000 { - compatible = "arm,realview-syscon", "syscon"; - reg = <0x10000000 0x1000>; - }; - - }; -}; - -ARM Versatile Express Boards ------------------------------ -For details on the device tree bindings for ARM Versatile Express boards -please consult the vexpress.txt file in the same directory as this file. - -ARM Juno Boards ----------------- -The Juno boards are targeting development for AArch64 systems. The first -iteration, Juno r0, is a vehicle for evaluating big.LITTLE on AArch64, -with the second iteration, Juno r1, mainly aimed at development of PCIe -based systems. Juno r1 also has support for AXI masters placed on the TLX -connectors to join the coherency domain. - -Juno boards are described in a similar way to ARM Versatile Express boards, -with the motherboard part of the hardware being described in a separate file -to highlight the fact that is part of the support infrastructure for the SoC. -Juno device tree bindings also share the Versatile Express bindings as -described under the RS1 memory mapping. - -Required properties (in root node): - compatible = "arm,juno"; /* For Juno r0 board */ - compatible = "arm,juno-r1"; /* For Juno r1 board */ - compatible = "arm,juno-r2"; /* For Juno r2 board */ - -Required nodes: -The description for the board must include: - - a "psci" node describing the boot method used for the secondary CPUs. - A detailed description of the bindings used for "psci" nodes is present - in the psci.yaml file. - - a "cpus" node describing the available cores and their associated - "enable-method"s. For more details see cpus.yaml file. - -Example: - -/dts-v1/; -/ { - model = "ARM Juno development board (r0)"; - compatible = "arm,juno", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - A57_0: cpu@0 { - compatible = "arm,cortex-a57"; - reg = <0x0 0x0>; - device_type = "cpu"; - enable-method = "psci"; - }; - - ..... - - A53_0: cpu@100 { - compatible = "arm,cortex-a53"; - reg = <0x0 0x100>; - device_type = "cpu"; - enable-method = "psci"; - }; - - ..... - }; - -}; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt deleted file mode 100644 index e3f996920403..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt +++ /dev/null @@ -1,36 +0,0 @@ -Broadcom Kona Family CPU Enable Method --------------------------------------- -This binding defines the enable method used for starting secondary -CPUs in the following Broadcom SoCs: - BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664 - -The enable method is specified by defining the following required -properties in the "cpu" device tree node: - - enable-method = "brcm,bcm11351-cpu-method"; - - secondary-boot-reg = <...>; - -The secondary-boot-reg property is a u32 value that specifies the -physical address of the register used to request the ROM holding pen -code release a secondary CPU. The value written to the register is -formed by encoding the target CPU id into the low bits of the -physical start address it should jump to. - -Example: - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - enable-method = "brcm,bcm11351-cpu-method"; - secondary-boot-reg = <0x3500417c>; - }; - }; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351.txt deleted file mode 100644 index 0ff6560e6094..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351.txt +++ /dev/null @@ -1,10 +0,0 @@ -Broadcom BCM11351 device tree bindings -------------------------------------------- - -Boards with the bcm281xx SoC family (which includes bcm11130, bcm11140, -bcm11351, bcm28145, bcm28155 SoCs) shall have the following properties: - -Required root node property: - -compatible = "brcm,bcm11351"; -DEPRECATED: compatible = "bcm,bcm11351"; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351.yaml new file mode 100644 index 000000000000..b5ef2666e6b2 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351.yaml @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm11351.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM11351 device tree bindings + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - brcm,bcm28155-ap + - const: brcm,bcm11351 + +... diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm21664.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm21664.txt deleted file mode 100644 index e0774255e1a6..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm21664.txt +++ /dev/null @@ -1,15 +0,0 @@ -Broadcom BCM21664 device tree bindings --------------------------------------- - -This document describes the device tree bindings for boards with the BCM21664 -SoC. - -Required root node property: - - compatible: brcm,bcm21664 - -Example: - / { - model = "BCM21664 SoC"; - compatible = "brcm,bcm21664"; - [...] - } diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm21664.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm21664.yaml new file mode 100644 index 000000000000..aafbd6a27708 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm21664.yaml @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm21664.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM21664 device tree bindings + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - brcm,bcm21664-garnet + - const: brcm,bcm21664 + +... diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550-cpu-method.txt deleted file mode 100644 index a3af54c0e404..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550-cpu-method.txt +++ /dev/null @@ -1,36 +0,0 @@ -Broadcom Kona Family CPU Enable Method --------------------------------------- -This binding defines the enable method used for starting secondary -CPUs in the following Broadcom SoCs: - BCM23550 - -The enable method is specified by defining the following required -properties in the "cpu" device tree node: - - enable-method = "brcm,bcm23550"; - - secondary-boot-reg = <...>; - -The secondary-boot-reg property is a u32 value that specifies the -physical address of the register used to request the ROM holding pen -code release a secondary CPU. The value written to the register is -formed by encoding the target CPU id into the low bits of the -physical start address it should jump to. - -Example: - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - enable-method = "brcm,bcm23550"; - secondary-boot-reg = <0x3500417c>; - }; - }; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550.txt deleted file mode 100644 index 080baad923d6..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550.txt +++ /dev/null @@ -1,15 +0,0 @@ -Broadcom BCM23550 device tree bindings --------------------------------------- - -This document describes the device tree bindings for boards with the BCM23550 -SoC. - -Required root node property: - - compatible: brcm,bcm23550 - -Example: - / { - model = "BCM23550 SoC"; - compatible = "brcm,bcm23550"; - [...] - } diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550.yaml new file mode 100644 index 000000000000..c4b4efd28a55 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550.yaml @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm23550.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM23550 device tree bindings + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - brcm,bcm23550-sparrow + - const: brcm,bcm23550 + +... diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt deleted file mode 100644 index 8608a776caa7..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt +++ /dev/null @@ -1,15 +0,0 @@ -Broadcom BCM4708 device tree bindings -------------------------------------------- - -Boards with the BCM4708 SoC shall have the following properties: - -Required root node property: - -bcm4708 -compatible = "brcm,bcm4708"; - -bcm4709 -compatible = "brcm,bcm4709"; - -bcm53012 -compatible = "brcm,bcm53012"; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml new file mode 100644 index 000000000000..d48313c7ae45 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm4708.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM4708 device tree bindings + +description: + Broadcom BCM4708/47081/4709/47094/53012 Wi-Fi/network SoCs based + on the iProc architecture (Northstar). + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + - Hauke Mehrtens <hauke@hauke-m.de> + - Rafal Milecki <zajec5@gmail.com> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: BCM4708 based boards + items: + - enum: + - asus,rt-ac56u + - asus,rt-ac68u + - buffalo,wzr-1750dhp + - linksys,ea6300-v1 + - linksys,ea6500-v2 + - luxul,xap-1510v1 + - luxul,xwc-1000 + - netgear,r6250v1 + - netgear,r6300v2 + - smartrg,sr400ac + - brcm,bcm94708 + - const: brcm,bcm4708 + + - description: BCM47081 based boards + items: + - enum: + - asus,rt-n18u + - buffalo,wzr-600dhp2 + - buffalo,wzr-900dhp + - luxul,xap-1410v1 + - luxul,xwr-1200v1 + - tplink,archer-c5-v2 + - const: brcm,bcm47081 + - const: brcm,bcm4708 + + - description: BCM4709 based boards + items: + - enum: + - asus,rt-ac87u + - buffalo,wxr-1900dhp + - linksys,ea9200 + - netgear,r7000 + - netgear,r8000 + - tplink,archer-c9-v1 + - brcm,bcm94709 + - const: brcm,bcm4709 + - const: brcm,bcm4708 + + - description: BCM47094 based boards + items: + - enum: + - dlink,dir-885l + - linksys,panamera + - luxul,abr-4500-v1 + - luxul,xap-1610-v1 + - luxul,xbr-4500-v1 + - luxul,xwc-2000-v1 + - luxul,xwr-3100v1 + - luxul,xwr-3150-v1 + - netgear,r8500 + - phicomm,k3 + - const: brcm,bcm47094 + - const: brcm,bcm4708 + + - description: BCM53012 based boards + items: + - enum: + - brcm,bcm953012er + - brcm,bcm953012hr + - brcm,bcm953012k + - const: brcm,brcm53012 + - const: brcm,bcm4708 +... diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,cygnus.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,cygnus.txt deleted file mode 100644 index 4c77169bb534..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,cygnus.txt +++ /dev/null @@ -1,31 +0,0 @@ -Broadcom Cygnus device tree bindings ------------------------------------- - - -Boards with Cygnus SoCs shall have the following properties: - -Required root node property: - -BCM11300 -compatible = "brcm,bcm11300", "brcm,cygnus"; - -BCM11320 -compatible = "brcm,bcm11320", "brcm,cygnus"; - -BCM11350 -compatible = "brcm,bcm11350", "brcm,cygnus"; - -BCM11360 -compatible = "brcm,bcm11360", "brcm,cygnus"; - -BCM58300 -compatible = "brcm,bcm58300", "brcm,cygnus"; - -BCM58302 -compatible = "brcm,bcm58302", "brcm,cygnus"; - -BCM58303 -compatible = "brcm,bcm58303", "brcm,cygnus"; - -BCM58305 -compatible = "brcm,bcm58305", "brcm,cygnus"; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,cygnus.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,cygnus.yaml new file mode 100644 index 000000000000..fe111e72dac3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,cygnus.yaml @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/brcm,cygnus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Cygnus device tree bindings + +maintainers: + - Ray Jui <rjui@broadcom.com> + - Scott Branden <sbranden@broadcom.com> + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - brcm,bcm11300 + - brcm,bcm11320 + - brcm,bcm11350 + - brcm,bcm11360 + - brcm,bcm58300 + - brcm,bcm58302 + - brcm,bcm58303 + - brcm,bcm58305 + - const: brcm,cygnus + +... diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,hr2.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,hr2.txt deleted file mode 100644 index a124c7fc4dcd..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,hr2.txt +++ /dev/null @@ -1,14 +0,0 @@ -Broadcom Hurricane 2 device tree bindings ---------------------------------------- - -Broadcom Hurricane 2 family of SoCs are used for switching control. These SoCs -are based on Broadcom's iProc SoC architecture and feature a single core Cortex -A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND -flash and a PCIe attached integrated switching engine. - -Boards with Hurricane SoCs shall have the following properties: - -Required root node property: - -BCM53342 -compatible = "brcm,bcm53342", "brcm,hr2"; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,hr2.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,hr2.yaml new file mode 100644 index 000000000000..1158f49b0b83 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,hr2.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/brcm,hr2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Hurricane 2 device tree bindings + +description: + Broadcom Hurricane 2 family of SoCs are used for switching control. These SoCs + are based on Broadcom's iProc SoC architecture and feature a single core Cortex + A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND + flash and a PCIe attached integrated switching engine. + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - ubnt,unifi-switch8 + - const: brcm,bcm53342 + - const: brcm,hr2 + +... diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,ns2.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,ns2.txt deleted file mode 100644 index 35f056f4a1c3..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,ns2.txt +++ /dev/null @@ -1,9 +0,0 @@ -Broadcom North Star 2 (NS2) device tree bindings ------------------------------------------------- - -Boards with NS2 shall have the following properties: - -Required root node property: - -NS2 SVK board -compatible = "brcm,ns2-svk", "brcm,ns2"; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,ns2.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,ns2.yaml new file mode 100644 index 000000000000..2451704f87f0 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,ns2.yaml @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/brcm,ns2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom North Star 2 (NS2) device tree bindings + +maintainers: + - Ray Jui <rjui@broadcom.com> + - Scott Branden <sbranden@broadcom.com> + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - brcm,ns2-svk + - brcm,ns2-xmc + - const: brcm,ns2 + +... diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt deleted file mode 100644 index 677ef9d9f445..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt +++ /dev/null @@ -1,39 +0,0 @@ -Broadcom Northstar Plus SoC CPU Enable Method ---------------------------------------------- -This binding defines the enable method used for starting secondary -CPU in the following Broadcom SoCs: - BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 - -The enable method is specified by defining the following required -properties in the corresponding secondary "cpu" device tree node: - - enable-method = "brcm,bcm-nsp-smp"; - - secondary-boot-reg = <...>; - -The secondary-boot-reg property is a u32 value that specifies the -physical address of the register which should hold the common -entry point for a secondary CPU. This entry is cpu node specific -and should be added per cpu. E.g., in case of NSP (BCM58625) which -is a dual core CPU SoC, this entry should be added to cpu1 node. - - -Example: - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - enable-method = "brcm,bcm-nsp-smp"; - secondary-boot-reg = <0xffff042c>; - reg = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.txt deleted file mode 100644 index eae53e4556be..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.txt +++ /dev/null @@ -1,34 +0,0 @@ -Broadcom Northstar Plus device tree bindings --------------------------------------------- - -Broadcom Northstar Plus family of SoCs are used for switching control -and management applications as well as residential router/gateway -applications. The SoC features dual core Cortex A9 ARM CPUs, integrating -several peripheral interfaces including multiple Gigabit Ethernet PHYs, -DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash, -SATA and several other IO controllers. - -Boards with Northstar Plus SoCs shall have the following properties: - -Required root node property: - -BCM58522 -compatible = "brcm,bcm58522", "brcm,nsp"; - -BCM58525 -compatible = "brcm,bcm58525", "brcm,nsp"; - -BCM58535 -compatible = "brcm,bcm58535", "brcm,nsp"; - -BCM58622 -compatible = "brcm,bcm58622", "brcm,nsp"; - -BCM58623 -compatible = "brcm,bcm58623", "brcm,nsp"; - -BCM58625 -compatible = "brcm,bcm58625", "brcm,nsp"; - -BCM88312 -compatible = "brcm,bcm88312", "brcm,nsp"; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml new file mode 100644 index 000000000000..fe364cebf57f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/brcm,nsp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Northstar Plus device tree bindings + +description: + Broadcom Northstar Plus family of SoCs are used for switching control + and management applications as well as residential router/gateway + applications. The SoC features dual core Cortex A9 ARM CPUs, integrating + several peripheral interfaces including multiple Gigabit Ethernet PHYs, + DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash, + SATA and several other IO controllers. + +maintainers: + - Ray Jui <rjui@broadcom.com> + - Scott Branden <sbranden@broadcom.com> + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - brcm,bcm58522 + - brcm,bcm58525 + - brcm,bcm58535 + - brcm,bcm58622 + - brcm,bcm58623 + - brcm,bcm58625 + - brcm,bcm88312 + - const: brcm,nsp + +... diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,stingray.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,stingray.txt deleted file mode 100644 index 23a02178dd44..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,stingray.txt +++ /dev/null @@ -1,12 +0,0 @@ -Broadcom Stingray device tree bindings ------------------------------------------------- - -Boards with Stingray shall have the following properties: - -Required root node property: - -Stingray Combo SVK board -compatible = "brcm,bcm958742k", "brcm,stingray"; - -Stingray SST100 board -compatible = "brcm,bcm958742t", "brcm,stingray"; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,stingray.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,stingray.yaml new file mode 100644 index 000000000000..4ad2b2124ab4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,stingray.yaml @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/brcm,stingray.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Stingray device tree bindings + +maintainers: + - Ray Jui <rjui@broadcom.com> + - Scott Branden <sbranden@broadcom.com> + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - brcm,bcm958742k + - brcm,bcm958742t + - brcm,bcm958802a802x + - const: brcm,stingray + +... diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,vulcan-soc.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,vulcan-soc.txt deleted file mode 100644 index 223ed3471c08..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,vulcan-soc.txt +++ /dev/null @@ -1,10 +0,0 @@ -Broadcom Vulcan device tree bindings ------------------------------------- - -Boards with Broadcom Vulcan shall have the following root property: - -Broadcom Vulcan Evaluation Board: - compatible = "brcm,vulcan-eval", "brcm,vulcan-soc"; - -Generic Vulcan board: - compatible = "brcm,vulcan-soc"; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,vulcan-soc.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,vulcan-soc.yaml new file mode 100644 index 000000000000..c5b6f31c20b9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,vulcan-soc.yaml @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/brcm,vulcan-soc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Vulcan device tree bindings + +maintainers: + - Robert Richter <rrichter@marvell.com> + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - brcm,vulcan-eval + - cavium,thunderx2-cn9900 + - const: brcm,vulcan-soc + +... diff --git a/Documentation/devicetree/bindings/arm/coresight-cti.yaml b/Documentation/devicetree/bindings/arm/coresight-cti.yaml new file mode 100644 index 000000000000..3db3642bd532 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/coresight-cti.yaml @@ -0,0 +1,336 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# Copyright 2019 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/coresight-cti.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Coresight Cross Trigger Interface (CTI) device. + +description: | + The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected + to one or more CoreSight components and/or a CPU, with CTIs interconnected in + a star topology via the Cross Trigger Matrix (CTM), which is not programmable. + The ECT components are not part of the trace generation data path and are thus + not part of the CoreSight graph described in the general CoreSight bindings + file coresight.txt. + + The CTI component properties define the connections between the individual + CTI and the components it is directly connected to, consisting of input and + output hardware trigger signals. CTIs can have a maximum number of input and + output hardware trigger signals (8 each for v1 CTI, 32 each for v2 CTI). The + number is defined at design time, the maximum of each defined in the DEVID + register. + + CTIs are interconnected in a star topology via the CTM, using a number of + programmable channels, usually 4, but again implementation defined and + described in the DEVID register. The star topology is not required to be + described in the bindings as the actual connections are software + programmable. + + In general the connections between CTI and components via the trigger signals + are implementation defined, except when the CTI is connected to an ARM v8 + architecture core and optional ETM. + + In this case the ARM v8 architecture defines the required signal connections + between CTI and the CPU core and ETM if present. In the case of a v8 + architecturally connected CTI an additional compatible string is used to + indicate this feature (arm,coresight-cti-v8-arch). + + When CTI trigger connection information is unavailable then a minimal driver + binding can be declared with no explicit trigger signals. This will result + the driver detecting the maximum available triggers and channels from the + DEVID register and make them all available for use as a single default + connection. Any user / client application will require additional information + on the connections between the CTI and other components for correct operation. + This information might be found by enabling the Integration Test registers in + the driver (set CONFIG_CORESIGHT_CTI_INTEGRATION_TEST in Kernel + configuration). These registers may be used to explore the trigger connections + between CTI and other CoreSight components. + + Certain triggers between CoreSight devices and the CTI have specific types + and usages. These can be defined along with the signal indexes with the + constants defined in <dt-bindings/arm/coresight-cti-dt.h> + + For example a CTI connected to a core will usually have a DBGREQ signal. This + is defined in the binding as type PE_EDBGREQ. These types will appear in an + optional array alongside the signal indexes. Omitting types will default all + signals to GEN_IO. + + Note that some hardware trigger signals can be connected to non-CoreSight + components (e.g. UART etc) depending on hardware implementation. + +maintainers: + - Mike Leach <mike.leach@linaro.org> + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + enum: + - arm,coresight-cti + required: + - compatible + +properties: + $nodename: + pattern: "^cti(@[0-9a-f]+)$" + compatible: + oneOf: + - items: + - const: arm,coresight-cti + - const: arm,primecell + - items: + - const: arm,coresight-cti-v8-arch + - const: arm,coresight-cti + - const: arm,primecell + + reg: + maxItems: 1 + + cpu: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Handle to cpu this device is associated with. This must appear in the + base cti node if compatible string arm,coresight-cti-v8-arch is used, + or may appear in a trig-conns child node when appropriate. + + arm,cti-ctm-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines the CTM this CTI is connected to, in large systems with multiple + separate CTI/CTM nets. Typically multi-socket systems where the CTM is + propagated between sockets. + + arm,cs-dev-assoc: + $ref: /schemas/types.yaml#/definitions/phandle + description: + defines a phandle reference to an associated CoreSight trace device. + When the associated trace device is enabled, then the respective CTI + will be enabled. Use in a trig-conns node, or in CTI base node when + compatible string arm,coresight-cti-v8-arch used. If the associated + device has not been registered then the node name will be stored as + the connection name for later resolution. If the associated device is + not a CoreSight device or not registered then the node name will remain + the connection name and automatic enabling will not occur. + + # size cells and address cells required if trig-conns node present. + "#size-cells": + const: 0 + + "#address-cells": + const: 1 + +patternProperties: + '^trig-conns@([0-9]+)$': + type: object + description: + A trigger connections child node which describes the trigger signals + between this CTI and another hardware device. This device may be a CPU, + CoreSight device, any other hardware device or simple external IO lines. + The connection may have both input and output triggers, or only one or the + other. + + properties: + reg: + maxItems: 1 + + arm,trig-in-sigs: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 32 + description: + List of CTI trigger in signal numbers in use by a trig-conns node. + + arm,trig-in-types: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 32 + description: + List of constants representing the types for the CTI trigger in + signals. Types in this array match to the corresponding signal in the + arm,trig-in-sigs array. If the -types array is smaller, or omitted + completely, then the types will default to GEN_IO. + + arm,trig-out-sigs: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 32 + description: + List of CTI trigger out signal numbers in use by a trig-conns node. + + arm,trig-out-types: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 32 + description: + List of constants representing the types for the CTI trigger out + signals. Types in this array match to the corresponding signal + in the arm,trig-out-sigs array. If the "-types" array is smaller, + or omitted completely, then the types will default to GEN_IO. + + arm,trig-filters: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 32 + description: + List of CTI trigger out signals that will be blocked from becoming + active, unless filtering is disabled on the driver. + + arm,trig-conn-name: + allOf: + - $ref: /schemas/types.yaml#/definitions/string + description: + Defines a connection name that will be displayed, if the cpu or + arm,cs-dev-assoc properties are not being used in this connection. + Principle use for CTI that are connected to non-CoreSight devices, or + external IO. + + anyOf: + - required: + - arm,trig-in-sigs + - required: + - arm,trig-out-sigs + oneOf: + - required: + - arm,trig-conn-name + - required: + - cpu + - required: + - arm,cs-dev-assoc + required: + - reg + +required: + - compatible + - reg + - clocks + - clock-names + +if: + properties: + compatible: + contains: + const: arm,coresight-cti-v8-arch + +then: + required: + - cpu + +examples: + # minimum CTI definition. DEVID register used to set number of triggers. + - | + cti@20020000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x20020000 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + }; + # v8 architecturally defined CTI - CPU + ETM connections generated by the + # driver according to the v8 architecture specification. + - | + cti@859000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x859000 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + + cpu = <&CPU1>; + arm,cs-dev-assoc = <&etm1>; + }; + # Implementation defined CTI - CPU + ETM connections explicitly defined.. + # Shows use of type constants from dt-bindings/arm/coresight-cti-dt.h + # #size-cells and #address-cells are required if trig-conns@ nodes present. + - | + #include <dt-bindings/arm/coresight-cti-dt.h> + + cti@858000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x858000 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + + arm,cti-ctm-id = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs = <4 5 6 7>; + arm,trig-in-types = <ETM_EXTOUT + ETM_EXTOUT + ETM_EXTOUT + ETM_EXTOUT>; + arm,trig-out-sigs = <4 5 6 7>; + arm,trig-out-types = <ETM_EXTIN + ETM_EXTIN + ETM_EXTIN + ETM_EXTIN>; + arm,cs-dev-assoc = <&etm0>; + }; + + trig-conns@1 { + reg = <1>; + cpu = <&CPU0>; + arm,trig-in-sigs = <0 1>; + arm,trig-in-types = <PE_DBGTRIGGER + PE_PMUIRQ>; + arm,trig-out-sigs=<0 1 2 >; + arm,trig-out-types = <PE_EDBGREQ + PE_DBGRESTART + PE_CTIIRQ>; + + arm,trig-filters = <0>; + }; + }; + # Implementation defined CTI - non CoreSight component connections. + - | + cti@20110000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0 0x20110000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + + #address-cells = <1>; + #size-cells = <0>; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs=<0>; + arm,trig-in-types=<GEN_INTREQ>; + arm,trig-out-sigs=<0>; + arm,trig-out-types=<GEN_HALTREQ>; + arm,trig-conn-name = "sys_profiler"; + }; + + trig-conns@1 { + reg = <1>; + arm,trig-out-sigs=<2 3>; + arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>; + arm,trig-conn-name = "watchdog"; + }; + + trig-conns@2 { + reg = <2>; + arm,trig-in-sigs=<1 6>; + arm,trig-in-types=<GEN_HALTREQ GEN_RESTARTREQ>; + arm,trig-conn-name = "g_counter"; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index d02c42d21f2f..846f6daae71b 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -45,6 +45,10 @@ its hardware characteristcs. - Coresight Address Translation Unit (CATU) "arm,coresight-catu", "arm,primecell"; + - Coresight Cross Trigger Interface (CTI): + "arm,coresight-cti", "arm,primecell"; + See coresight-cti.yaml for full CTI definitions. + * reg: physical base address and length of the register set(s) of the component. @@ -72,6 +76,9 @@ its hardware characteristcs. * reg-names: the only acceptable values are "stm-base" and "stm-stimulus-base", each corresponding to the areas defined in "reg". +* Required properties for Coresight Cross Trigger Interface (CTI) + See coresight-cti.yaml for full CTI definitions. + * Required properties for devices that don't show up on the AMBA bus, such as non-configurable replicators and non-configurable funnels: diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 0d5b61056b10..a01814765ddb 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -123,11 +123,18 @@ properties: - arm,cortex-a12 - arm,cortex-a15 - arm,cortex-a17 + - arm,cortex-a32 + - arm,cortex-a34 + - arm,cortex-a35 - arm,cortex-a53 - arm,cortex-a55 - arm,cortex-a57 + - arm,cortex-a65 - arm,cortex-a72 - arm,cortex-a73 + - arm,cortex-a75 + - arm,cortex-a76 + - arm,cortex-a77 - arm,cortex-m0 - arm,cortex-m0+ - arm,cortex-m1 @@ -136,6 +143,8 @@ properties: - arm,cortex-r4 - arm,cortex-r5 - arm,cortex-r7 + - arm,neoverse-e1 + - arm,neoverse-n1 - brcm,brahma-b15 - brcm,brahma-b53 - brcm,vulcan @@ -155,6 +164,8 @@ properties: - nvidia,tegra194-carmel - qcom,krait - qcom,kryo + - qcom,kryo260 + - qcom,kryo280 - qcom,kryo385 - qcom,kryo485 - qcom,scorpion @@ -201,6 +212,8 @@ properties: - rockchip,rk3066-smp - socionext,milbeaut-m10v-smp - ste,dbx500-smp + - ti,am3352 + - ti,am4372 cpu-release-addr: $ref: '/schemas/types.yaml#/definitions/uint64' @@ -287,6 +300,39 @@ properties: While optional, it is the preferred way to get access to the cpu-core power-domains. + secondary-boot-reg: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + Required for systems that have an "enable-method" property value of + "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp". + + This includes the following SoCs: | + BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550 + BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 + + The secondary-boot-reg property is a u32 value that specifies the + physical address of the register used to request the ROM holding pen + code release a secondary CPU. The value written to the register is + formed by encoding the target CPU id into the low bits of the + physical start address it should jump to. + +if: + # If the enable-method property contains one of those values + properties: + enable-method: + contains: + enum: + - brcm,bcm11351-cpu-method + - brcm,bcm23550 + - brcm,bcm-nsp-smp + # and if enable-method is present + required: + - enable-method + +then: + required: + - secondary-boot-reg + required: - device_type - reg diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt index e07735a8c2c7..623fedf12180 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt @@ -164,7 +164,18 @@ Required properties: - compatible: should be: "fsl,imx8qxp-sc-key" followed by "fsl,imx-sc-key"; -- linux,keycodes: See Documentation/devicetree/bindings/input/keys.txt +- linux,keycodes: See Documentation/devicetree/bindings/input/input.yaml + +Thermal bindings based on SCU Message Protocol +------------------------------------------------------------ + +Required properties: +- compatible: Should be : + "fsl,imx8qxp-sc-thermal" + followed by "fsl,imx-sc-thermal"; + +- #thermal-sensor-cells: See Documentation/devicetree/bindings/thermal/thermal.txt + for a description. Example (imx8qxp): ------------- @@ -238,6 +249,11 @@ firmware { compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; timeout-sec = <60>; }; + + tsens: thermal-sensor { + compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; + #thermal-sensor-cells = <1>; + }; }; }; diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 0e17e1f6fb80..cd3fbe7e3948 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -119,6 +119,10 @@ properties: - fsl,imx6q-sabreauto - fsl,imx6q-sabrelite - fsl,imx6q-sabresd + - technexion,imx6q-pico-dwarf # TechNexion i.MX6Q Pico-Dwarf + - technexion,imx6q-pico-hobbit # TechNexion i.MX6Q Pico-Hobbit + - technexion,imx6q-pico-nymph # TechNexion i.MX6Q Pico-Nymph + - technexion,imx6q-pico-pi # TechNexion i.MX6Q Pico-Pi - technologic,imx6q-ts4900 - technologic,imx6q-ts7970 - toradex,apalis_imx6q # Apalis iMX6 Module @@ -166,6 +170,10 @@ properties: - emtrion,emcon-mx6-avari # emCON-MX6S or emCON-MX6DL SoM on Avari Base - fsl,imx6dl-sabreauto # i.MX6 DualLite/Solo SABRE Automotive Board - fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board + - technexion,imx6dl-pico-dwarf # TechNexion i.MX6DL Pico-Dwarf + - technexion,imx6dl-pico-hobbit # TechNexion i.MX6DL Pico-Hobbit + - technexion,imx6dl-pico-nymph # TechNexion i.MX6DL Pico-Nymph + - technexion,imx6dl-pico-pi # TechNexion i.MX6DL Pico-Pi - technologic,imx6dl-ts4900 - technologic,imx6dl-ts7970 - toradex,colibri_imx6dl # Colibri iMX6 Module @@ -225,6 +233,9 @@ properties: - fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board - kontron,imx6ul-n6310-som # Kontron N6310 SOM - kontron,imx6ul-n6311-som # Kontron N6311 SOM + - technexion,imx6ul-pico-dwarf # TechNexion i.MX6UL Pico-Dwarf + - technexion,imx6ul-pico-hobbit # TechNexion i.MX6UL Pico-Hobbit + - technexion,imx6ul-pico-pi # TechNexion i.MX6UL Pico-Pi - const: fsl,imx6ul - description: Kontron N6310 S Board @@ -274,6 +285,7 @@ properties: items: - enum: - toradex,colibri-imx7s # Colibri iMX7 Solo Module + - toradex,colibri-imx7s-aster # Colibri iMX7 Solo Module on Aster Carrier Board - toradex,colibri-imx7s-eval-v3 # Colibri iMX7 Solo Module on Colibri Evaluation Board V3 - tq,imx7s-mba7 # i.MX7S TQ MBa7 with TQMa7S SoM - const: fsl,imx7s @@ -284,8 +296,14 @@ properties: - fsl,imx7d-sdb # i.MX7 SabreSD Board - fsl,imx7d-sdb-reva # i.MX7 SabreSD Rev-A Board - novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board + - technexion,imx7d-pico-dwarf # TechNexion i.MX7D Pico-Dwarf + - technexion,imx7d-pico-hobbit # TechNexion i.MX7D Pico-Hobbit + - technexion,imx7d-pico-nymph # TechNexion i.MX7D Pico-Nymph + - technexion,imx7d-pico-pi # TechNexion i.MX7D Pico-Pi - toradex,colibri-imx7d # Colibri iMX7 Dual Module + - toradex,colibri-imx7d-aster # Colibri iMX7 Dual Module on Aster Carrier Board - toradex,colibri-imx7d-emmc # Colibri iMX7 Dual 1GB (eMMC) Module + - toradex,colibri-imx7d-emmc-aster # Colibri iMX7 Dual 1GB (eMMC) Module on Aster Carrier Board - toradex,colibri-imx7d-emmc-eval-v3 # Colibri iMX7 Dual 1GB (eMMC) Module on Colibri Evaluation Board V3 - toradex,colibri-imx7d-eval-v3 # Colibri iMX7 Dual Module on Colibri Evaluation Board V3 - tq,imx7d-mba7 # i.MX7D TQ MBa7 with TQMa7D SoM @@ -324,6 +342,12 @@ properties: - fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board - const: fsl,imx8mn + - description: i.MX8MP based Boards + items: + - enum: + - fsl,imx8mp-evk # i.MX8MP EVK Board + - const: fsl,imx8mp + - description: i.MX8MQ based Boards items: - enum: @@ -395,6 +419,51 @@ properties: - fsl,ls1021a-twr - const: fsl,ls1021a + - description: LS1028A based Boards + items: + - enum: + - fsl,ls1028a-qds + - fsl,ls1028a-rdb + - const: fsl,ls1028a + + - description: Kontron KBox A-230-LS + items: + - const: kontron,kbox-a-230-ls + - const: kontron,sl28-var4 + - const: kontron,sl28 + - const: fsl,ls1028a + - description: + Kontron SMARC-sAL28 board on the SMARC Eval Carrier 2.0 + items: + - enum: + - kontron,sl28-var2-ads2 + - kontron,sl28-var3-ads2 + - kontron,sl28-var4-ads2 + - enum: + - kontron,sl28-var2 + - kontron,sl28-var3 + - kontron,sl28-var4 + - const: kontron,sl28 + - const: fsl,ls1028a + + - description: + Kontron SMARC-sAL28 board (on a generic/undefined carrier) + items: + - enum: + - kontron,sl28-var2 + - kontron,sl28-var3 + - kontron,sl28-var4 + - const: kontron,sl28 + - const: fsl,ls1028a + + - description: + Kontron SMARC-sAL28 board (base). This is used in the base device + tree which is compatible with the overlays provided by the + vendor. + items: + - const: kontron,sl28 + - const: fsl,ls1028a + - description: LS1043A based Boards items: - enum: diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.yaml b/Documentation/devicetree/bindings/arm/l2c2x0.yaml index 913a8cd8b2c0..5d1d50eea26e 100644 --- a/Documentation/devicetree/bindings/arm/l2c2x0.yaml +++ b/Documentation/devicetree/bindings/arm/l2c2x0.yaml @@ -29,27 +29,30 @@ allOf: properties: compatible: - enum: - - arm,pl310-cache - - arm,l220-cache - - arm,l210-cache - # DEPRECATED by "brcm,bcm11351-a2-pl310-cache" - - bcm,bcm11351-a2-pl310-cache - # For Broadcom bcm11351 chipset where an - # offset needs to be added to the address before passing down to the L2 - # cache controller - - brcm,bcm11351-a2-pl310-cache - # Marvell Controller designed to be - # compatible with the ARM one, with system cache mode (meaning - # maintenance operations on L1 are broadcasted to the L2 and L2 - # performs the same operation). - - marvell,aurora-system-cache - # Marvell Controller designed to be - # compatible with the ARM one with outer cache mode. - - marvell,aurora-outer-cache - # Marvell Tauros3 cache controller, compatible - # with arm,pl310-cache controller. - - marvell,tauros3-cache + oneOf: + - enum: + - arm,pl310-cache + - arm,l220-cache + - arm,l210-cache + # DEPRECATED by "brcm,bcm11351-a2-pl310-cache" + - bcm,bcm11351-a2-pl310-cache + # For Broadcom bcm11351 chipset where an + # offset needs to be added to the address before passing down to the L2 + # cache controller + - brcm,bcm11351-a2-pl310-cache + # Marvell Controller designed to be + # compatible with the ARM one, with system cache mode (meaning + # maintenance operations on L1 are broadcasted to the L2 and L2 + # performs the same operation). + - marvell,aurora-system-cache + # Marvell Controller designed to be + # compatible with the ARM one with outer cache mode. + - marvell,aurora-outer-cache + - items: + # Marvell Tauros3 cache controller, compatible + # with arm,pl310-cache controller. + - const: marvell,tauros3-cache + - const: arm,pl310-cache cache-level: const: 2 diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml index 818dfe6de512..3235ec9e9bad 100644 --- a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml +++ b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml @@ -28,8 +28,11 @@ properties: items: - enum: - mrvl,mmp2-brownstone + - olpc,xo-1.75 - const: mrvl,mmp2 - description: MMP3 based boards items: - - const: mrvl,mmp3 + - enum: + - dell,wyse-ariel + - const: marvell,mmp3 ... diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 79902f470e4b..c3a8604dfa80 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -43,6 +43,8 @@ required: - reg-names - interrupts +additionalProperties: false + examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml index 52ae094ce330..97df36d301c9 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -20,27 +20,36 @@ properties: items: - enum: - apm,potenza-pmu - - arm,armv8-pmuv3 - - arm,cortex-a73-pmu - - arm,cortex-a72-pmu - - arm,cortex-a57-pmu - - arm,cortex-a53-pmu - - arm,cortex-a35-pmu - - arm,cortex-a17-pmu - - arm,cortex-a15-pmu - - arm,cortex-a12-pmu - - arm,cortex-a9-pmu - - arm,cortex-a8-pmu - - arm,cortex-a7-pmu - - arm,cortex-a5-pmu - - arm,arm11mpcore-pmu - - arm,arm1176-pmu + - arm,armv8-pmuv3 # Only for s/w models - arm,arm1136-pmu + - arm,arm1176-pmu + - arm,arm11mpcore-pmu + - arm,cortex-a5-pmu + - arm,cortex-a7-pmu + - arm,cortex-a8-pmu + - arm,cortex-a9-pmu + - arm,cortex-a12-pmu + - arm,cortex-a15-pmu + - arm,cortex-a17-pmu + - arm,cortex-a32-pmu + - arm,cortex-a34-pmu + - arm,cortex-a35-pmu + - arm,cortex-a53-pmu + - arm,cortex-a55-pmu + - arm,cortex-a57-pmu + - arm,cortex-a65-pmu + - arm,cortex-a72-pmu + - arm,cortex-a73-pmu + - arm,cortex-a75-pmu + - arm,cortex-a76-pmu + - arm,cortex-a77-pmu + - arm,neoverse-e1-pmu + - arm,neoverse-n1-pmu - brcm,vulcan-pmu - cavium,thunder-pmu + - qcom,krait-pmu - qcom,scorpion-pmu - qcom,scorpion-mp-pmu - - qcom,krait-pmu interrupts: # Don't know how many CPUs, so no constraints to specify diff --git a/Documentation/devicetree/bindings/arm/psci.yaml b/Documentation/devicetree/bindings/arm/psci.yaml index 5e66934455bb..9247b58c26fc 100644 --- a/Documentation/devicetree/bindings/arm/psci.yaml +++ b/Documentation/devicetree/bindings/arm/psci.yaml @@ -32,6 +32,9 @@ description: |+ http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf properties: + $nodename: + const: psci + compatible: oneOf: - description: @@ -141,6 +144,8 @@ allOf: - cpu_off - cpu_on +additionalProperties: false + examples: - |+ diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 5976c0b16b65..64ddae3bd39f 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -28,6 +28,7 @@ description: | apq8074 apq8084 apq8096 + ipq6018 ipq8074 mdm9615 msm8916 @@ -41,6 +42,7 @@ description: | The 'board' element must be one of the following strings: cdp + cp01-c1 dragonboard hk01 idp @@ -150,4 +152,10 @@ properties: - enum: - qcom,sc7180-idp - const: qcom,sc7180 + + - items: + - enum: + - qcom,ipq6018-cp01-c1 + - const: qcom,ipq6018 + ... diff --git a/Documentation/devicetree/bindings/arm/renesas,prr.yaml b/Documentation/devicetree/bindings/arm/renesas,prr.yaml index 7f8d17f33983..dd087643a9f8 100644 --- a/Documentation/devicetree/bindings/arm/renesas,prr.yaml +++ b/Documentation/devicetree/bindings/arm/renesas,prr.yaml @@ -27,6 +27,8 @@ required: - compatible - reg +additionalProperties: false + examples: - | prr: chipid@ff000044 { diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 9436124c5809..611094d9186b 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -208,6 +208,7 @@ properties: - description: R-Car M3-W+ (R8A77961) items: - enum: + - renesas,m3ulcb # M3ULCB (R-Car Starter Kit Pro, RTP8J77961ASKB0SK0SA05A (M3 ES3.0)) - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012SA5A) - const: renesas,r8a77961 diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 874b0eaa2a75..715586dea9bb 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -402,6 +402,11 @@ properties: - const: phytec,rk3288-phycore-som - const: rockchip,rk3288 + - description: Pine64 PinebookPro + items: + - const: pine64,pinebook-pro + - const: rockchip,rk3399 + - description: Pine64 Rock64 items: - const: pine64,rock64 @@ -443,7 +448,7 @@ properties: - description: Rockchip Kylin items: - - const: rockchip,kylin-rk3036 + - const: rockchip,rk3036-kylin - const: rockchip,rk3036 - description: Rockchip PX3 Evaluation board @@ -468,6 +473,11 @@ properties: - const: rockchip,r88 - const: rockchip,rk3368 + - description: Rockchip RK3036 Evaluation board + items: + - const: rockchip,rk3036-evb + - const: rockchip,rk3036 + - description: Rockchip RK3228 Evaluation board items: - const: rockchip,rk3228-evb diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml index afcd70803c12..0425d333b50d 100644 --- a/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml @@ -30,6 +30,8 @@ required: - compatible - reg +additionalProperties: false + examples: - | chipid@10000000 { diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.yaml b/Documentation/devicetree/bindings/arm/samsung/pmu.yaml index 73b56fc5bf58..c9651892710e 100644 --- a/Documentation/devicetree/bindings/arm/samsung/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/pmu.yaml @@ -89,6 +89,8 @@ required: - clock-names - clocks +additionalProperties: false + examples: - | #include <dt-bindings/clock/exynos5250.h> diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-secure-firmware.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-secure-firmware.yaml index 51d23b6f8a94..3d9abad3c749 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-secure-firmware.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-secure-firmware.yaml @@ -23,6 +23,8 @@ required: - compatible - reg +additionalProperties: false + examples: - | firmware@203f000 { diff --git a/Documentation/devicetree/bindings/arm/socionext/cache-uniphier.txt b/Documentation/devicetree/bindings/arm/socionext/cache-uniphier.txt deleted file mode 100644 index d27a646f48a9..000000000000 --- a/Documentation/devicetree/bindings/arm/socionext/cache-uniphier.txt +++ /dev/null @@ -1,60 +0,0 @@ -UniPhier outer cache controller - -UniPhier SoCs are integrated with a full-custom outer cache controller system. -All of them have a level 2 cache controller, and some have a level 3 cache -controller as well. - -Required properties: -- compatible: should be "socionext,uniphier-system-cache" -- reg: offsets and lengths of the register sets for the device. It should - contain 3 regions: control register, revision register, operation register, - in this order. -- cache-unified: specifies the cache is a unified cache. -- cache-size: specifies the size in bytes of the cache -- cache-sets: specifies the number of associativity sets of the cache -- cache-line-size: specifies the line size in bytes -- cache-level: specifies the level in the cache hierarchy. The value should - be 2 for L2 cache, 3 for L3 cache, etc. - -Optional properties: -- next-level-cache: phandle to the next level cache if present. The next level - cache should be also compatible with "socionext,uniphier-system-cache". - -The L2 cache must exist to use the L3 cache; the cache hierarchy must be -indicated correctly with "next-level-cache" properties. - -Example 1 (system with L2): - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, - <0x506c0000 0x400>; - cache-unified; - cache-size = <0x80000>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - -Example 2 (system with L2 and L3): - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, - <0x506c0000 0x400>; - cache-unified; - cache-size = <0x200000>; - cache-sets = <512>; - cache-line-size = <128>; - cache-level = <2>; - next-level-cache = <&l3>; - }; - - l3: l3-cache@500c8000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, - <0x506c8000 0x400>; - cache-unified; - cache-size = <0x400000>; - cache-sets = <512>; - cache-line-size = <256>; - cache-level = <3>; - }; diff --git a/Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml b/Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml new file mode 100644 index 000000000000..2e765bb3e6f6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier outer cache controller + +description: | + UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache + controller system. All of them have a level 2 cache controller, and some + have a level 3 cache controller as well. + +maintainers: + - Masahiro Yamada <yamada.masahiro@socionext.com> + +properties: + compatible: + const: socionext,uniphier-system-cache + + reg: + description: | + should contain 3 regions: control register, revision register, + operation register, in this order. + minItems: 3 + maxItems: 3 + + interrupts: + description: | + Interrupts can be used to notify the completion of cache operations. + The number of interrupts should match to the number of CPU cores. + The specified interrupts correspond to CPU0, CPU1, ... in this order. + minItems: 1 + maxItems: 4 + + cache-unified: true + + cache-size: true + + cache-sets: true + + cache-line-size: true + + cache-level: + minimum: 2 + maximum: 3 + + next-level-cache: true + +allOf: + - $ref: /schemas/cache-controller.yaml# + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - cache-unified + - cache-size + - cache-sets + - cache-line-size + - cache-level + +examples: + - | + // System with L2. + cache-controller@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; + cache-unified; + cache-size = <0x140000>; + cache-sets = <512>; + cache-line-size = <128>; + cache-level = <2>; + }; + - | + // System with L2 and L3. + // L2 should specify the next level cache by 'next-level-cache'. + l2: cache-controller@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; + interrupts = <0 190 4>, <0 191 4>; + cache-unified; + cache-size = <0x200000>; + cache-sets = <512>; + cache-line-size = <128>; + cache-level = <2>; + next-level-cache = <&l3>; + }; + + l3: cache-controller@500c8000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <0x200000>; + cache-sets = <512>; + cache-line-size = <256>; + cache-level = <3>; + }; diff --git a/Documentation/devicetree/bindings/arm/socionext/uniphier.txt b/Documentation/devicetree/bindings/arm/socionext/uniphier.txt deleted file mode 100644 index b3ed1033740e..000000000000 --- a/Documentation/devicetree/bindings/arm/socionext/uniphier.txt +++ /dev/null @@ -1,47 +0,0 @@ -Socionext UniPhier SoC family ------------------------------ - -Required properties in the root node: - - compatible: should contain board and SoC compatible strings - -SoC and board compatible strings: - (sorted chronologically) - - - LD4 SoC: "socionext,uniphier-ld4" - - Reference Board: "socionext,uniphier-ld4-ref" - - - Pro4 SoC: "socionext,uniphier-pro4" - - Reference Board: "socionext,uniphier-pro4-ref" - - Ace Board: "socionext,uniphier-pro4-ace" - - Sanji Board: "socionext,uniphier-pro4-sanji" - - - sLD8 SoC: "socionext,uniphier-sld8" - - Reference Board: "socionext,uniphier-sld8-ref" - - - PXs2 SoC: "socionext,uniphier-pxs2" - - Gentil Board: "socionext,uniphier-pxs2-gentil" - - Vodka Board: "socionext,uniphier-pxs2-vodka" - - - LD6b SoC: "socionext,uniphier-ld6b" - - Reference Board: "socionext,uniphier-ld6b-ref" - - - LD11 SoC: "socionext,uniphier-ld11" - - Reference Board: "socionext,uniphier-ld11-ref" - - Global Board: "socionext,uniphier-ld11-global" - - - LD20 SoC: "socionext,uniphier-ld20" - - Reference Board: "socionext,uniphier-ld20-ref" - - Global Board: "socionext,uniphier-ld20-global" - - - PXs3 SoC: "socionext,uniphier-pxs3" - - Reference Board: "socionext,uniphier-pxs3-ref" - -Example: - -/dts-v1/; - -/ { - compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20"; - - ... -}; diff --git a/Documentation/devicetree/bindings/arm/socionext/uniphier.yaml b/Documentation/devicetree/bindings/arm/socionext/uniphier.yaml new file mode 100644 index 000000000000..65ad6d8a3c99 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/socionext/uniphier.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/socionext/uniphier.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier platform device tree bindings + +maintainers: + - Masahiro Yamada <yamada.masahiro@socionext.com> + +properties: + $nodename: + const: / + compatible: + oneOf: + - description: LD4 SoC boards + items: + - enum: + - socionext,uniphier-ld4-ref + - const: socionext,uniphier-ld4 + - description: Pro4 SoC boards + items: + - enum: + - socionext,uniphier-pro4-ace + - socionext,uniphier-pro4-ref + - socionext,uniphier-pro4-sanji + - const: socionext,uniphier-pro4 + - description: sLD8 SoC boards + items: + - enum: + - socionext,uniphier-sld8-ref + - const: socionext,uniphier-sld8 + - description: PXs2 SoC boards + items: + - enum: + - socionext,uniphier-pxs2-gentil + - socionext,uniphier-pxs2-vodka + - const: socionext,uniphier-pxs2 + - description: LD6b SoC boards + items: + - enum: + - socionext,uniphier-ld6b-ref + - const: socionext,uniphier-ld6b + - description: LD11 SoC boards + items: + - enum: + - socionext,uniphier-ld11-global + - socionext,uniphier-ld11-ref + - const: socionext,uniphier-ld11 + - description: LD20 SoC boards + items: + - enum: + - socionext,uniphier-ld20-global + - socionext,uniphier-ld20-ref + - const: socionext,uniphier-ld20 + - description: PXs3 SoC boards + items: + - enum: + - socionext,uniphier-pxs3-ref + - const: socionext,uniphier-pxs3 diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index 0dedf94c8578..baff80197d5a 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -29,6 +29,8 @@ required: - reg - clocks +additionalProperties: false + examples: - | #include <dt-bindings/clock/stm32mp1-clks.h> diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 327ce6730823..abf2d97fb7ae 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -394,6 +394,12 @@ properties: - const: linksprite,pcduino3-nano - const: allwinner,sun7i-a20 + - description: Linutronix Testbox v2 + items: + - const: linutronix,testbox-v2 + - const: lamobo,lamobo-r1 + - const: allwinner,sun7i-a20 + - description: HAOYU Electronics Marsboard A10 items: - const: haoyu,a10-marsboard @@ -636,6 +642,21 @@ properties: - const: pine64,pinebook - const: allwinner,sun50i-a64 + - description: Pine64 PinePhone Developer Batch (1.0) + items: + - const: pine64,pinephone-1.0 + - const: allwinner,sun50i-a64 + + - description: Pine64 PinePhone Braveheart (1.1) + items: + - const: pine64,pinephone-1.1 + - const: allwinner,sun50i-a64 + + - description: Pine64 PineTab + items: + - const: pine64,pinetab + - const: allwinner,sun50i-a64 + - description: Pine64 SoPine Baseboard items: - const: pine64,sopine-baseboard @@ -647,6 +668,11 @@ properties: - const: pineriver,mini-xplus - const: allwinner,sun4i-a10 + - description: PocketBook Touch Lux 3 + items: + - const: pocketbook,touch-lux-3 + - const: allwinner,sun5i-a13 + - description: Point of View Protab2-IPS9 items: - const: pov,protab2-ips9 diff --git a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml index 9370e64992dd..e713a6fe4cf7 100644 --- a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml @@ -30,6 +30,7 @@ properties: enum: - allwinner,sun5i-a13-mbus - allwinner,sun8i-h3-mbus + - allwinner,sun50i-a64-mbus reg: maxItems: 1 @@ -41,6 +42,10 @@ properties: description: See section 2.3.9 of the DeviceTree Specification. + '#address-cells': true + + '#size-cells': true + required: - "#interconnect-cells" - compatible @@ -58,6 +63,8 @@ examples: compatible = "allwinner,sun5i-a13-mbus"; reg = <0x01c01000 0x1000>; clocks = <&ccu CLK_MBUS>; + #address-cells = <1>; + #size-cells = <1>; dma-ranges = <0x00000000 0x40000000 0x20000000>; #interconnect-cells = <1>; }; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt deleted file mode 100644 index cb12f33a247f..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt +++ /dev/null @@ -1,300 +0,0 @@ -NVIDIA Tegra Power Management Controller (PMC) - -== Power Management Controller Node == - -The PMC block interacts with an external Power Management Unit. The PMC -mostly controls the entry and exit of the system from different sleep -modes. It provides power-gating controllers for SoC and CPU power-islands. - -Required properties: -- name : Should be pmc -- compatible : Should contain one of the following: - For Tegra20 must contain "nvidia,tegra20-pmc". - For Tegra30 must contain "nvidia,tegra30-pmc". - For Tegra114 must contain "nvidia,tegra114-pmc" - For Tegra124 must contain "nvidia,tegra124-pmc" - For Tegra132 must contain "nvidia,tegra124-pmc" - For Tegra210 must contain "nvidia,tegra210-pmc" -- reg : Offset and length of the register set for the device -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: - "pclk" (The Tegra clock of that name), - "clk32k_in" (The 32KHz clock input to Tegra). - -Optional properties: -- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal. - The PMU is an external Power Management Unit, whose interrupt output - signal is fed into the PMC. This signal is optionally inverted, and then - fed into the ARM GIC. The PMC is not involved in the detection or - handling of this interrupt signal, merely its inversion. -- nvidia,suspend-mode : The suspend mode that the platform should use. - Valid values are 0, 1 and 2: - 0 (LP0): CPU + Core voltage off and DRAM in self-refresh - 1 (LP1): CPU voltage off and DRAM in self-refresh - 2 (LP2): CPU voltage off -- nvidia,core-power-req-active-high : Boolean, core power request active-high -- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high -- nvidia,combined-power-req : Boolean, combined power request for CPU & Core -- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC) - is enabled. - -Required properties when nvidia,suspend-mode is specified: -- nvidia,cpu-pwr-good-time : CPU power good time in uS. -- nvidia,cpu-pwr-off-time : CPU power off time in uS. -- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time> - Core power good time in uS. -- nvidia,core-pwr-off-time : Core power off time in uS. - -Required properties when nvidia,suspend-mode=<0>: -- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector - The LP0 vector contains the warm boot code that is executed by AVP when - resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7 - processor and always being the first boot processor when chip is power on - or resume from deep sleep mode. When the system is resumed from the deep - sleep mode, the warm boot code will restore some PLLs, clocks and then - bring up CPU0 for resuming the system. - -Hardware-triggered thermal reset: -On Tegra30, Tegra114 and Tegra124, if the 'i2c-thermtrip' subnode exists, -hardware-triggered thermal reset will be enabled. - -Required properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'): -- nvidia,i2c-controller-id : ID of I2C controller to send poweroff command to. Valid values are - described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0" of the - Tegra K1 Technical Reference Manual. -- nvidia,bus-addr : Bus address of the PMU on the I2C bus -- nvidia,reg-addr : I2C register address to write poweroff command to -- nvidia,reg-data : Poweroff command to write to PMU - -Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'): -- nvidia,pinmux-id : Pinmux used by the hardware when issuing poweroff command. - Defaults to 0. Valid values are described in section 12.5.2 - "Pinmux Support" of the Tegra4 Technical Reference Manual. - -Optional nodes: -- powergates : This node contains a hierarchy of power domain nodes, which - should match the powergates on the Tegra SoC. See "Powergate - Nodes" below. - -Example: - -/ SoC dts including file -pmc@7000f400 { - compatible = "nvidia,tegra20-pmc"; - reg = <0x7000e400 0x400>; - clocks = <&tegra_car 110>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <100>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <458>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - nvidia,lp0-vec = <0xbdffd000 0x2000>; -}; - -/ Tegra board dts file -{ - ... - pmc@7000f400 { - i2c-thermtrip { - nvidia,i2c-controller-id = <4>; - nvidia,bus-addr = <0x40>; - nvidia,reg-addr = <0x36>; - nvidia,reg-data = <0x2>; - }; - }; - ... - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - ... -}; - - -== Powergate Nodes == - -Each of the powergate nodes represents a power-domain on the Tegra SoC -that can be power-gated by the Tegra PMC. The name of the powergate node -should be one of the below. Note that not every powergate is applicable -to all Tegra devices and the following list shows which powergates are -applicable to which devices. Please refer to the Tegra TRM for more -details on the various powergates. - - Name Description Devices Applicable - 3d 3D Graphics Tegra20/114/124/210 - 3d0 3D Graphics 0 Tegra30 - 3d1 3D Graphics 1 Tegra30 - aud Audio Tegra210 - dfd Debug Tegra210 - dis Display A Tegra114/124/210 - disb Display B Tegra114/124/210 - heg 2D Graphics Tegra30/114/124/210 - iram Internal RAM Tegra124/210 - mpe MPEG Encode All - nvdec NVIDIA Video Decode Engine Tegra210 - nvjpg NVIDIA JPEG Engine Tegra210 - pcie PCIE Tegra20/30/124/210 - sata SATA Tegra30/124/210 - sor Display interfaces Tegra124/210 - ve2 Video Encode Engine 2 Tegra210 - venc Video Encode Engine All - vdec Video Decode Engine Tegra20/30/114/124 - vic Video Imaging Compositor Tegra124/210 - xusba USB Partition A Tegra114/124/210 - xusbb USB Partition B Tegra114/124/210 - xusbc USB Partition C Tegra114/124/210 - -Required properties: - - clocks: Must contain an entry for each clock required by the PMC for - controlling a power-gate. See ../clocks/clock-bindings.txt for details. - - resets: Must contain an entry for each reset required by the PMC for - controlling a power-gate. See ../reset/reset.txt for details. - - #power-domain-cells: Must be 0. - -Example: - - pmc: pmc@7000e400 { - compatible = "nvidia,tegra210-pmc"; - reg = <0x0 0x7000e400 0x0 0x400>; - clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - - powergates { - pd_audio: aud { - clocks = <&tegra_car TEGRA210_CLK_APE>, - <&tegra_car TEGRA210_CLK_APB2APE>; - resets = <&tegra_car 198>; - #power-domain-cells = <0>; - }; - }; - }; - - -== Powergate Clients == - -Hardware blocks belonging to a power domain should contain a "power-domains" -property that is a phandle pointing to the corresponding powergate node. - -Example: - - adma: adma@702e2000 { - ... - power-domains = <&pd_audio>; - ... - }; - -== Pad Control == - -On Tegra SoCs a pad is a set of pins which are configured as a group. -The pin grouping is a fixed attribute of the hardware. The PMC can be -used to set pad power state and signaling voltage. A pad can be either -in active or power down mode. The support for power state and signaling -voltage configuration varies depending on the pad in question. 3.3 V and -1.8 V signaling voltages are supported on pins where software -controllable signaling voltage switching is available. - -The pad configuration state nodes are placed under the pmc node and they -are referred to by the pinctrl client properties. For more information -see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt. -The pad name should be used as the value of the pins property in pin -configuration nodes. - -The following pads are present on Tegra124 and Tegra132: -audio bb cam comp -csia csb cse dsi -dsib dsic dsid hdmi -hsic hv lvds mipi-bias -nand pex-bias pex-clk1 pex-clk2 -pex-cntrl sdmmc1 sdmmc3 sdmmc4 -sys_ddc uart usb0 usb1 -usb2 usb_bias - -The following pads are present on Tegra210: -audio audio-hv cam csia -csib csic csid csie -csif dbg debug-nonao dmic -dp dsi dsib dsic -dsid emmc emmc2 gpio -hdmi hsic lvds mipi-bias -pex-bias pex-clk1 pex-clk2 pex-cntrl -sdmmc1 sdmmc3 spi spi-hv -uart usb0 usb1 usb2 -usb3 usb-bias - -Required pin configuration properties: - - pins: Must contain name of the pad(s) to be configured. - -Optional pin configuration properties: - - low-power-enable: Configure the pad into power down mode - - low-power-disable: Configure the pad into active mode - - power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 - or TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. - The values are defined in - include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h. - -Note: The power state can be configured on all of the Tegra124 and - Tegra132 pads. None of the Tegra124 or Tegra132 pads support - signaling voltage switching. - -Note: All of the listed Tegra210 pads except pex-cntrl support power - state configuration. Signaling voltage switching is supported on - following Tegra210 pads: audio, audio-hv, cam, dbg, dmic, gpio, - pex-cntrl, sdmmc1, sdmmc3, spi, spi-hv, and uart. - -Pad configuration state example: - pmc: pmc@7000e400 { - compatible = "nvidia,tegra210-pmc"; - reg = <0x0 0x7000e400 0x0 0x400>; - clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - - ... - - sdmmc1_3v3: sdmmc1-3v3 { - pins = "sdmmc1"; - power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; - }; - - sdmmc1_1v8: sdmmc1-1v8 { - pins = "sdmmc1"; - power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; - }; - - hdmi_off: hdmi-off { - pins = "hdmi"; - low-power-enable; - } - - hdmi_on: hdmi-on { - pins = "hdmi"; - low-power-disable; - } - }; - -Pinctrl client example: - sdmmc1: sdhci@700b0000 { - ... - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; - pinctrl-0 = <&sdmmc1_3v3>; - pinctrl-1 = <&sdmmc1_1v8>; - }; - ... - sor@54540000 { - ... - pinctrl-0 = <&hdmi_off>; - pinctrl-1 = <&hdmi_on>; - pinctrl-names = "hdmi-on", "hdmi-off"; - }; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml new file mode 100644 index 000000000000..f17bb353f65e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -0,0 +1,354 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tegra Power Management Controller (PMC) + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jonathan Hunter <jonathanh@nvidia.com> + +properties: + compatible: + enum: + - nvidia,tegra20-pmc + - nvidia,tegra20-pmc + - nvidia,tegra30-pmc + - nvidia,tegra114-pmc + - nvidia,tegra124-pmc + - nvidia,tegra210-pmc + + reg: + maxItems: 1 + description: + Offset and length of the register set for the device. + + clock-names: + items: + - const: pclk + - const: clk32k_in + description: + Must includes entries pclk and clk32k_in. + pclk is the Tegra clock of that name and clk32k_in is 32KHz clock + input to Tegra. + + clocks: + maxItems: 2 + description: + Must contain an entry for each entry in clock-names. + See ../clocks/clocks-bindings.txt for details. + + '#clock-cells': + const: 1 + description: + Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. + PMC also has blink control which allows 32Khz clock output to + Tegra blink pad. + Consumer of PMC clock should specify the desired clock by having + the clock ID in its "clocks" phandle cell with pmc clock provider. + See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC + clock IDs. + + '#interrupt-cells': + const: 2 + description: + Specifies number of cells needed to encode an interrupt source. + The value must be 2. + + interrupt-controller: true + + nvidia,invert-interrupt: + $ref: /schemas/types.yaml#/definitions/flag + description: Inverts the PMU interrupt signal. + The PMU is an external Power Management Unit, whose interrupt output + signal is fed into the PMC. This signal is optionally inverted, and + then fed into the ARM GIC. The PMC is not involved in the detection + or handling of this interrupt signal, merely its inversion. + + nvidia,core-power-req-active-high: + $ref: /schemas/types.yaml#/definitions/flag + description: Core power request active-high. + + nvidia,sys-clock-req-active-high: + $ref: /schemas/types.yaml#/definitions/flag + description: System clock request active-high. + + nvidia,combined-power-req: + $ref: /schemas/types.yaml#/definitions/flag + description: combined power request for CPU and Core. + + nvidia,cpu-pwr-good-en: + $ref: /schemas/types.yaml#/definitions/flag + description: + CPU power good signal from external PMIC to PMC is enabled. + + nvidia,suspend-mode: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0, 1, 2] + description: + The suspend mode that the platform should use. + Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh + Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh + Mode 2 is for LP2, CPU voltage off + + nvidia,cpu-pwr-good-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: CPU power good time in uSec. + + nvidia,cpu-pwr-off-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: CPU power off time in uSec. + + nvidia,core-pwr-good-time: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + <Oscillator-stable-time Power-stable-time> + Core power good time in uSec. + + nvidia,core-pwr-off-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Core power off time in uSec. + + nvidia,lp0-vec: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + <start length> Starting address and length of LP0 vector. + The LP0 vector contains the warm boot code that is executed + by AVP when resuming from the LP0 state. + The AVP (Audio-Video Processor) is an ARM7 processor and + always being the first boot processor when chip is power on + or resume from deep sleep mode. When the system is resumed + from the deep sleep mode, the warm boot code will restore + some PLLs, clocks and then brings up CPU0 for resuming the + system. + + i2c-thermtrip: + type: object + description: + On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists, + hardware-triggered thermal reset will be enabled. + + properties: + nvidia,i2c-controller-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + ID of I2C controller to send poweroff command to PMU. + Valid values are described in section 9.2.148 + "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference + Manual. + + nvidia,bus-addr: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Bus address of the PMU on the I2C bus. + + nvidia,reg-addr: + $ref: /schemas/types.yaml#/definitions/uint32 + description: PMU I2C register address to issue poweroff command. + + nvidia,reg-data: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Poweroff command to write to PMU. + + nvidia,pinmux-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Pinmux used by the hardware when issuing Poweroff command. + Defaults to 0. Valid values are described in section 12.5.2 + "Pinmux Support" of the Tegra4 Technical Reference Manual. + + required: + - nvidia,i2c-controller-id + - nvidia,bus-addr + - nvidia,reg-addr + - nvidia,reg-data + + additionalProperties: false + + powergates: + type: object + description: | + This node contains a hierarchy of power domain nodes, which should + match the powergates on the Tegra SoC. Each powergate node + represents a power-domain on the Tegra SoC that can be power-gated + by the Tegra PMC. + Hardware blocks belonging to a power domain should contain + "power-domains" property that is a phandle pointing to corresponding + powergate node. + The name of the powergate node should be one of the below. Note that + not every powergate is applicable to all Tegra devices and the following + list shows which powergates are applicable to which devices. + Please refer to Tegra TRM for mode details on the powergate nodes to + use for each power-gate block inside Tegra. + Name Description Devices Applicable + 3d 3D Graphics Tegra20/114/124/210 + 3d0 3D Graphics 0 Tegra30 + 3d1 3D Graphics 1 Tegra30 + aud Audio Tegra210 + dfd Debug Tegra210 + dis Display A Tegra114/124/210 + disb Display B Tegra114/124/210 + heg 2D Graphics Tegra30/114/124/210 + iram Internal RAM Tegra124/210 + mpe MPEG Encode All + nvdec NVIDIA Video Decode Engine Tegra210 + nvjpg NVIDIA JPEG Engine Tegra210 + pcie PCIE Tegra20/30/124/210 + sata SATA Tegra30/124/210 + sor Display interfaces Tegra124/210 + ve2 Video Encode Engine 2 Tegra210 + venc Video Encode Engine All + vdec Video Decode Engine Tegra20/30/114/124 + vic Video Imaging Compositor Tegra124/210 + xusba USB Partition A Tegra114/124/210 + xusbb USB Partition B Tegra114/124/210 + xusbc USB Partition C Tegra114/124/210 + + patternProperties: + "^[a-z0-9]+$": + type: object + + patternProperties: + clocks: + minItems: 1 + maxItems: 8 + description: + Must contain an entry for each clock required by the PMC + for controlling a power-gate. + See ../clocks/clock-bindings.txt document for more details. + + resets: + minItems: 1 + maxItems: 8 + description: + Must contain an entry for each reset required by the PMC + for controlling a power-gate. + See ../reset/reset.txt for more details. + + '#power-domain-cells': + const: 0 + description: Must be 0. + + required: + - clocks + - resets + - '#power-domain-cells' + + additionalProperties: false + +patternProperties: + "^[a-f0-9]+-[a-f0-9]+$": + type: object + description: + This is a Pad configuration node. On Tegra SOCs a pad is a set of + pins which are configured as a group. The pin grouping is a fixed + attribute of the hardware. The PMC can be used to set pad power state + and signaling voltage. A pad can be either in active or power down mode. + The support for power state and signaling voltage configuration varies + depending on the pad in question. 3.3V and 1.8V signaling voltages + are supported on pins where software controllable signaling voltage + switching is available. + + The pad configuration state nodes are placed under the pmc node and they + are referred to by the pinctrl client properties. For more information + see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt. + The pad name should be used as the value of the pins property in pin + configuration nodes. + + The following pads are present on Tegra124 and Tegra132 + audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic, + hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl, + sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias. + + The following pads are present on Tegra210 + audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg, + debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi, + hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1, + sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias. + + properties: + pins: + $ref: /schemas/types.yaml#/definitions/string + description: Must contain name of the pad(s) to be configured. + + low-power-enable: + $ref: /schemas/types.yaml#/definitions/flag + description: Configure the pad into power down mode. + + low-power-disable: + $ref: /schemas/types.yaml#/definitions/flag + description: Configure the pad into active mode. + + power-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or + TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. + The values are defined in + include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h. + Power state can be configured on all Tegra124 and Tegra132 + pads. None of the Tegra124 or Tegra132 pads support signaling + voltage switching. + All of the listed Tegra210 pads except pex-cntrl support power + state configuration. Signaling voltage switching is supported + on below Tegra210 pads. + audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1, + sdmmc3, spi, spi-hv, and uart. + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + - clock-names + - clocks + - '#clock-cells' + +dependencies: + "nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"] + "nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"] + "nvidia,cpu-pwr-off-time": ["nvidia,cpu-pwr-good-time"] + +examples: + - | + + #include <dt-bindings/clock/tegra210-car.h> + #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> + #include <dt-bindings/soc/tegra-pmc.h> + + tegra_pmc: pmc@7000e400 { + compatible = "nvidia,tegra210-pmc"; + reg = <0x0 0x7000e400 0x0 0x400>; + clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; + + nvidia,invert-interrupt; + nvidia,suspend-mode = <0>; + nvidia,cpu-pwr-good-time = <0>; + nvidia,cpu-pwr-off-time = <0>; + nvidia,core-pwr-good-time = <4587 3876>; + nvidia,core-pwr-off-time = <39065>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + + powergates { + pd_audio: aud { + clocks = <&tegra_car TEGRA210_CLK_APE>, + <&tegra_car TEGRA210_CLK_APB2APE>; + resets = <&tegra_car 198>; + #power-domain-cells = <0>; + }; + + pd_xusbss: xusba { + clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; + resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; + #power-domain-cells = <0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/vexpress.txt b/Documentation/devicetree/bindings/arm/vexpress.txt deleted file mode 100644 index 39844cd0bcce..000000000000 --- a/Documentation/devicetree/bindings/arm/vexpress.txt +++ /dev/null @@ -1,229 +0,0 @@ -ARM Versatile Express boards family ------------------------------------ - -ARM's Versatile Express platform consists of a motherboard and one -or more daughterboards (tiles). The motherboard provides a set of -peripherals. Processor and RAM "live" on the tiles. - -The motherboard and each core tile should be described by a separate -Device Tree source file, with the tile's description including -the motherboard file using a /include/ directive. As the motherboard -can be initialized in one of two different configurations ("memory -maps"), care must be taken to include the correct one. - - -Root node ---------- - -Required properties in the root node: -- compatible value: - compatible = "arm,vexpress,<model>", "arm,vexpress"; - where <model> is the full tile model name (as used in the tile's - Technical Reference Manual), eg.: - - for Coretile Express A5x2 (V2P-CA5s): - compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; - - for Coretile Express A9x4 (V2P-CA9): - compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; - If a tile comes in several variants or can be used in more then one - configuration, the compatible value should be: - compatible = "arm,vexpress,<model>,<variant>", \ - "arm,vexpress,<model>", "arm,vexpress"; - eg: - - Coretile Express A15x2 (V2P-CA15) with Tech Chip 1: - compatible = "arm,vexpress,v2p-ca15,tc1", \ - "arm,vexpress,v2p-ca15", "arm,vexpress"; - - LogicTile Express 13MG (V2F-2XV6) running Cortex-A7 (3 cores) SMM: - compatible = "arm,vexpress,v2f-2xv6,ca7x3", \ - "arm,vexpress,v2f-2xv6", "arm,vexpress"; - -Optional properties in the root node: -- tile model name (use name from the tile's Technical Reference - Manual, eg. "V2P-CA5s") - model = "<model>"; -- tile's HBI number (unique ARM's board model ID, visible on the - PCB's silkscreen) in hexadecimal transcription: - arm,hbi = <0xhbi> - eg: - - for Coretile Express A5x2 (V2P-CA5s) HBI-0191: - arm,hbi = <0x191>; - - Coretile Express A9x4 (V2P-CA9) HBI-0225: - arm,hbi = <0x225>; - - -CPU nodes ---------- - -Top-level standard "cpus" node is required. It must contain a node -with device_type = "cpu" property for every available core, eg.: - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0>; - }; - }; - - -Configuration infrastructure ----------------------------- - -The platform has an elaborated configuration system, consisting of -microcontrollers residing on the mother- and daughterboards known -as Motherboard/Daughterboard Configuration Controller (MCC and DCC). -The controllers are responsible for the platform initialization -(reset generation, flash programming, FPGA bitfiles loading etc.) -but also control clock generators, voltage regulators, gather -environmental data like temperature, power consumption etc. Even -the video output switch (FPGA) is controlled that way. - -The controllers are not mapped into normal memory address space -and must be accessed through bridges - other devices capable -of generating transactions on the configuration bus. - -The nodes describing configuration controllers must define -the following properties: -- compatible value: - compatible = "arm,vexpress,config-bus"; -- bridge phandle: - arm,vexpress,config-bridge = <phandle>; -and children describing available functions. - - -Platform topology ------------------ - -As Versatile Express can be configured in number of physically -different setups, the device tree should describe platform topology. -Root node and main motherboard node must define the following -property, describing physical location of the children nodes: -- site number: - arm,vexpress,site = <number>; - where 0 means motherboard, 1 or 2 are daugtherboard sites, - 0xf means "master" site (site containing main CPU tile) -- when daughterboards are stacked on one site, their position - in the stack be be described with: - arm,vexpress,position = <number>; -- when describing tiles consisting more than one DCC, its number - can be described with: - arm,vexpress,dcc = <number>; - -Any of the numbers above defaults to zero if not defined in -the node or any of its parent. - - -Motherboard ------------ - -The motherboard description file provides a single "motherboard" node -using 2 address cells corresponding to the Static Memory Bus used -between the motherboard and the tile. The first cell defines the Chip -Select (CS) line number, the second cell address offset within the CS. -All interrupt lines between the motherboard and the tile are active -high and are described using single cell. - -Optional properties of the "motherboard" node: -- motherboard's memory map variant: - arm,v2m-memory-map = "<name>"; - where name is one of: - - "rs1" - for RS1 map (i.a. peripherals on CS3); this map is also - referred to as "ARM Cortex-A Series memory map": - arm,v2m-memory-map = "rs1"; - When this property is missing, the motherboard is using the original - memory map (also known as the "Legacy memory map", primarily used - with the original CoreTile Express A9x4) with peripherals on CS7. - -Motherboard .dtsi files provide a set of labelled peripherals that -can be used to obtain required phandle in the tile's "aliases" node: -- UARTs, note that the numbers correspond to the physical connectors - on the motherboard's back panel: - v2m_serial0, v2m_serial1, v2m_serial2 and v2m_serial3 -- I2C controllers: - v2m_i2c_dvi and v2m_i2c_pcie -- SP804 timers: - v2m_timer01 and v2m_timer23 - -The tile description should define a "smb" node, describing the -Static Memory Bus between the tile and motherboard. It must define -the following properties: -- "simple-bus" compatible value (to ensure creation of the children) - compatible = "simple-bus"; -- mapping of the SMB CS/offset addresses into main address space: - #address-cells = <2>; - #size-cells = <1>; - ranges = <...>; -- interrupts mapping: - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <...>; - - -Example of a VE tile description (simplified) ---------------------------------------------- - -/dts-v1/; - -/ { - model = "V2P-CA5s"; - arm,hbi = <0x225>; - arm,vexpress,site = <0xf>; - compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0>; - }; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x2c001000 0x1000>, - <0x2c000100 0x100>; - }; - - dcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - osc@0 { - compatible = "arm,vexpress-osc"; - }; - }; - - smb { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - /* CS0 is visible at 0x08000000 */ - ranges = <0 0 0x08000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - /* Active high IRQ 0 is connected to GIC's SPI0 */ - interrupt-map = <0 0 0 &gic 0 0 4>; - - /include/ "vexpress-v2m-rs1.dtsi" - }; -}; - diff --git a/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml b/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml new file mode 100644 index 000000000000..7b69831060d8 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/ata/renesas,rcar-sata.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Renesas R-Car Serial-ATA Interface + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,sata-r8a7779 # R-Car H1 + - items: + - enum: + - renesas,sata-r8a7790-es1 # R-Car H2 ES1 + - renesas,sata-r8a7790 # R-Car H2 other than ES1 + - renesas,sata-r8a7791 # R-Car M2-W + - renesas,sata-r8a7793 # R-Car M2-N + - const: renesas,rcar-gen2-sata # generic R-Car Gen2 + - items: + - enum: + - renesas,sata-r8a774b1 # RZ/G2N + - renesas,sata-r8a7795 # R-Car H3 + - renesas,sata-r8a77965 # R-Car M3-N + - const: renesas,rcar-gen3-sata # generic R-Car Gen3 or RZ/G2 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + iommus: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r8a7791-cpg-mssr.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/r8a7791-sysc.h> + + sata@ee300000 { + compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata"; + reg = <0xee300000 0x200000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 815>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 815>; + }; diff --git a/Documentation/devicetree/bindings/ata/sata_rcar.txt b/Documentation/devicetree/bindings/ata/sata_rcar.txt deleted file mode 100644 index a2fbdc91570d..000000000000 --- a/Documentation/devicetree/bindings/ata/sata_rcar.txt +++ /dev/null @@ -1,36 +0,0 @@ -* Renesas R-Car SATA - -Required properties: -- compatible : should contain one or more of the following: - - "renesas,sata-r8a774b1" for RZ/G2N - - "renesas,sata-r8a7779" for R-Car H1 - - "renesas,sata-r8a7790-es1" for R-Car H2 ES1 - - "renesas,sata-r8a7790" for R-Car H2 other than ES1 - - "renesas,sata-r8a7791" for R-Car M2-W - - "renesas,sata-r8a7793" for R-Car M2-N - - "renesas,sata-r8a7795" for R-Car H3 - - "renesas,sata-r8a77965" for R-Car M3-N - - "renesas,rcar-gen2-sata" for a generic R-Car Gen2 - compatible device - - "renesas,rcar-gen3-sata" for a generic R-Car Gen3 or - RZ/G2 compatible device - - "renesas,rcar-sata" is deprecated - - When compatible with the generic version nodes - must list the SoC-specific version corresponding - to the platform first followed by the generic - version. - -- reg : address and length of the SATA registers; -- interrupts : must consist of one interrupt specifier. -- clocks : must contain a reference to the functional clock. - -Example: - -sata0: sata@ee300000 { - compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata"; - reg = <0 0xee300000 0 0x2000>; - interrupt-parent = <&gic>; - interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7791_CLK_SATA0>; -}; diff --git a/Documentation/devicetree/bindings/bus/socionext,uniphier-system-bus.yaml b/Documentation/devicetree/bindings/bus/socionext,uniphier-system-bus.yaml new file mode 100644 index 000000000000..c4c9119e4a20 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/socionext,uniphier-system-bus.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier System Bus + +description: | + The UniPhier System Bus is an external bus that connects on-board devices to + the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and + some control signals. It supports up to 8 banks (chip selects). + + Before any access to the bus, the bus controller must be configured; the bus + controller registers provide the control for the translation from the offset + within each bank to the CPU-viewed address. The needed setup includes the + base address, the size of each bank. Optionally, some timing parameters can + be optimized for faster bus access. + +maintainers: + - Masahiro Yamada <yamada.masahiro@socionext.com> + +properties: + compatible: + const: socionext,uniphier-system-bus + + reg: + maxItems: 1 + + "#address-cells": + description: | + The first cell is the bank number (chip select). + The second cell is the address offset within the bank. + const: 2 + + "#size-cells": + const: 1 + + ranges: + description: | + Provide address translation from the System Bus to the parent bus. + + Note: + The address region(s) that can be assigned for the System Bus is + implementation defined. Some SoCs can use 0x00000000-0x0fffffff and + 0x40000000-0x4fffffff, while other SoCs only 0x40000000-0x4fffffff. + There might be additional limitations depending on SoCs and the boot mode. + The address translation is arbitrary as long as the banks are assigned in + the supported address space with the required alignment and they do not + overlap one another. + + For example, it is possible to map: + bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff + It is also possible to map: + bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff + There is no reason to stick to a particular translation mapping, but the + "ranges" property should provide a "reasonable" default that is known to + work. The software should initialize the bus controller according to it. + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + +examples: + - | + // In this example, + // - the Ethernet device is connected at the offset 0x01f00000 of CS1 and + // mapped to 0x43f00000 of the parent bus. + // - the UART device is connected at the offset 0x00200000 of CS5 and + // mapped to 0x46200000 of the parent bus. + + system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0x00000000 0x42000000 0x02000000>, + <5 0x00000000 0x46000000 0x01000000>; + + ethernet@1,01f00000 { + compatible = "smsc,lan9115"; + reg = <1 0x01f00000 0x1000>; + interrupts = <0 48 4>; + phy-mode = "mii"; + }; + + uart@5,00200000 { + compatible = "ns16550a"; + reg = <5 0x00200000 0x20>; + interrupts = <0 49 4>; + clock-frequency = <12288000>; + }; + }; diff --git a/Documentation/devicetree/bindings/bus/ti-sysc.txt b/Documentation/devicetree/bindings/bus/ti-sysc.txt index 233eb8294204..c984143d08d2 100644 --- a/Documentation/devicetree/bindings/bus/ti-sysc.txt +++ b/Documentation/devicetree/bindings/bus/ti-sysc.txt @@ -38,6 +38,7 @@ Required standard properties: "ti,sysc-dra7-mcasp" "ti,sysc-usb-host-fs" "ti,sysc-dra7-mcan" + "ti,sysc-pruss" - reg shall have register areas implemented for the interconnect target module in question such as revision, sysc and syss diff --git a/Documentation/devicetree/bindings/bus/uniphier-system-bus.txt b/Documentation/devicetree/bindings/bus/uniphier-system-bus.txt deleted file mode 100644 index 68ef80afff16..000000000000 --- a/Documentation/devicetree/bindings/bus/uniphier-system-bus.txt +++ /dev/null @@ -1,66 +0,0 @@ -UniPhier System Bus - -The UniPhier System Bus is an external bus that connects on-board devices to -the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and -some control signals. It supports up to 8 banks (chip selects). - -Before any access to the bus, the bus controller must be configured; the bus -controller registers provide the control for the translation from the offset -within each bank to the CPU-viewed address. The needed setup includes the base -address, the size of each bank. Optionally, some timing parameters can be -optimized for faster bus access. - -Required properties: -- compatible: should be "socionext,uniphier-system-bus". -- reg: offset and length of the register set for the bus controller device. -- #address-cells: should be 2. The first cell is the bank number (chip select). - The second cell is the address offset within the bank. -- #size-cells: should be 1. -- ranges: should provide a proper address translation from the System Bus to - the parent bus. - -Note: -The address region(s) that can be assigned for the System Bus is implementation -defined. Some SoCs can use 0x00000000-0x0fffffff and 0x40000000-0x4fffffff, -while other SoCs can only use 0x40000000-0x4fffffff. There might be additional -limitations depending on SoCs and the boot mode. The address translation is -arbitrary as long as the banks are assigned in the supported address space with -the required alignment and they do not overlap one another. -For example, it is possible to map: - bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff -It is also possible to map: - bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff -There is no reason to stick to a particular translation mapping, but the -"ranges" property should provide a "reasonable" default that is known to work. -The software should initialize the bus controller according to it. - -Example: - - system-bus { - compatible = "socionext,uniphier-system-bus"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <1 0x00000000 0x42000000 0x02000000 - 5 0x00000000 0x46000000 0x01000000>; - - ethernet@1,01f00000 { - compatible = "smsc,lan9115"; - reg = <1 0x01f00000 0x1000>; - interrupts = <0 48 4> - phy-mode = "mii"; - }; - - uart@5,00200000 { - compatible = "ns16550a"; - reg = <5 0x00200000 0x20>; - interrupts = <0 49 4> - clock-frequency = <12288000>; - }; - }; - -In this example, - - the Ethernet device is connected at the offset 0x01f00000 of CS1 and - mapped to 0x43f00000 of the parent bus. - - the UART device is connected at the offset 0x00200000 of CS5 and - mapped to 0x46200000 of the parent bus. diff --git a/Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml b/Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml new file mode 100644 index 000000000000..6d7396ab8bee --- /dev/null +++ b/Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/chrome/google,cros-ec-typec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google Chrome OS EC(Embedded Controller) Type C port driver. + +maintainers: + - Benson Leung <bleung@chromium.org> + - Prashant Malani <pmalani@chromium.org> + +description: + Chrome OS devices have an Embedded Controller(EC) which has access to + Type C port state. This node is intended to allow the host to read and + control the Type C ports. The node for this device should be under a + cros-ec node like google,cros-ec-spi. + +properties: + compatible: + const: google,cros-ec-typec + + connector: + $ref: /schemas/connector/usb-connector.yaml# + +required: + - compatible + +examples: + - |+ + spi0 { + #address-cells = <1>; + #size-cells = <0>; + + cros_ec: ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0>; + + typec { + compatible = "google,cros-ec-typec"; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + try-power-role = "source"; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml b/Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml new file mode 100644 index 000000000000..444aeea27db8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/arm,syscon-icst.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM System Controller ICST Clocks + +maintainers: + - Linus Walleij <linusw@kernel.org> + +description: | + The ICS525 and ICS307 oscillators are produced by Integrated + Devices Technology (IDT). ARM integrated these oscillators deeply into their + reference designs by adding special control registers that manage such + oscillators to their system controllers. + + The various ARM system controllers contain logic to serialize and initialize + an ICST clock request after a write to the 32 bit register at an offset + into the system controller. Furthermore, to even be able to alter one of + these frequencies, the system controller must first be unlocked by + writing a special token to another offset in the system controller. + + Some ARM hardware contain special versions of the serial interface that only + connects the low 8 bits of the VDW (missing one bit), hard-wires RDW to + different values and sometimes also hard-wires the output divider. They + therefore have special compatible strings as per this table (the OD value is + the value on the pins, not the resulting output divider). + + In the core modules and logic tiles, the ICST is a configurable clock fed + from a 24 MHz clock on the motherboard (usually the main crystal) used for + generating e.g. video clocks. It is located on the core module and there is + only one of these. This clock node must be a subnode of the core module. + + Hardware variant RDW OD VDW + + Integrator/AP 22 1 Bit 8 0, rest variable + integratorap-cm + + Integrator/AP 46 3 Bit 8 0, rest variable + integratorap-sys + + Integrator/AP 22 or 1 17 or (33 or 25 MHz) + integratorap-pci 14 1 14 + + Integrator/CP 22 variable Bit 8 0, rest variable + integratorcp-cm-core + + Integrator/CP 22 variable Bit 8 0, rest variable + integratorcp-cm-mem + + The ICST oscillator must be provided inside a system controller node. + +properties: + "#clock-cells": + const: 0 + + compatible: + enum: + - arm,syscon-icst525 + - arm,syscon-icst307 + - arm,syscon-icst525-integratorap-cm + - arm,syscon-icst525-integratorap-sys + - arm,syscon-icst525-integratorap-pci + - arm,syscon-icst525-integratorcp-cm-core + - arm,syscon-icst525-integratorcp-cm-mem + - arm,integrator-cm-auxosc + - arm,versatile-cm-auxosc + - arm,impd-vco1 + - arm,impd-vco2 + + clocks: + description: Parent clock for the ICST VCO + maxItems: 1 + + clock-output-names: + maxItems: 1 + + lock-offset: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: Offset to the unlocking register for the oscillator + + vco-offset: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: Offset to the VCO register for the oscillator + +required: + - "#clock-cells" + - compatible + - clocks + +examples: + - | + vco1: clock { + compatible = "arm,impd1-vco1"; + #clock-cells = <0>; + lock-offset = <0x08>; + vco-offset = <0x00>; + clocks = <&sysclk>; + clock-output-names = "IM-PD1-VCO1"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/arm-integrator.txt b/Documentation/devicetree/bindings/clock/arm-integrator.txt deleted file mode 100644 index 11f5f95f571b..000000000000 --- a/Documentation/devicetree/bindings/clock/arm-integrator.txt +++ /dev/null @@ -1,34 +0,0 @@ -Clock bindings for ARM Integrator and Versatile Core Module clocks - -Auxiliary Oscillator Clock - -This is a configurable clock fed from a 24 MHz chrystal, -used for generating e.g. video clocks. It is located on the -core module and there is only one of these. - -This clock node *must* be a subnode of the core module, since -it obtains the base address for it's address range from its -parent node. - - -Required properties: -- compatible: must be "arm,integrator-cm-auxosc" or "arm,versatile-cm-auxosc" -- #clock-cells: must be <0> - -Optional properties: -- clocks: parent clock(s) - -Example: - -core-module@10000000 { - xtal24mhz: xtal24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - auxosc: cm_aux_osc@25M { - #clock-cells = <0>; - compatible = "arm,integrator-cm-auxosc"; - clocks = <&xtal24mhz>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt b/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt deleted file mode 100644 index 4cd81742038f..000000000000 --- a/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt +++ /dev/null @@ -1,70 +0,0 @@ -ARM System Controller ICST clocks - -The ICS525 and ICS307 oscillators are produced by Integrated Devices -Technology (IDT). ARM integrated these oscillators deeply into their -reference designs by adding special control registers that manage such -oscillators to their system controllers. - -The various ARM system controllers contain logic to serialize and initialize -an ICST clock request after a write to the 32 bit register at an offset -into the system controller. Furthermore, to even be able to alter one of -these frequencies, the system controller must first be unlocked by -writing a special token to another offset in the system controller. - -Some ARM hardware contain special versions of the serial interface that only -connects the low 8 bits of the VDW (missing one bit), hardwires RDW to -different values and sometimes also hardwire the output divider. They -therefore have special compatible strings as per this table (the OD value is -the value on the pins, not the resulting output divider): - -Hardware variant: RDW OD VDW - -Integrator/AP 22 1 Bit 8 0, rest variable -integratorap-cm - -Integrator/AP 46 3 Bit 8 0, rest variable -integratorap-sys - -Integrator/AP 22 or 1 17 or (33 or 25 MHz) -integratorap-pci 14 1 14 - -Integrator/CP 22 variable Bit 8 0, rest variable -integratorcp-cm-core - -Integrator/CP 22 variable Bit 8 0, rest variable -integratorcp-cm-mem - -The ICST oscillator must be provided inside a system controller node. - -Required properties: -- compatible: must be one of - "arm,syscon-icst525" - "arm,syscon-icst307" - "arm,syscon-icst525-integratorap-cm" - "arm,syscon-icst525-integratorap-sys" - "arm,syscon-icst525-integratorap-pci" - "arm,syscon-icst525-integratorcp-cm-core" - "arm,syscon-icst525-integratorcp-cm-mem" -- lock-offset: the offset address into the system controller where the - unlocking register is located -- vco-offset: the offset address into the system controller where the - ICST control register is located (even 32 bit address) -- #clock-cells: must be <0> -- clocks: parent clock, since the ICST needs a parent clock to derive its - frequency from, this attribute is compulsory. - -Example: - -syscon: syscon@10000000 { - compatible = "syscon"; - reg = <0x10000000 0x1000>; - - oscclk0: osc0@c { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x0c>; - clocks = <&xtal24mhz>; - }; - (...) -}; diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt b/Documentation/devicetree/bindings/clock/clock-bindings.txt index b646bbcf7f92..8a55fdcf96ee 100644 --- a/Documentation/devicetree/bindings/clock/clock-bindings.txt +++ b/Documentation/devicetree/bindings/clock/clock-bindings.txt @@ -94,7 +94,7 @@ clock is connected to output 0 of the &ref. /* external oscillator */ osc: oscillator { compatible = "fixed-clock"; - #clock-cells = <1>; + #clock-cells = <0>; clock-frequency = <32678>; clock-output-names = "osc"; }; diff --git a/Documentation/devicetree/bindings/clock/fsl,plldig.yaml b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml index c8350030b374..a203d5d498db 100644 --- a/Documentation/devicetree/bindings/clock/fsl,plldig.yaml +++ b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml @@ -21,6 +21,9 @@ properties: reg: maxItems: 1 + clocks: + maxItems: 1 + '#clock-cells': const: 0 @@ -41,6 +44,8 @@ required: - clocks - '#clock-cells' +additionalProperties: false + examples: # Display PIXEL Clock node: - | diff --git a/Documentation/devicetree/bindings/clock/imx8mm-clock.txt b/Documentation/devicetree/bindings/clock/imx8mm-clock.txt deleted file mode 100644 index 8e4ab9e619a1..000000000000 --- a/Documentation/devicetree/bindings/clock/imx8mm-clock.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Clock bindings for NXP i.MX8M Mini - -Required properties: -- compatible: Should be "fsl,imx8mm-ccm" -- reg: Address and length of the register set -- #clock-cells: Should be <1> -- clocks: list of clock specifiers, must contain an entry for each required - entry in clock-names -- clock-names: should include the following entries: - - "osc_32k" - - "osc_24m" - - "clk_ext1" - - "clk_ext2" - - "clk_ext3" - - "clk_ext4" - -clk: clock-controller@30380000 { - compatible = "fsl,imx8mm-ccm"; - reg = <0x0 0x30380000 0x0 0x10000>; - #clock-cells = <1>; - clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; - clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; -}; - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mm-clock.h -for the full list of i.MX8M Mini clock IDs. diff --git a/Documentation/devicetree/bindings/clock/imx8mm-clock.yaml b/Documentation/devicetree/bindings/clock/imx8mm-clock.yaml new file mode 100644 index 000000000000..ec830db1367b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx8mm-clock.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx8mm-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8M Mini Clock Control Module Binding + +maintainers: + - Anson Huang <Anson.Huang@nxp.com> + +description: | + NXP i.MX8M Mini clock control module is an integrated clock controller, which + generates and supplies to all modules. + +properties: + compatible: + const: fsl,imx8mm-ccm + + reg: + maxItems: 1 + + clocks: + items: + - description: 32k osc + - description: 24m osc + - description: ext1 clock input + - description: ext2 clock input + - description: ext3 clock input + - description: ext4 clock input + + clock-names: + items: + - const: osc_32k + - const: osc_24m + - const: clk_ext1 + - const: clk_ext2 + - const: clk_ext3 + - const: clk_ext4 + + '#clock-cells': + const: 1 + description: + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mm-clock.h + for the full list of i.MX8M Mini clock IDs. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +examples: + # Clock Control Module node: + - | + clk: clock-controller@30380000 { + compatible = "fsl,imx8mm-ccm"; + reg = <0x30380000 0x10000>; + #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, + <&clk_ext3>, <&clk_ext4>; + clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", + "clk_ext3", "clk_ext4"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml b/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml index cd0b8a341321..bdaa29616ab1 100644 --- a/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml @@ -40,7 +40,7 @@ properties: '#clock-cells': const: 1 - description: | + description: The clock consumer should specify the desired clock by having the clock ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mn-clock.h for the full list of i.MX8M Nano clock IDs. @@ -52,12 +52,14 @@ required: - clock-names - '#clock-cells' +additionalProperties: false + examples: # Clock Control Module node: - | clk: clock-controller@30380000 { compatible = "fsl,imx8mn-ccm"; - reg = <0x0 0x30380000 0x0 0x10000>; + reg = <0x30380000 0x10000>; #clock-cells = <1>; clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, <&clk_ext3>, <&clk_ext4>; @@ -65,48 +67,4 @@ examples: "clk_ext2", "clk_ext3", "clk_ext4"; }; - # Required external clocks for Clock Control Module node: - - | - osc_32k: clock-osc-32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "osc_32k"; - }; - - osc_24m: clock-osc-24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc_24m"; - }; - - clk_ext1: clock-ext1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext1"; - }; - - clk_ext2: clock-ext2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext2"; - }; - - clk_ext3: clock-ext3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext3"; - }; - - clk_ext4: clock-ext4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency= <133000000>; - clock-output-names = "clk_ext4"; - }; - ... diff --git a/Documentation/devicetree/bindings/clock/imx8mp-clock.yaml b/Documentation/devicetree/bindings/clock/imx8mp-clock.yaml index 89aee63c9019..4351a1dbb4f7 100644 --- a/Documentation/devicetree/bindings/clock/imx8mp-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx8mp-clock.yaml @@ -52,6 +52,8 @@ required: - clock-names - '#clock-cells' +additionalProperties: false + examples: # Clock Control Module node: - | diff --git a/Documentation/devicetree/bindings/clock/imx8mq-clock.txt b/Documentation/devicetree/bindings/clock/imx8mq-clock.txt deleted file mode 100644 index 52de8263e012..000000000000 --- a/Documentation/devicetree/bindings/clock/imx8mq-clock.txt +++ /dev/null @@ -1,20 +0,0 @@ -* Clock bindings for NXP i.MX8M Quad - -Required properties: -- compatible: Should be "fsl,imx8mq-ccm" -- reg: Address and length of the register set -- #clock-cells: Should be <1> -- clocks: list of clock specifiers, must contain an entry for each required - entry in clock-names -- clock-names: should include the following entries: - - "ckil" - - "osc_25m" - - "osc_27m" - - "clk_ext1" - - "clk_ext2" - - "clk_ext3" - - "clk_ext4" - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mq-clock.h -for the full list of i.MX8M Quad clock IDs. diff --git a/Documentation/devicetree/bindings/clock/imx8mq-clock.yaml b/Documentation/devicetree/bindings/clock/imx8mq-clock.yaml new file mode 100644 index 000000000000..05d7d1471e0c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx8mq-clock.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx8mq-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8M Quad Clock Control Module Binding + +maintainers: + - Anson Huang <Anson.Huang@nxp.com> + +description: | + NXP i.MX8M Quad clock control module is an integrated clock controller, which + generates and supplies to all modules. + +properties: + compatible: + const: fsl,imx8mq-ccm + + reg: + maxItems: 1 + + clocks: + items: + - description: 32k osc + - description: 25m osc + - description: 27m osc + - description: ext1 clock input + - description: ext2 clock input + - description: ext3 clock input + - description: ext4 clock input + + clock-names: + items: + - const: ckil + - const: osc_25m + - const: osc_27m + - const: clk_ext1 + - const: clk_ext2 + - const: clk_ext3 + - const: clk_ext4 + + '#clock-cells': + const: 1 + description: + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mq-clock.h + for the full list of i.MX8M Quad clock IDs. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +examples: + # Clock Control Module node: + - | + clk: clock-controller@30380000 { + compatible = "fsl,imx8mq-ccm"; + reg = <0x30380000 0x10000>; + #clock-cells = <1>; + clocks = <&ckil>, <&osc_25m>, <&osc_27m>, + <&clk_ext1>, <&clk_ext2>, + <&clk_ext3>, <&clk_ext4>; + clock-names = "ckil", "osc_25m", "osc_27m", + "clk_ext1", "clk_ext2", + "clk_ext3", "clk_ext4"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/marvell,mmp2-clock.yaml b/Documentation/devicetree/bindings/clock/marvell,mmp2-clock.yaml new file mode 100644 index 000000000000..e2b6ac96bbcb --- /dev/null +++ b/Documentation/devicetree/bindings/clock/marvell,mmp2-clock.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/marvell,mmp2-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell MMP2 and MMP3 Clock Controller + +maintainers: + - Lubomir Rintel <lkundrak@v3.sk> + +description: | + The clock subsystem on MMP2 or MMP3 generates and supplies clock to various + controllers within the SoC. + + Each clock is assigned an identifier and client nodes use this identifier + to specify the clock which they consume. + + All these identifiers could be found in <dt-bindings/clock/marvell,mmp2.h>. + +properties: + compatible: + enum: + - marvell,mmp2-clock # controller compatible with MMP2 SoC + - marvell,mmp3-clock # controller compatible with MMP3 SoC + + reg: + items: + - description: MPMU register region + - description: APMU register region + - description: APBC register region + + reg-names: + items: + - const: mpmu + - const: apmu + - const: apbc + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - reg-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + clock-controller@d4050000 { + compatible = "marvell,mmp2-clock"; + reg = <0xd4050000 0x1000>, + <0xd4282800 0x400>, + <0xd4015000 0x1000>; + reg-names = "mpmu", "apmu", "apbc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/marvell,mmp2.txt b/Documentation/devicetree/bindings/clock/marvell,mmp2.txt deleted file mode 100644 index 23b52dc02266..000000000000 --- a/Documentation/devicetree/bindings/clock/marvell,mmp2.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Marvell MMP2 Clock Controller - -The MMP2 clock subsystem generates and supplies clock to various -controllers within the MMP2 SoC. - -Required Properties: - -- compatible: should be one of the following. - - "marvell,mmp2-clock" - controller compatible with MMP2 SoC. - -- reg: physical base address of the clock subsystem and length of memory mapped - region. There are 3 places in SOC has clock control logic: - "mpmu", "apmu", "apbc". So three reg spaces need to be defined. - -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Each clock is assigned an identifier and client nodes use this identifier -to specify the clock which they consume. - -All these identifiers could be found in <dt-bindings/clock/marvell,mmp2.h>. diff --git a/Documentation/devicetree/bindings/clock/milbeaut-clock.yaml b/Documentation/devicetree/bindings/clock/milbeaut-clock.yaml index f0b804a7f096..0e8b07710451 100644 --- a/Documentation/devicetree/bindings/clock/milbeaut-clock.yaml +++ b/Documentation/devicetree/bindings/clock/milbeaut-clock.yaml @@ -35,6 +35,8 @@ required: - clocks - '#clock-cells' +additionalProperties: false + examples: # Clock controller node: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml index 3647007f82ca..eacccc88bbf6 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml @@ -68,6 +68,8 @@ required: - nvmem-cell-names - '#thermal-sensor-cells' +additionalProperties: false + examples: - | clock-controller@900000 { diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml index 89c6e070e7ac..98572b4a9b60 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml @@ -40,6 +40,8 @@ required: - '#clock-cells' - '#reset-cells' +additionalProperties: false + examples: - | clock-controller@1800000 { diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml index 18e4e77b8cfa..5a5b2214f0ca 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml @@ -56,6 +56,8 @@ required: - '#reset-cells' - '#power-domain-cells' +additionalProperties: false + examples: - | clock-controller@300000 { diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml index 1d3cae980471..a0bb713929b0 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml @@ -66,6 +66,8 @@ required: - '#reset-cells' - '#power-domain-cells' +additionalProperties: false + examples: - | #include <dt-bindings/clock/qcom,rpmcc.h> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml index 8cdece395eba..ce06f3f8c3e3 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml @@ -40,6 +40,8 @@ required: - '#clock-cells' - '#reset-cells' +additionalProperties: false + examples: - | clock-controller@1800000 { diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml index ee4f968e2909..a345320e0e49 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml @@ -58,6 +58,8 @@ required: - '#reset-cells' - '#power-domain-cells' +additionalProperties: false + examples: - | #include <dt-bindings/clock/qcom,rpmh.h> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml index 888e9a708390..36f3b3668ced 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml @@ -56,6 +56,8 @@ required: - '#reset-cells' - '#power-domain-cells' +additionalProperties: false + examples: - | #include <dt-bindings/clock/qcom,rpmh.h> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml new file mode 100644 index 000000000000..2c40a8aa9815 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8250.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for SM8250 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on SM8250. + + See also: + - dt-bindings/clock/qcom,gcc-sm8250.h + +properties: + compatible: + const: qcom,gcc-sm8250 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + + clock-names: + items: + - const: bi_tcxo + - const: sleep_clk + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + protected-clocks: + description: + Protected clock specifier list as per common clock binding. + +required: + - compatible + - clocks + - clock-names + - reg + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,gcc-sm8250"; + reg = <0 0x00100000 0 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml index d18f8ab9eeee..e533bb0cfd2b 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml @@ -74,6 +74,8 @@ required: - '#reset-cells' - '#power-domain-cells' +additionalProperties: false + examples: # Example for GCC for MSM8960: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml index 85518494ce43..f684fe67db84 100644 --- a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml @@ -74,6 +74,8 @@ required: - '#reset-cells' - '#power-domain-cells' +additionalProperties: false + if: properties: compatible: diff --git a/Documentation/devicetree/bindings/clock/qcom,msm8998-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,msm8998-gpucc.yaml index 7d853c1a85e5..d747bb58f0a7 100644 --- a/Documentation/devicetree/bindings/clock/qcom,msm8998-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,msm8998-gpucc.yaml @@ -50,6 +50,8 @@ required: - '#reset-cells' - '#power-domain-cells' +additionalProperties: false + examples: - | #include <dt-bindings/clock/qcom,gcc-msm8998.h> diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt index 944719bd586f..90a1349bc713 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt @@ -14,7 +14,9 @@ Required properties : "qcom,rpmcc-apq8060", "qcom,rpmcc" "qcom,rpmcc-msm8916", "qcom,rpmcc" "qcom,rpmcc-msm8974", "qcom,rpmcc" + "qcom,rpmcc-msm8976", "qcom,rpmcc" "qcom,rpmcc-apq8064", "qcom,rpmcc" + "qcom,rpmcc-ipq806x", "qcom,rpmcc" "qcom,rpmcc-msm8996", "qcom,rpmcc" "qcom,rpmcc-msm8998", "qcom,rpmcc" "qcom,rpmcc-qcs404", "qcom,rpmcc" diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index 2cd158f13bab..a46a3a799a70 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -20,6 +20,7 @@ properties: - qcom,sc7180-rpmh-clk - qcom,sdm845-rpmh-clk - qcom,sm8150-rpmh-clk + - qcom,sm8250-rpmh-clk clocks: maxItems: 1 @@ -35,6 +36,8 @@ required: - compatible - '#clock-cells' +additionalProperties: false + examples: # Example for GCC for SDM845: The below node should be defined inside # &apps_rsc node. diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml index 0429062f1585..58cdfd5924d3 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml @@ -58,6 +58,8 @@ required: - '#reset-cells' - '#power-domain-cells' +additionalProperties: false + examples: - | #include <dt-bindings/clock/qcom,gcc-sc7180.h> diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7180-gpucc.yaml index 5785192cc4be..8635e35fd3f0 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc7180-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc7180-gpucc.yaml @@ -52,6 +52,8 @@ required: - '#reset-cells' - '#power-domain-cells' +additionalProperties: false + examples: - | #include <dt-bindings/clock/qcom,gcc-sc7180.h> diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-mss.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7180-mss.yaml new file mode 100644 index 000000000000..0dd5d25ae7d7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc7180-mss.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7180-mss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Modem Clock Controller Binding for SC7180 + +maintainers: + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm modem clock control module which supports the clocks on SC7180. + + See also: + - dt-bindings/clock/qcom,mss-sc7180.h + +properties: + compatible: + const: qcom,sc7180-mss + + clocks: + items: + - description: gcc_mss_mfab_axi clock from GCC + - description: gcc_mss_nav_axi clock from GCC + - description: gcc_mss_cfg_ahb clock from GCC + + clock-names: + items: + - const: gcc_mss_mfab_axis + - const: gcc_mss_nav_axi + - const: cfg_ahb + + '#clock-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sc7180.h> + clock-controller@41a8000 { + compatible = "qcom,sc7180-mss"; + reg = <0 0x041a8000 0 0x8000>; + clocks = <&gcc GCC_MSS_MFAB_AXIS_CLK>, + <&gcc GCC_MSS_NAV_AXI_CLK>, + <&gcc GCC_MSS_CFG_AHB_CLK>; + clock-names = "gcc_mss_mfab_axis", + "gcc_mss_nav_axi", + "cfg_ahb"; + #clock-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7180-videocc.yaml index 31df901884ac..0071b9701960 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc7180-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc7180-videocc.yaml @@ -48,6 +48,8 @@ required: - '#reset-cells' - '#power-domain-cells' +additionalProperties: false + examples: - | #include <dt-bindings/clock/qcom,rpmh.h> diff --git a/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml index 89269ddfbdcd..ad47d747a3e4 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml @@ -67,6 +67,8 @@ required: - '#reset-cells' - '#power-domain-cells' +additionalProperties: false + examples: - | #include <dt-bindings/clock/qcom,gcc-sdm845.h> diff --git a/Documentation/devicetree/bindings/clock/qcom,sdm845-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdm845-gpucc.yaml index bac04f1c5d79..7a052ac5dc00 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sdm845-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sdm845-gpucc.yaml @@ -52,6 +52,8 @@ required: - '#reset-cells' - '#power-domain-cells' +additionalProperties: false + examples: - | #include <dt-bindings/clock/qcom,gcc-sdm845.h> diff --git a/Documentation/devicetree/bindings/clock/qcom,sdm845-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdm845-videocc.yaml index 9d216c0f11d4..2a6a81ab0318 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sdm845-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sdm845-videocc.yaml @@ -48,6 +48,8 @@ required: - '#reset-cells' - '#power-domain-cells' +additionalProperties: false + examples: - | #include <dt-bindings/clock/qcom,rpmh.h> diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt deleted file mode 100644 index f4d153f24a0f..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt +++ /dev/null @@ -1,100 +0,0 @@ -* Renesas Clock Pulse Generator / Module Standby and Software Reset - -On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator) -and MSSR (Module Standby and Software Reset) blocks are intimately connected, -and share the same register block. - -They provide the following functionalities: - - The CPG block generates various core clocks, - - The MSSR block provides two functions: - 1. Module Standby, providing a Clock Domain to control the clock supply - to individual SoC devices, - 2. Reset Control, to perform a software reset of individual SoC devices. - -Required Properties: - - compatible: Must be one of: - - "renesas,r7s9210-cpg-mssr" for the r7s9210 SoC (RZ/A2) - - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M) - - "renesas,r8a7744-cpg-mssr" for the r8a7744 SoC (RZ/G1N) - - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E) - - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C) - - "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M) - - "renesas,r8a774b1-cpg-mssr" for the r8a774b1 SoC (RZ/G2N) - - "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E) - - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2) - - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W) - - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H) - - "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N) - - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2) - - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3) - - "renesas,r8a7796-cpg-mssr" for the r8a77960 SoC (R-Car M3-W) - - "renesas,r8a77961-cpg-mssr" for the r8a77961 SoC (R-Car M3-W+) - - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N) - - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M) - - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H) - - "renesas,r8a77990-cpg-mssr" for the r8a77990 SoC (R-Car E3) - - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3) - - - reg: Base address and length of the memory resource used by the CPG/MSSR - block - - - clocks: References to external parent clocks, one entry for each entry in - clock-names - - clock-names: List of external parent clock names. Valid names are: - - "extal" (r7s9210, r8a7743, r8a7744, r8a7745, r8a77470, r8a774a1, - r8a774b1, r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793, - r8a7794, r8a7795, r8a77960, r8a77961, r8a77965, r8a77970, - r8a77980, r8a77990, r8a77995) - - "extalr" (r8a774a1, r8a774b1, r8a7795, r8a77960, r8a77961, r8a77965, - r8a77970, r8a77980) - - "usb_extal" (r8a7743, r8a7744, r8a7745, r8a77470, r8a7790, r8a7791, - r8a7793, r8a7794) - - - #clock-cells: Must be 2 - - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" - and a core clock reference, as defined in - <dt-bindings/clock/*-cpg-mssr.h>. - - For module clocks, the two clock specifier cells must be "CPG_MOD" and - a module number, as defined in the datasheet. - - - #power-domain-cells: Must be 0 - - SoC devices that are part of the CPG/MSSR Clock Domain and can be - power-managed through Module Standby should refer to the CPG device - node in their "power-domains" property, as documented by the generic PM - Domain bindings in - Documentation/devicetree/bindings/power/power-domain.yaml. - - - #reset-cells: Must be 1 - - The single reset specifier cell must be the module number, as defined - in the datasheet. - - -Examples --------- - - - CPG device node: - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7795-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - - - CPG/MSSR Clock Domain member device node: - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a7795", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 310>; - clock-names = "fck"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>; - dma-names = "tx", "rx"; - power-domains = <&cpg>; - resets = <&cpg 310>; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml new file mode 100644 index 000000000000..9cd102e5fed5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Renesas Clock Pulse Generator / Module Standby and Software Reset + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + +description: | + On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator) + and MSSR (Module Standby and Software Reset) blocks are intimately connected, + and share the same register block. + + They provide the following functionalities: + - The CPG block generates various core clocks, + - The MSSR block provides two functions: + 1. Module Standby, providing a Clock Domain to control the clock supply + to individual SoC devices, + 2. Reset Control, to perform a software reset of individual SoC devices. + +properties: + compatible: + enum: + - renesas,r7s9210-cpg-mssr # RZ/A2 + - renesas,r8a7743-cpg-mssr # RZ/G1M + - renesas,r8a7744-cpg-mssr # RZ/G1N + - renesas,r8a7745-cpg-mssr # RZ/G1E + - renesas,r8a77470-cpg-mssr # RZ/G1C + - renesas,r8a774a1-cpg-mssr # RZ/G2M + - renesas,r8a774b1-cpg-mssr # RZ/G2N + - renesas,r8a774c0-cpg-mssr # RZ/G2E + - renesas,r8a7790-cpg-mssr # R-Car H2 + - renesas,r8a7791-cpg-mssr # R-Car M2-W + - renesas,r8a7792-cpg-mssr # R-Car V2H + - renesas,r8a7793-cpg-mssr # R-Car M2-N + - renesas,r8a7794-cpg-mssr # R-Car E2 + - renesas,r8a7795-cpg-mssr # R-Car H3 + - renesas,r8a7796-cpg-mssr # R-Car M3-W + - renesas,r8a77961-cpg-mssr # R-Car M3-W+ + - renesas,r8a77965-cpg-mssr # R-Car M3-N + - renesas,r8a77970-cpg-mssr # R-Car V3M + - renesas,r8a77980-cpg-mssr # R-Car V3H + - renesas,r8a77990-cpg-mssr # R-Car E3 + - renesas,r8a77995-cpg-mssr # R-Car D3 + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + items: + enum: + - extal # All + - extalr # Most R-Car Gen3 and RZ/G2 + - usb_extal # Most R-Car Gen2 and RZ/G1 + + '#clock-cells': + description: | + - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" + and a core clock reference, as defined in + <dt-bindings/clock/*-cpg-mssr.h> + - For module clocks, the two clock specifier cells must be "CPG_MOD" and + a module number, as defined in the datasheet. + const: 2 + + '#power-domain-cells': + description: + SoC devices that are part of the CPG/MSSR Clock Domain and can be + power-managed through Module Standby should refer to the CPG device node + in their "power-domains" property, as documented by the generic PM Domain + bindings in Documentation/devicetree/bindings/power/power-domain.yaml. + const: 0 + + '#reset-cells': + description: + The single reset specifier cell must be the module number, as defined in + the datasheet. + const: 1 + +if: + not: + properties: + compatible: + items: + enum: + - renesas,r7s9210-cpg-mssr +then: + required: + - '#reset-cells' + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7795-cpg-mssr"; + reg = <0xe6150000 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt index 83f6c6a7c41c..4bf6f53bd95e 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt +++ b/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt @@ -38,10 +38,17 @@ Required properties: - reg: offset and length of the USB 2.0 clock selector register block. - clocks: A list of phandles and specifier pairs. - clock-names: Name of the clocks. - - The functional clock must be "ehci_ohci" + - The functional clock of USB 2.0 host side must be "ehci_ohci" + - The functional clock of HS-USB side must be "hs-usb-if" - The USB_EXTAL clock pin must be "usb_extal" - The USB_XTAL clock pin must be "usb_xtal" - #clock-cells: Must be 0 +- power-domains: A phandle and symbolic PM domain specifier. + See power/renesas,rcar-sysc.yaml. +- resets: A list of phandles and specifier pairs. +- reset-names: Name of the resets. + - The reset of USB 2.0 host side must be "ehci_ohci" + - The reset of HS-USB side must be "hs-usb-if" Example (R-Car H3): @@ -49,7 +56,11 @@ Example (R-Car H3): compatible = "renesas,r8a7795-rcar-usb2-clock-sel", "renesas,rcar-gen3-usb2-clock-sel"; reg = <0 0xe6590630 0 0x02>; - clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>; - clock-names = "ehci_ohci", "usb_extal", "usb_xtal"; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, + <&usb_extal>, <&usb_xtal>; + clock-names = "ehci_ohci", "hs-usb-if", "usb_extal", "usb_xtal"; #clock-cells = <0>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + reset-names = "ehci_ohci", "hs-usb-if"; }; diff --git a/Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml b/Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml new file mode 100644 index 000000000000..c3930edc410f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/socionext,uniphier-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier clock controller + +maintainers: + - Masahiro Yamada <yamada.masahiro@socionext.com> + +properties: + compatible: + oneOf: + - description: System clock + enum: + - socionext,uniphier-ld4-clock + - socionext,uniphier-pro4-clock + - socionext,uniphier-sld8-clock + - socionext,uniphier-pro5-clock + - socionext,uniphier-pxs2-clock + - socionext,uniphier-ld6b-clock + - socionext,uniphier-ld11-clock + - socionext,uniphier-ld20-clock + - socionext,uniphier-pxs3-clock + - description: Media I/O (MIO) clock, SD clock + enum: + - socionext,uniphier-ld4-mio-clock + - socionext,uniphier-pro4-mio-clock + - socionext,uniphier-sld8-mio-clock + - socionext,uniphier-pro5-sd-clock + - socionext,uniphier-pxs2-sd-clock + - socionext,uniphier-ld11-mio-clock + - socionext,uniphier-ld20-sd-clock + - socionext,uniphier-pxs3-sd-clock + - description: Peripheral clock + enum: + - socionext,uniphier-ld4-peri-clock + - socionext,uniphier-pro4-peri-clock + - socionext,uniphier-sld8-peri-clock + - socionext,uniphier-pro5-peri-clock + - socionext,uniphier-pxs2-peri-clock + - socionext,uniphier-ld11-peri-clock + - socionext,uniphier-ld20-peri-clock + - socionext,uniphier-pxs3-peri-clock + + "#clock-cells": + const: 1 + +additionalProperties: false + +required: + - compatible + - "#clock-cells" + +examples: + - | + sysctrl@61840000 { + compatible = "socionext,uniphier-sysctrl", "simple-mfd", "syscon"; + reg = <0x61840000 0x4000>; + + clock { + compatible = "socionext,uniphier-ld11-clock"; + #clock-cells = <1>; + }; + + // other nodes ... + }; + + - | + mioctrl@59810000 { + compatible = "socionext,uniphier-mioctrl", "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; + + clock { + compatible = "socionext,uniphier-ld11-mio-clock"; + #clock-cells = <1>; + }; + + // other nodes ... + }; + + - | + perictrl@59820000 { + compatible = "socionext,uniphier-perictrl", "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + clock { + compatible = "socionext,uniphier-ld11-peri-clock"; + #clock-cells = <1>; + }; + + // other nodes ... + }; diff --git a/Documentation/devicetree/bindings/clock/sprd.txt b/Documentation/devicetree/bindings/clock/sprd,sc9860-clk.txt index e9d179e882d9..aaaf02ca2a6a 100644 --- a/Documentation/devicetree/bindings/clock/sprd.txt +++ b/Documentation/devicetree/bindings/clock/sprd,sc9860-clk.txt @@ -1,4 +1,4 @@ -Spreadtrum Clock Binding +Spreadtrum SC9860 Clock Binding ------------------------ Required properties: diff --git a/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml b/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml new file mode 100644 index 000000000000..bb3a78d8105e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2019 Unisoc Inc. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/clock/sprd,sc9863a-clk.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: SC9863A Clock Control Unit Device Tree Bindings + +maintainers: + - Orson Zhai <orsonzhai@gmail.com> + - Baolin Wang <baolin.wang7@gmail.com> + - Chunyan Zhang <zhang.lyra@gmail.com> + +properties: + "#clock-cells": + const: 1 + + compatible : + enum: + - sprd,sc9863a-ap-clk + - sprd,sc9863a-aon-clk + - sprd,sc9863a-apahb-gate + - sprd,sc9863a-pmu-gate + - sprd,sc9863a-aonapb-gate + - sprd,sc9863a-pll + - sprd,sc9863a-mpll + - sprd,sc9863a-rpll + - sprd,sc9863a-dpll + - sprd,sc9863a-mm-gate + - sprd,sc9863a-apapb-gate + + clocks: + minItems: 1 + maxItems: 4 + description: | + The input parent clock(s) phandle for this clock, only list fixed + clocks which are declared in devicetree. + + clock-names: + minItems: 1 + maxItems: 4 + items: + - const: ext-26m + - const: ext-32k + - const: ext-4m + - const: rco-100m + + reg: + maxItems: 1 + +required: + - compatible + - '#clock-cells' + +if: + properties: + compatible: + enum: + - sprd,sc9863a-ap-clk + - sprd,sc9863a-aon-clk +then: + required: + - reg + +else: + description: | + Other SC9863a clock nodes should be the child of a syscon node in + which compatible string shoule be: + "sprd,sc9863a-glbregs", "syscon", "simple-mfd" + + The 'reg' property for the clock node is also required if there is a sub + range of registers for the clocks. + +examples: + - | + ap_clk: clock-controller@21500000 { + compatible = "sprd,sc9863a-ap-clk"; + reg = <0 0x21500000 0 0x1000>; + clocks = <&ext_26m>, <&ext_32k>; + clock-names = "ext-26m", "ext-32k"; + #clock-cells = <1>; + }; + + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + ap_ahb_regs: syscon@20e00000 { + compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd"; + reg = <0 0x20e00000 0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x20e00000 0x4000>; + + apahb_gate: apahb-gate@0 { + compatible = "sprd,sc9863a-apahb-gate"; + reg = <0x0 0x1020>; + #clock-cells = <1>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml b/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml new file mode 100644 index 000000000000..869b18ac88d7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti,am654-ehrpwm-tbclk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI EHRPWM Time Base Clock + +maintainers: + - Vignesh Raghavendra <vigneshr@ti.com> + +properties: + compatible: + items: + - const: ti,am654-ehrpwm-tbclk + - const: syscon + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - reg + +examples: + - | + ehrpwm_tbclk: syscon@4140 { + compatible = "ti,am654-ehrpwm-tbclk", "syscon"; + reg = <0x4140 0x18>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/uniphier-clock.txt b/Documentation/devicetree/bindings/clock/uniphier-clock.txt deleted file mode 100644 index 7b5f602765fe..000000000000 --- a/Documentation/devicetree/bindings/clock/uniphier-clock.txt +++ /dev/null @@ -1,132 +0,0 @@ -UniPhier clock controller - - -System clock ------------- - -Required properties: -- compatible: should be one of the following: - "socionext,uniphier-ld4-clock" - for LD4 SoC. - "socionext,uniphier-pro4-clock" - for Pro4 SoC. - "socionext,uniphier-sld8-clock" - for sLD8 SoC. - "socionext,uniphier-pro5-clock" - for Pro5 SoC. - "socionext,uniphier-pxs2-clock" - for PXs2/LD6b SoC. - "socionext,uniphier-ld11-clock" - for LD11 SoC. - "socionext,uniphier-ld20-clock" - for LD20 SoC. - "socionext,uniphier-pxs3-clock" - for PXs3 SoC -- #clock-cells: should be 1. - -Example: - - sysctrl@61840000 { - compatible = "socionext,uniphier-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x4000>; - - clock { - compatible = "socionext,uniphier-ld11-clock"; - #clock-cells = <1>; - }; - - other nodes ... - }; - -Provided clocks: - - 8: ST DMAC -12: GIO (Giga bit stream I/O) -14: USB3 ch0 host -15: USB3 ch1 host -16: USB3 ch0 PHY0 -17: USB3 ch0 PHY1 -20: USB3 ch1 PHY0 -21: USB3 ch1 PHY1 - - -Media I/O (MIO) clock, SD clock -------------------------------- - -Required properties: -- compatible: should be one of the following: - "socionext,uniphier-ld4-mio-clock" - for LD4 SoC. - "socionext,uniphier-pro4-mio-clock" - for Pro4 SoC. - "socionext,uniphier-sld8-mio-clock" - for sLD8 SoC. - "socionext,uniphier-pro5-sd-clock" - for Pro5 SoC. - "socionext,uniphier-pxs2-sd-clock" - for PXs2/LD6b SoC. - "socionext,uniphier-ld11-mio-clock" - for LD11 SoC. - "socionext,uniphier-ld20-sd-clock" - for LD20 SoC. - "socionext,uniphier-pxs3-sd-clock" - for PXs3 SoC -- #clock-cells: should be 1. - -Example: - - mioctrl@59810000 { - compatible = "socionext,uniphier-mioctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; - - clock { - compatible = "socionext,uniphier-ld11-mio-clock"; - #clock-cells = <1>; - }; - - other nodes ... - }; - -Provided clocks: - - 0: SD ch0 host - 1: eMMC host - 2: SD ch1 host - 7: MIO DMAC - 8: USB2 ch0 host - 9: USB2 ch1 host -10: USB2 ch2 host -12: USB2 ch0 PHY -13: USB2 ch1 PHY -14: USB2 ch2 PHY - - -Peripheral clock ----------------- - -Required properties: -- compatible: should be one of the following: - "socionext,uniphier-ld4-peri-clock" - for LD4 SoC. - "socionext,uniphier-pro4-peri-clock" - for Pro4 SoC. - "socionext,uniphier-sld8-peri-clock" - for sLD8 SoC. - "socionext,uniphier-pro5-peri-clock" - for Pro5 SoC. - "socionext,uniphier-pxs2-peri-clock" - for PXs2/LD6b SoC. - "socionext,uniphier-ld11-peri-clock" - for LD11 SoC. - "socionext,uniphier-ld20-peri-clock" - for LD20 SoC. - "socionext,uniphier-pxs3-peri-clock" - for PXs3 SoC -- #clock-cells: should be 1. - -Example: - - perictrl@59820000 { - compatible = "socionext,uniphier-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - clock { - compatible = "socionext,uniphier-ld11-peri-clock"; - #clock-cells = <1>; - }; - - other nodes ... - }; - -Provided clocks: - - 0: UART ch0 - 1: UART ch1 - 2: UART ch2 - 3: UART ch3 - 4: I2C ch0 - 5: I2C ch1 - 6: I2C ch2 - 7: I2C ch3 - 8: I2C ch4 - 9: I2C ch5 -10: I2C ch6 diff --git a/Documentation/devicetree/bindings/connector/samsung,usb-connector-11pin.txt b/Documentation/devicetree/bindings/connector/samsung,usb-connector-11pin.txt index 22256e295a7a..3dd8961154ab 100644 --- a/Documentation/devicetree/bindings/connector/samsung,usb-connector-11pin.txt +++ b/Documentation/devicetree/bindings/connector/samsung,usb-connector-11pin.txt @@ -19,7 +19,7 @@ Required nodes: 0: High Speed (HS), 3: Mobile High-Definition Link (MHL), specific to 11-pin Samsung micro-USB. -[1]: bindings/connector/usb-connector.txt +[1]: bindings/connector/usb-connector.yaml Example ------- diff --git a/Documentation/devicetree/bindings/connector/usb-connector.txt b/Documentation/devicetree/bindings/connector/usb-connector.txt deleted file mode 100644 index 88578ac1a8a7..000000000000 --- a/Documentation/devicetree/bindings/connector/usb-connector.txt +++ /dev/null @@ -1,135 +0,0 @@ -USB Connector -============= - -A USB connector node represents a physical USB connector. It should be -a child of a USB interface controller. - -Required properties: -- compatible: describes type of the connector, must be one of: - "usb-a-connector", - "usb-b-connector", - "usb-c-connector". - -Optional properties: -- label: symbolic name for the connector, -- type: size of the connector, should be specified in case of USB-A, USB-B - non-fullsize connectors: "mini", "micro". -- self-powered: Set this property if the usb device that has its own power - source. - -Optional properties for usb-b-connector: -- id-gpios: an input gpio for USB ID pin. -- vbus-gpios: an input gpio for USB VBUS pin, used to detect presence of - VBUS 5V. - see gpio/gpio.txt. -- vbus-supply: a phandle to the regulator for USB VBUS if needed when host - mode or dual role mode is supported. - Particularly, if use an output GPIO to control a VBUS regulator, should - model it as a regulator. - see regulator/fixed-regulator.yaml -- pinctrl-names : a pinctrl state named "default" is optional -- pinctrl-0 : pin control group - see pinctrl/pinctrl-bindings.txt - -Optional properties for usb-c-connector: -- power-role: should be one of "source", "sink" or "dual"(DRP) if typec - connector has power support. -- try-power-role: preferred power role if "dual"(DRP) can support Try.SNK - or Try.SRC, should be "sink" for Try.SNK or "source" for Try.SRC. -- data-role: should be one of "host", "device", "dual"(DRD) if typec - connector supports USB data. - -Required properties for usb-c-connector with power delivery support: -- source-pdos: An array of u32 with each entry providing supported power - source data object(PDO), the detailed bit definitions of PDO can be found - in "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.2 - Source_Capabilities Message, the order of each entry(PDO) should follow - the PD spec chapter 6.4.1. Required for power source and power dual role. - User can specify the source PDO array via PDO_FIXED/BATT/VAR/PPS_APDO() - defined in dt-bindings/usb/pd.h. -- sink-pdos: An array of u32 with each entry providing supported power - sink data object(PDO), the detailed bit definitions of PDO can be found - in "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.3 - Sink Capabilities Message, the order of each entry(PDO) should follow - the PD spec chapter 6.4.1. Required for power sink and power dual role. - User can specify the sink PDO array via PDO_FIXED/BATT/VAR/PPS_APDO() defined - in dt-bindings/usb/pd.h. -- op-sink-microwatt: Sink required operating power in microwatt, if source - can't offer the power, Capability Mismatch is set. Required for power - sink and power dual role. - -Required nodes: -- any data bus to the connector should be modeled using the OF graph bindings - specified in bindings/graph.txt, unless the bus is between parent node and - the connector. Since single connector can have multiple data buses every bus - has assigned OF graph port number as follows: - 0: High Speed (HS), present in all connectors, - 1: Super Speed (SS), present in SS capable connectors, - 2: Sideband use (SBU), present in USB-C. - -Examples --------- - -1. Micro-USB connector with HS lines routed via controller (MUIC): - -muic-max77843@66 { - ... - usb_con: connector { - compatible = "usb-b-connector"; - label = "micro-USB"; - type = "micro"; - }; -}; - -2. USB-C connector attached to CC controller (s2mm005), HS lines routed -to companion PMIC (max77865), SS lines to USB3 PHY and SBU to DisplayPort. -DisplayPort video lines are routed to the connector via SS mux in USB3 PHY. - -ccic: s2mm005@33 { - ... - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usb_con_hs: endpoint { - remote-endpoint = <&max77865_usbc_hs>; - }; - }; - port@1 { - reg = <1>; - usb_con_ss: endpoint { - remote-endpoint = <&usbdrd_phy_ss>; - }; - }; - port@2 { - reg = <2>; - usb_con_sbu: endpoint { - remote-endpoint = <&dp_aux>; - }; - }; - }; - }; -}; - -3. USB-C connector attached to a typec port controller(ptn5110), which has -power delivery support and enables drp. - -typec: ptn5110@50 { - ... - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "dual"; - try-power-role = "sink"; - source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>; - sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM) - PDO_VAR(5000, 12000, 2000)>; - op-sink-microwatt = <10000000>; - }; -}; diff --git a/Documentation/devicetree/bindings/connector/usb-connector.yaml b/Documentation/devicetree/bindings/connector/usb-connector.yaml new file mode 100644 index 000000000000..4638d7adb806 --- /dev/null +++ b/Documentation/devicetree/bindings/connector/usb-connector.yaml @@ -0,0 +1,206 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/connector/usb-connector.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: USB Connector + +maintainers: + - Rob Herring <robh@kernel.org> + +description: + A USB connector node represents a physical USB connector. It should be a child + of a USB interface controller. + +properties: + compatible: + enum: + - usb-a-connector + - usb-b-connector + - usb-c-connector + + label: + description: Symbolic name for the connector. + + type: + description: Size of the connector, should be specified in case of + non-fullsize 'usb-a-connector' or 'usb-b-connector' compatible + connectors. + allOf: + - $ref: /schemas/types.yaml#definitions/string + enum: + - mini + - micro + + self-powered: + description: Set this property if the USB device has its own power source. + type: boolean + + # The following are optional properties for "usb-b-connector". + id-gpios: + description: An input gpio for USB ID pin. + maxItems: 1 + + vbus-gpios: + description: An input gpio for USB VBus pin, used to detect presence of + VBUS 5V. + maxItems: 1 + + vbus-supply: + description: A phandle to the regulator for USB VBUS if needed when host + mode or dual role mode is supported. + Particularly, if use an output GPIO to control a VBUS regulator, should + model it as a regulator. See bindings/regulator/fixed-regulator.yaml + + # The following are optional properties for "usb-c-connector". + power-role: + description: Determines the power role that the Type C connector will + support. "dual" refers to Dual Role Port (DRP). + allOf: + - $ref: /schemas/types.yaml#definitions/string + enum: + - source + - sink + - dual + + try-power-role: + description: Preferred power role. + allOf: + - $ref: /schemas/types.yaml#definitions/string + enum: + - source + - sink + - dual + + data-role: + description: Data role if Type C connector supports USB data. "dual" refers + Dual Role Device (DRD). + allOf: + - $ref: /schemas/types.yaml#definitions/string + enum: + - host + - device + - dual + + # The following are optional properties for "usb-c-connector" with power + # delivery support. + source-pdos: + description: An array of u32 with each entry providing supported power + source data object(PDO), the detailed bit definitions of PDO can be found + in "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.2 + Source_Capabilities Message, the order of each entry(PDO) should follow + the PD spec chapter 6.4.1. Required for power source and power dual role. + User can specify the source PDO array via PDO_FIXED/BATT/VAR/PPS_APDO() + defined in dt-bindings/usb/pd.h. + minItems: 1 + maxItems: 7 + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + + sink-pdos: + description: An array of u32 with each entry providing supported power sink + data object(PDO), the detailed bit definitions of PDO can be found in + "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.3 + Sink Capabilities Message, the order of each entry(PDO) should follow the + PD spec chapter 6.4.1. Required for power sink and power dual role. User + can specify the sink PDO array via PDO_FIXED/BATT/VAR/PPS_APDO() defined + in dt-bindings/usb/pd.h. + minItems: 1 + maxItems: 7 + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + + op-sink-microwatt: + description: Sink required operating power in microwatt, if source can't + offer the power, Capability Mismatch is set. Required for power sink and + power dual role. + + ports: + description: OF graph bindings (specified in bindings/graph.txt) that model + any data bus to the connector unless the bus is between parent node and + the connector. Since a single connector can have multiple data buses every + bus has an assigned OF graph port number as described below. + type: object + properties: + port@0: + type: object + description: High Speed (HS), present in all connectors. + + port@1: + type: object + description: Super Speed (SS), present in SS capable connectors. + + port@2: + type: object + description: Sideband Use (SBU), present in USB-C. This describes the + alternate mode connection of which SBU is a part. + + required: + - port@0 + +required: + - compatible + +examples: + # Micro-USB connector with HS lines routed via controller (MUIC). + - |+ + muic-max77843 { + usb_con1: connector { + compatible = "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + }; + }; + + # USB-C connector attached to CC controller (s2mm005), HS lines routed + # to companion PMIC (max77865), SS lines to USB3 PHY and SBU to DisplayPort. + # DisplayPort video lines are routed to the connector via SS mux in USB3 PHY. + - |+ + ccic: s2mm005 { + usb_con2: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usb_con_hs: endpoint { + remote-endpoint = <&max77865_usbc_hs>; + }; + }; + port@1 { + reg = <1>; + usb_con_ss: endpoint { + remote-endpoint = <&usbdrd_phy_ss>; + }; + }; + port@2 { + reg = <2>; + usb_con_sbu: endpoint { + remote-endpoint = <&dp_aux>; + }; + }; + }; + }; + }; + + # USB-C connector attached to a typec port controller(ptn5110), which has + # power delivery support and enables drp. + - |+ + #include <dt-bindings/usb/pd.h> + typec: ptn5110 { + usb_con3: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 12000, 2000)>; + op-sink-microwatt = <10000000>; + }; + }; diff --git a/Documentation/devicetree/bindings/crypto/fsl-dcp.txt b/Documentation/devicetree/bindings/crypto/fsl-dcp.txt index 4e4d387e38a5..513499fcdb5b 100644 --- a/Documentation/devicetree/bindings/crypto/fsl-dcp.txt +++ b/Documentation/devicetree/bindings/crypto/fsl-dcp.txt @@ -11,7 +11,7 @@ Required properties: Example: -dcp@80028000 { +dcp: crypto@80028000 { compatible = "fsl,imx28-dcp", "fsl,imx23-dcp"; reg = <0x80028000 0x2000>; interrupts = <52 53>; diff --git a/Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt b/Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt index e8a35c71e947..db690b10e582 100644 --- a/Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt +++ b/Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt @@ -8,7 +8,7 @@ Required properties: Example: -sah@10025000 { +sah: crypto@10025000 { compatible = "fsl,imx27-sahara"; reg = < 0x10025000 0x800>; interrupts = <75>; diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt index 2fe245ca816a..8f359f473ada 100644 --- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt @@ -138,7 +138,7 @@ iMX6QDL/SX requires four clocks iMX6UL does only require three clocks - crypto: caam@2140000 { + crypto: crypto@2140000 { compatible = "fsl,sec-v4.0"; #address-cells = <1>; #size-cells = <1>; diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml index d1205a6697a0..a8d202c9d004 100644 --- a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml +++ b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml @@ -71,9 +71,9 @@ properties: maxItems: 2 reg-names: - items: - - const: vpu - - const: hhi + items: + - const: vpu + - const: hhi interrupts: maxItems: 1 @@ -107,6 +107,8 @@ required: - "#address-cells" - "#size-cells" +additionalProperties: false + examples: - | vpu: vpu@d0100000 { diff --git a/Documentation/devicetree/bindings/display/bridge/adi,adv7123.txt b/Documentation/devicetree/bindings/display/bridge/adi,adv7123.txt index a6b2b2b8f3d9..d3c2a4914ea2 100644 --- a/Documentation/devicetree/bindings/display/bridge/adi,adv7123.txt +++ b/Documentation/devicetree/bindings/display/bridge/adi,adv7123.txt @@ -1,5 +1,5 @@ -Analog Device ADV7123 Video DAC -------------------------------- +Analog Devices ADV7123 Video DAC +-------------------------------- The ADV7123 is a digital-to-analog converter that outputs VGA signals from a parallel video input. diff --git a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt index e8ddec5d9d91..659523f538bf 100644 --- a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt +++ b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt @@ -1,5 +1,5 @@ -Analog Device ADV7511(W)/13/33/35 HDMI Encoders ------------------------------------------ +Analog Devices ADV7511(W)/13/33/35 HDMI Encoders +------------------------------------------------ The ADV7511, ADV7511W, ADV7513, ADV7533 and ADV7535 are HDMI audio and video transmitters compatible with HDMI 1.4 and DVI 1.0. They support color space diff --git a/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt b/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt deleted file mode 100644 index 8def11b16a24..000000000000 --- a/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt +++ /dev/null @@ -1,36 +0,0 @@ -Vivante GPU core devices -======================== - -Required properties: -- compatible: Should be "vivante,gc" - A more specific compatible is not needed, as the cores contain chip - identification registers at fixed locations, which provide all the - necessary information to the driver. -- reg: should be register base and length as documented in the - datasheet -- interrupts: Should contain the cores interrupt line -- clocks: should contain one clock for entry in clock-names - see Documentation/devicetree/bindings/clock/clock-bindings.txt -- clock-names: - - "bus": AXI/master interface clock - - "reg": AHB/slave interface clock - (only required if GPU can gate slave interface independently) - - "core": GPU core clock - - "shader": Shader clock (only required if GPU has feature PIPE_3D) - -Optional properties: -- power-domains: a power domain consumer specifier according to - Documentation/devicetree/bindings/power/power_domain.txt - -example: - -gpu_3d: gpu@130000 { - compatible = "vivante,gc"; - reg = <0x00130000 0x4000>; - interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>, - <&clks IMX6QDL_CLK_GPU3D_CORE>, - <&clks IMX6QDL_CLK_GPU3D_SHADER>; - clock-names = "bus", "core", "shader"; - power-domains = <&gpc 1>; -}; diff --git a/Documentation/devicetree/bindings/display/panel/panel-dpi.yaml b/Documentation/devicetree/bindings/display/panel/panel-dpi.yaml index f63870384c00..0cd74c8dab42 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-dpi.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-dpi.yaml @@ -21,15 +21,6 @@ properties: - {} - const: panel-dpi - data-mapping: - enum: - - rgb24 - - rgb565 - - bgr666 - description: | - Describes the media format, how the display panel is connected - to the display interface. - backlight: true enable-gpios: true height-mm: true @@ -52,7 +43,6 @@ examples: compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; label = "osddisplay"; power-supply = <&vcc_supply>; - data-mapping = "rgb565"; backlight = <&backlight>; port { diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index cac61a998203..eb04c2330698 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -65,7 +65,7 @@ properties: ports: type: object description: - Ports as described in Documentation/devictree/bindings/graph.txt + Ports as described in Documentation/devicetree/bindings/graph.txt properties: "#address-cells": const: 1 @@ -121,7 +121,7 @@ examples: #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/soc/ti,sci_pm_domain.h> - dss: dss@04a00000 { + dss: dss@4a00000 { compatible = "ti,am65x-dss"; reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ diff --git a/Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml index ade9b2f513f5..eb4b1a266210 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml @@ -98,7 +98,7 @@ properties: ports: type: object description: - Ports as described in Documentation/devictree/bindings/graph.txt + Ports as described in Documentation/devicetree/bindings/graph.txt properties: "#address-cells": const: 1 @@ -154,7 +154,7 @@ examples: #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/soc/ti,sci_pm_domain.h> - dss: dss@04a00000 { + dss: dss@4a00000 { compatible = "ti,j721e-dss"; reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ diff --git a/Documentation/devicetree/bindings/display/ti/ti,k2g-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,k2g-dss.yaml index 385bd060ccf9..8f87b82c6695 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,k2g-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,k2g-dss.yaml @@ -56,7 +56,7 @@ properties: port: type: object description: - Port as described in Documentation/devictree/bindings/graph.txt. + Port as described in Documentation/devicetree/bindings/graph.txt. The DSS DPI output port node max-memory-bandwidth: @@ -81,7 +81,7 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> - dss: dss@02540000 { + dss: dss@2540000 { compatible = "ti,k2g-dss"; reg = <0x02540000 0x400>, <0x02550000 0x1000>, diff --git a/Documentation/devicetree/bindings/dma/adi,axi-dmac.txt b/Documentation/devicetree/bindings/dma/adi,axi-dmac.txt index b38ee732efa9..cd17684aaab5 100644 --- a/Documentation/devicetree/bindings/dma/adi,axi-dmac.txt +++ b/Documentation/devicetree/bindings/dma/adi,axi-dmac.txt @@ -1,4 +1,4 @@ -Analog Device AXI-DMAC DMA controller +Analog Devices AXI-DMAC DMA controller Required properties: - compatible: Must be "adi,axi-dmac-1.00.a". diff --git a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt index f1f95f678739..e8f6c42e80f2 100644 --- a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt +++ b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt @@ -16,6 +16,7 @@ Required Properties: - "renesas,r8a7794-usb-dmac" (R-Car E2) - "renesas,r8a7795-usb-dmac" (R-Car H3) - "renesas,r8a7796-usb-dmac" (R-Car M3-W) + - "renesas,r8a77961-usb-dmac" (R-Car M3-W+) - "renesas,r8a77965-usb-dmac" (R-Car M3-N) - "renesas,r8a77990-usb-dmac" (R-Car E3) - "renesas,r8a77995-usb-dmac" (R-Car D3) diff --git a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml index 2ca3ddbe1ff4..e7f2ad7dab5e 100644 --- a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml +++ b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml @@ -43,6 +43,8 @@ required: - interrupts - '#dma-cells' +additionalProperties: false + examples: - | dma@3000000 { diff --git a/Documentation/devicetree/bindings/dma/socionext,uniphier-mio-dmac.yaml b/Documentation/devicetree/bindings/dma/socionext,uniphier-mio-dmac.yaml new file mode 100644 index 000000000000..e7bf6dd7da29 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/socionext,uniphier-mio-dmac.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/socionext,uniphier-mio-dmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier Media IO DMA controller + +description: | + This works as an external DMA engine for SD/eMMC controllers etc. + found in UniPhier LD4, Pro4, sLD8 SoCs. + +maintainers: + - Masahiro Yamada <yamada.masahiro@socionext.com> + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + const: socionext,uniphier-mio-dmac + + reg: + maxItems: 1 + + interrupts: + description: | + A list of interrupt specifiers associated with the DMA channels. + The number of interrupt lines is SoC-dependent. + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + '#dma-cells': + description: The single cell represents the channel index. + const: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - '#dma-cells' + +additionalProperties: false + +examples: + - | + // In the example below, "interrupts = <0 68 4>, <0 68 4>, ..." is not a + // typo. The first two channels share a single interrupt line. + + dmac: dma-controller@5a000000 { + compatible = "socionext,uniphier-mio-dmac"; + reg = <0x5a000000 0x1000>; + interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, + <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>; + clocks = <&mio_clk 7>; + resets = <&mio_rst 7>; + #dma-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/dma/socionext,uniphier-xdmac.yaml b/Documentation/devicetree/bindings/dma/socionext,uniphier-xdmac.yaml new file mode 100644 index 000000000000..86cfb599256e --- /dev/null +++ b/Documentation/devicetree/bindings/dma/socionext,uniphier-xdmac.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/socionext,uniphier-xdmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier external DMA controller + +description: | + This describes the devicetree bindings for an external DMA engine to perform + memory-to-memory or peripheral-to-memory data transfer capable of supporting + 16 channels, implemented in Socionext UniPhier SoCs. + +maintainers: + - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + const: socionext,uniphier-xdmac + + reg: + items: + - description: XDMAC base register region (offset and length) + - description: XDMAC extension register region (offset and length) + + interrupts: + maxItems: 1 + + "#dma-cells": + const: 2 + description: | + DMA request from clients consists of 2 cells: + 1. Channel index + 2. Transfer request factor number, If no transfer factor, use 0. + The number is SoC-specific, and this should be specified with + relation to the device to use the DMA controller. + + dma-channels: + minimum: 1 + maximum: 16 + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - "#dma-cells" + +examples: + - | + xdmac: dma-controller@5fc10000 { + compatible = "socionext,uniphier-xdmac"; + reg = <0x5fc10000 0x1000>, <0x5fc20000 0x800>; + interrupts = <0 188 4>; + #dma-cells = <2>; + dma-channels = <16>; + }; + +... diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt index 0e1398f93aa2..29fcd37082e8 100644 --- a/Documentation/devicetree/bindings/dma/ti-edma.txt +++ b/Documentation/devicetree/bindings/dma/ti-edma.txt @@ -180,7 +180,7 @@ edma1_tptc0: tptc@27b0000 { }; edma1_tptc1: tptc@27b8000 { - compatible = "ti, k2g-edma3-tptc", "ti,edma3-tptc"; + compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; reg = <0x027b8000 0x400>; power-domains = <&k2g_pds 0x4f>; }; diff --git a/Documentation/devicetree/bindings/dma/ti/k3-udma.yaml b/Documentation/devicetree/bindings/dma/ti/k3-udma.yaml index 34780d7535b8..39ea05e6e5ff 100644 --- a/Documentation/devicetree/bindings/dma/ti/k3-udma.yaml +++ b/Documentation/devicetree/bindings/dma/ti/k3-udma.yaml @@ -45,7 +45,8 @@ allOf: properties: "#dma-cells": - const: 1 + minimum: 1 + maximum: 2 description: | The cell is the PSI-L thread ID of the remote (to UDMAP) end. Valid ranges for thread ID depends on the data movement direction: @@ -55,6 +56,8 @@ properties: Please refer to the device documentation for the PSI-L thread map and also the PSI-L peripheral chapter for the correct thread ID. + When #dma-cells is 2, the second parameter is the channel ATYPE. + compatible: enum: - ti,am654-navss-main-udmap @@ -131,6 +134,20 @@ required: - ti,sci-rm-range-rchan - ti,sci-rm-range-rflow +if: + properties: + "#dma-cells": + const: 2 +then: + properties: + ti,udma-atype: + description: ATYPE value which should be used by non slave channels + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - ti,udma-atype + examples: - |+ cbass_main { diff --git a/Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt b/Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt deleted file mode 100644 index b12388dc7eac..000000000000 --- a/Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt +++ /dev/null @@ -1,25 +0,0 @@ -UniPhier Media IO DMA controller - -This works as an external DMA engine for SD/eMMC controllers etc. -found in UniPhier LD4, Pro4, sLD8 SoCs. - -Required properties: -- compatible: should be "socionext,uniphier-mio-dmac". -- reg: offset and length of the register set for the device. -- interrupts: a list of interrupt specifiers associated with the DMA channels. -- clocks: a single clock specifier. -- #dma-cells: should be <1>. The single cell represents the channel index. - -Example: - dmac: dma-controller@5a000000 { - compatible = "socionext,uniphier-mio-dmac"; - reg = <0x5a000000 0x1000>; - interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, - <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>; - clocks = <&mio_clk 7>; - #dma-cells = <1>; - }; - -Note: -In the example above, "interrupts = <0 68 4>, <0 68 4>, ..." is not a typo. -The first two channels share a single interrupt line. diff --git a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml index f04870d84542..a5dc070d0ca7 100644 --- a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml +++ b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml @@ -68,6 +68,8 @@ required: - mbox-names - memory-region +additionalProperties: false + examples: - | #include <dt-bindings/firmware/imx/rsrc.h> diff --git a/Documentation/devicetree/bindings/eeprom/at24.yaml b/Documentation/devicetree/bindings/eeprom/at24.yaml index 0f6d8db18d6c..a15787e504f0 100644 --- a/Documentation/devicetree/bindings/eeprom/at24.yaml +++ b/Documentation/devicetree/bindings/eeprom/at24.yaml @@ -172,6 +172,8 @@ required: - compatible - reg +additionalProperties: false + examples: - | i2c { diff --git a/Documentation/devicetree/bindings/example-schema.yaml b/Documentation/devicetree/bindings/example-schema.yaml index 4ddcf709cc3c..62811a1b5058 100644 --- a/Documentation/devicetree/bindings/example-schema.yaml +++ b/Documentation/devicetree/bindings/example-schema.yaml @@ -7,9 +7,9 @@ # $id is a unique identifier based on the filename. There may or may not be a # file present at the URL. -$id: "http://devicetree.org/schemas/example-schema.yaml#" +$id: http://devicetree.org/schemas/example-schema.yaml# # $schema is the meta-schema this schema should be validated with. -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$schema: http://devicetree.org/meta-schemas/core.yaml# title: An example schema annotated with jsonschema details diff --git a/Documentation/devicetree/bindings/extcon/extcon-usbc-cros-ec.txt b/Documentation/devicetree/bindings/extcon/extcon-usbc-cros-ec.txt deleted file mode 100644 index 8e8625c00dfa..000000000000 --- a/Documentation/devicetree/bindings/extcon/extcon-usbc-cros-ec.txt +++ /dev/null @@ -1,24 +0,0 @@ -ChromeOS EC USB Type-C cable and accessories detection - -On ChromeOS systems with USB Type C ports, the ChromeOS Embedded Controller is -able to detect the state of external accessories such as display adapters -or USB devices when said accessories are attached or detached. - -The node for this device must be under a cros-ec node like google,cros-ec-spi -or google,cros-ec-i2c. - -Required properties: -- compatible: Should be "google,extcon-usbc-cros-ec". -- google,usb-port-id: Specifies the USB port ID to use. - -Example: - cros-ec@0 { - compatible = "google,cros-ec-i2c"; - - ... - - extcon { - compatible = "google,extcon-usbc-cros-ec"; - google,usb-port-id = <0>; - }; - } diff --git a/Documentation/devicetree/bindings/extcon/extcon-usbc-cros-ec.yaml b/Documentation/devicetree/bindings/extcon/extcon-usbc-cros-ec.yaml new file mode 100644 index 000000000000..9c5849b341ea --- /dev/null +++ b/Documentation/devicetree/bindings/extcon/extcon-usbc-cros-ec.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/extcon/extcon-usbc-cros-ec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ChromeOS EC USB Type-C cable and accessories detection + +maintainers: + - Benson Leung <bleung@chromium.org> + - Enric Balletbo i Serra <enric.balletbo@collabora.com> + +description: | + On ChromeOS systems with USB Type C ports, the ChromeOS Embedded Controller is + able to detect the state of external accessories such as display adapters + or USB devices when said accessories are attached or detached. + The node for this device must be under a cros-ec node like google,cros-ec-spi + or google,cros-ec-i2c. + +properties: + compatible: + const: google,extcon-usbc-cros-ec + + google,usb-port-id: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + description: the port id + minimum: 0 + maximum: 255 + +required: + - compatible + - google,usb-port-id + +additionalProperties: false + +examples: + - | + spi0 { + #address-cells = <1>; + #size-cells = <0>; + cros-ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0>; + + usbc_extcon0: extcon0 { + compatible = "google,extcon-usbc-cros-ec"; + google,usb-port-id = <0>; + }; + + usbc_extcon1: extcon1 { + compatible = "google,extcon-usbc-cros-ec"; + google,usb-port-id = <1>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml b/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml index 878a2079ebb6..1bd2870c3a9c 100644 --- a/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml +++ b/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml @@ -34,9 +34,12 @@ required: - compatible - reg +additionalProperties: false + examples: - | npe@c8006000 { compatible = "intel,ixp4xx-network-processing-engine"; reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; }; +... diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt index 3f29ea04b5fe..354b448fc0c3 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt @@ -10,6 +10,7 @@ Required properties: * "qcom,scm-apq8064" * "qcom,scm-apq8084" * "qcom,scm-ipq4019" + * "qcom,scm-ipq806x" * "qcom,scm-msm8660" * "qcom,scm-msm8916" * "qcom,scm-msm8960" diff --git a/Documentation/devicetree/bindings/fpga/fpga-region.txt b/Documentation/devicetree/bindings/fpga/fpga-region.txt index 90c44694a30b..8ab19d1d3f9a 100644 --- a/Documentation/devicetree/bindings/fpga/fpga-region.txt +++ b/Documentation/devicetree/bindings/fpga/fpga-region.txt @@ -263,7 +263,7 @@ Overlay contains: gpio@10040 { compatible = "altr,pio-1.0"; reg = <0x10040 0x20>; - altr,gpio-bank-width = <4>; + altr,ngpio = <4>; #gpio-cells = <2>; clocks = <2>; gpio-controller; @@ -468,8 +468,7 @@ programming is the FPGA based bridge of fpga_region1. compatible = "altr,pio-1.0"; reg = <0x10040 0x20>; clocks = <0x2>; - altr,gpio-bank-width = <0x4>; - resetvalue = <0x0>; + altr,ngpio = <0x4>; #gpio-cells = <0x2>; gpio-controller; }; diff --git a/Documentation/devicetree/bindings/gnss/gnss.txt b/Documentation/devicetree/bindings/gnss/gnss.txt index f547bd4549fe..d6dc9c0d8249 100644 --- a/Documentation/devicetree/bindings/gnss/gnss.txt +++ b/Documentation/devicetree/bindings/gnss/gnss.txt @@ -8,7 +8,7 @@ bus (e.g. UART, I2C or SPI). Please refer to the following documents for generic properties: - Documentation/devicetree/bindings/serial/slave-device.txt + Documentation/devicetree/bindings/serial/serial.yaml Documentation/devicetree/bindings/spi/spi-bus.txt Required properties: diff --git a/Documentation/devicetree/bindings/gpio/brcm,xgs-iproc-gpio.yaml b/Documentation/devicetree/bindings/gpio/brcm,xgs-iproc-gpio.yaml index 64e279a4bc10..5f1ed20e43ee 100644 --- a/Documentation/devicetree/bindings/gpio/brcm,xgs-iproc-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/brcm,xgs-iproc-gpio.yaml @@ -47,6 +47,8 @@ required: - "#gpio-cells" - gpio-controller +additionalProperties: false + dependencies: interrupt-controller: [ interrupts ] diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt index 2e097b57f170..0fc6700ed800 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt @@ -14,7 +14,7 @@ Required properties: "marvell,armada-8k-gpio" should be used for the Armada 7K and 8K SoCs (either from AP or CP), see - Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt + Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt for specific details about the offset property. - reg: Address and length of the register set for the device. Only one diff --git a/Documentation/devicetree/bindings/gpio/gpio-uniphier.txt b/Documentation/devicetree/bindings/gpio/gpio-uniphier.txt deleted file mode 100644 index f281f12dac18..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-uniphier.txt +++ /dev/null @@ -1,51 +0,0 @@ -UniPhier GPIO controller - -Required properties: -- compatible: Should be "socionext,uniphier-gpio". -- reg: Specifies offset and length of the register set for the device. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells: Should be 2. The first cell is the pin number and the second - cell is used to specify optional parameters. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Should be 2. The first cell defines the interrupt number. - The second cell bits[3:0] is used to specify trigger type as follows: - 1 = low-to-high edge triggered - 2 = high-to-low edge triggered - 4 = active high level-sensitive - 8 = active low level-sensitive - Valid combinations are 1, 2, 3, 4, 8. -- ngpios: Specifies the number of GPIO lines. -- gpio-ranges: Mapping to pin controller pins (as described in gpio.txt) -- socionext,interrupt-ranges: Specifies an interrupt number mapping between - this GPIO controller and its interrupt parent, in the form of arbitrary - number of <child-interrupt-base parent-interrupt-base length> triplets. - -Optional properties: -- gpio-ranges-group-names: Used for named gpio ranges (as described in gpio.txt) - -Example: - gpio: gpio@55000000 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000000 0x200>; - interrupt-parent = <&aidet>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 0>; - gpio-ranges-group-names = "gpio_range"; - ngpios = <248>; - socionext,interrupt-ranges = <0 48 16>, <16 154 5>, <21 217 3>; - }; - -Consumer Example: - - sdhci0_pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio UNIPHIER_GPIO_PORT(29, 4) GPIO_ACTIVE_LOW>; - }; - -Please note UNIPHIER_GPIO_PORT(29, 4) represents PORT294 in the SoC document. -Unfortunately, only the one's place is octal in the port numbering. (That is, -PORT 8, 9, 18, 19, 28, 29, ... are missing.) UNIPHIER_GPIO_PORT() is a helper -macro to calculate 29 * 8 + 4. diff --git a/Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml b/Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml new file mode 100644 index 000000000000..c58ff9a94f45 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier GPIO controller + +maintainers: + - Masahiro Yamada <yamada.masahiro@socionext.com> + +properties: + $nodename: + pattern: "^gpio@[0-9a-f]+$" + + compatible: + const: socionext,uniphier-gpio + + reg: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + interrupt-controller: true + + "#interrupt-cells": + description: | + The first cell defines the interrupt number. + The second cell bits[3:0] is used to specify trigger type as follows: + 1 = low-to-high edge triggered + 2 = high-to-low edge triggered + 4 = active high level-sensitive + 8 = active low level-sensitive + Valid combinations are 1, 2, 3, 4, 8. + const: 2 + + ngpios: + minimum: 0 + maximum: 512 + + gpio-ranges: true + + gpio-ranges-group-names: + $ref: /schemas/types.yaml#/definitions/string-array + + socionext,interrupt-ranges: + description: | + Specifies an interrupt number mapping between this GPIO controller and + its interrupt parent, in the form of arbitrary number of + <child-interrupt-base parent-interrupt-base length> triplets. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + - interrupt-controller + - "#interrupt-cells" + - ngpios + - gpio-ranges + - socionext,interrupt-ranges + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/gpio/uniphier-gpio.h> + + gpio: gpio@55000000 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>; + gpio-ranges-group-names = "gpio_range"; + ngpios = <248>; + socionext,interrupt-ranges = <0 48 16>, <16 154 5>, <21 217 3>; + }; + + // Consumer: + // Please note UNIPHIER_GPIO_PORT(29, 4) represents PORT294 in the SoC + // document. Unfortunately, only the one's place is octal in the port + // numbering. (That is, PORT 8, 9, 18, 19, 28, 29, ... do not exist.) + // UNIPHIER_GPIO_PORT() is a helper macro to calculate 29 * 8 + 4. + sdhci0_pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio UNIPHIER_GPIO_PORT(29, 4) GPIO_ACTIVE_LOW>; + }; diff --git a/Documentation/devicetree/bindings/gpio/xylon,logicvc-gpio.yaml b/Documentation/devicetree/bindings/gpio/xylon,logicvc-gpio.yaml index d102888c1be7..a36aec27069c 100644 --- a/Documentation/devicetree/bindings/gpio/xylon,logicvc-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/xylon,logicvc-gpio.yaml @@ -49,6 +49,8 @@ required: - "#gpio-cells" - gpio-controller +additionalProperties: false + examples: - | logicvc: logicvc@43c00000 { diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index e8b99adcb1bd..0b229a7d4a98 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -43,6 +43,9 @@ properties: operating-points-v2: true + resets: + maxItems: 2 + required: - compatible - reg @@ -50,6 +53,8 @@ required: - interrupt-names - clocks +additionalProperties: false + allOf: - if: properties: @@ -57,9 +62,6 @@ allOf: contains: const: amlogic,meson-g12a-mali then: - properties: - resets: - minItems: 2 required: - resets diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml index 8d966f3ff3db..0407e45eb8c4 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml @@ -75,6 +75,9 @@ properties: mali-supply: true + power-domains: + maxItems: 1 + resets: minItems: 1 maxItems: 2 @@ -91,6 +94,8 @@ required: - interrupt-names - clocks +additionalProperties: false + allOf: - if: properties: diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml index afde81be3c29..f5401cc8de4a 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml @@ -115,6 +115,8 @@ required: - clocks - clock-names +additionalProperties: false + allOf: - if: properties: diff --git a/Documentation/devicetree/bindings/gpu/samsung-rotator.yaml b/Documentation/devicetree/bindings/gpu/samsung-rotator.yaml index f4dfa6fc724c..665c6e3b31d3 100644 --- a/Documentation/devicetree/bindings/gpu/samsung-rotator.yaml +++ b/Documentation/devicetree/bindings/gpu/samsung-rotator.yaml @@ -36,6 +36,8 @@ required: - clocks - clock-names +additionalProperties: false + examples: - | rotator@12810000 { diff --git a/Documentation/devicetree/bindings/gpu/vivante,gc.yaml b/Documentation/devicetree/bindings/gpu/vivante,gc.yaml new file mode 100644 index 000000000000..0bc4b38d5cbb --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/vivante,gc.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/vivante,gc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Vivante GPU Bindings + +description: Vivante GPU core devices + +maintainers: + - Lucas Stach <l.stach@pengutronix.de> + +properties: + compatible: + const: vivante,gc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: AXI/master interface clock + - description: GPU core clock + - description: Shader clock (only required if GPU has feature PIPE_3D) + - description: AHB/slave interface clock (only required if GPU can gate slave interface independently) + minItems: 1 + maxItems: 4 + + clock-names: + items: + enum: [ bus, core, shader, reg ] + minItems: 1 + maxItems: 4 + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx6qdl-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + gpu@130000 { + compatible = "vivante,gc"; + reg = <0x00130000 0x4000>; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>, + <&clks IMX6QDL_CLK_GPU3D_CORE>, + <&clks IMX6QDL_CLK_GPU3D_SHADER>; + clock-names = "bus", "core", "shader"; + power-domains = <&gpc 1>; + }; + +... diff --git a/Documentation/devicetree/bindings/hwmon/adi,adm1177.yaml b/Documentation/devicetree/bindings/hwmon/adi,adm1177.yaml index 2a9822075b36..154bee851139 100644 --- a/Documentation/devicetree/bindings/hwmon/adi,adm1177.yaml +++ b/Documentation/devicetree/bindings/hwmon/adi,adm1177.yaml @@ -47,6 +47,8 @@ required: - compatible - reg +additionalProperties: false + examples: - | #include <dt-bindings/gpio/gpio.h> diff --git a/Documentation/devicetree/bindings/hwmon/adi,axi-fan-control.yaml b/Documentation/devicetree/bindings/hwmon/adi,axi-fan-control.yaml index 57a240d2d026..7db78767c02d 100644 --- a/Documentation/devicetree/bindings/hwmon/adi,axi-fan-control.yaml +++ b/Documentation/devicetree/bindings/hwmon/adi,axi-fan-control.yaml @@ -2,7 +2,7 @@ # Copyright 2019 Analog Devices Inc. %YAML 1.2 --- -$id: http://devicetree.org/schemas/bindings/hwmon/adi,axi-fan-control.yaml# +$id: http://devicetree.org/schemas/hwmon/adi,axi-fan-control.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Analog Devices AXI FAN Control Device Tree Bindings @@ -47,7 +47,7 @@ required: examples: - | - fpga_axi: fpga-axi@0 { + fpga_axi: fpga-axi { #address-cells = <0x2>; #size-cells = <0x1>; diff --git a/Documentation/devicetree/bindings/hwmon/adi,ltc2947.yaml b/Documentation/devicetree/bindings/hwmon/adi,ltc2947.yaml index 6a742a51e2f9..44a63fffb4be 100644 --- a/Documentation/devicetree/bindings/hwmon/adi,ltc2947.yaml +++ b/Documentation/devicetree/bindings/hwmon/adi,ltc2947.yaml @@ -87,6 +87,8 @@ required: - reg +additionalProperties: false + examples: - | spi { diff --git a/Documentation/devicetree/bindings/hwmon/adt7475.yaml b/Documentation/devicetree/bindings/hwmon/adt7475.yaml index 76985034ea73..46c441574f98 100644 --- a/Documentation/devicetree/bindings/hwmon/adt7475.yaml +++ b/Documentation/devicetree/bindings/hwmon/adt7475.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/adt7475.yaml# +$id: http://devicetree.org/schemas/hwmon/adt7475.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: ADT7475 hwmon sensor diff --git a/Documentation/devicetree/bindings/hwmon/pmbus/ti,ucd90320.yaml b/Documentation/devicetree/bindings/hwmon/pmbus/ti,ucd90320.yaml index 5d42e1304202..e8feee38c76c 100644 --- a/Documentation/devicetree/bindings/hwmon/pmbus/ti,ucd90320.yaml +++ b/Documentation/devicetree/bindings/hwmon/pmbus/ti,ucd90320.yaml @@ -32,6 +32,8 @@ required: - compatible - reg +additionalProperties: false + examples: - | i2c { diff --git a/Documentation/devicetree/bindings/hwmon/ti,tmp513.yaml b/Documentation/devicetree/bindings/hwmon/ti,tmp513.yaml index 168235ad5d81..3f043e943668 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,tmp513.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,tmp513.yaml @@ -76,6 +76,8 @@ required: - compatible - reg +additionalProperties: false + examples: - | i2c { diff --git a/Documentation/devicetree/bindings/i2c/brcm,brcmstb-i2c.yaml b/Documentation/devicetree/bindings/i2c/brcm,brcmstb-i2c.yaml new file mode 100644 index 000000000000..edbca2476128 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/brcm,brcmstb-i2c.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/brcm,brcmstb-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom STB BSC IIC Master Controller + +maintainers: + - Kamal Dasu <kdasu.kdev@gmail.com> + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + enum: + - brcm,bcm2711-hdmi-i2c + - brcm,brcmstb-i2c + - brcm,brcmper-i2c + + reg: + minItems: 1 + maxItems: 2 + items: + - description: BSC register range + - description: Auto-I2C register range + + reg-names: + items: + - const: bsc + - const: auto-i2c + + interrupts: + maxItems: 1 + + interrupt-names: + maxItems: 1 + + clock-frequency: + enum: + - 46875 + - 50000 + - 93750 + - 97500 + - 187500 + - 200000 + - 375000 + - 390000 + +required: + - compatible + - reg + - clock-frequency + +unevaluatedProperties: false + +if: + properties: + compatible: + contains: + enum: + - brcm,bcm2711-hdmi-i2c + +then: + properties: + reg: + minItems: 2 + + required: + - reg-names + +else: + properties: + reg: + maxItems: 1 + +examples: + - | + bsca: i2c@f0406200 { + clock-frequency = <390000>; + compatible = "brcm,brcmstb-i2c"; + interrupt-parent = <&irq0_intc>; + reg = <0xf0406200 0x58>; + interrupts = <0x18>; + interrupt-names = "upg_bsca"; + }; + + - | + ddc0: i2c@7ef04500 { + compatible = "brcm,bcm2711-hdmi-i2c"; + reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>; + reg-names = "bsc", "auto-i2c"; + clock-frequency = <390000>; + }; + +... diff --git a/Documentation/devicetree/bindings/i2c/i2c-at91.txt b/Documentation/devicetree/bindings/i2c/i2c-at91.txt index d4bad86107b8..96c914e048f5 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-at91.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-at91.txt @@ -28,8 +28,13 @@ Optional properties: "atmel,sama5d4-i2c", "atmel,sama5d2-i2c", "microchip,sam9x60-i2c". +- scl-gpios: specify the gpio related to SCL pin +- sda-gpios: specify the gpio related to SDA pin +- pinctrl: add extra pinctrl to configure i2c pins to gpio function for i2c + bus recovery, call it "gpio" state - Child nodes conforming to i2c bus binding + Examples : i2c0: i2c@fff84000 { @@ -64,6 +69,11 @@ i2c0: i2c@f8034600 { clocks = <&flx0>; atmel,fifo-size = <16>; i2c-sda-hold-time-ns = <336>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA 31 GPIO_ACTIVE_HIGH>; wm8731: wm8731@1a { compatible = "wm8731"; diff --git a/Documentation/devicetree/bindings/i2c/i2c-brcmstb.txt b/Documentation/devicetree/bindings/i2c/i2c-brcmstb.txt deleted file mode 100644 index 0380609b177a..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-brcmstb.txt +++ /dev/null @@ -1,26 +0,0 @@ -Broadcom stb bsc iic master controller - -Required properties: - -- compatible: should be "brcm,brcmstb-i2c" or "brcm,brcmper-i2c" -- clock-frequency: 32-bit decimal value of iic master clock freqency in Hz - valid values are 375000, 390000, 187500, 200000 - 93750, 97500, 46875 and 50000 -- reg: specifies the base physical address and size of the registers - -Optional properties : - -- interrupts: specifies the interrupt number, the irq line to be used -- interrupt-names: Interrupt name string - -Example: - -bsca: i2c@f0406200 { - clock-frequency = <390000>; - compatible = "brcm,brcmstb-i2c"; - interrupt-parent = <&irq0_intc>; - reg = <0xf0406200 0x58>; - interrupts = <0x18>; - interrupt-names = "upg_bsca"; -}; - diff --git a/Documentation/devicetree/bindings/i2c/i2c-rk3x.txt b/Documentation/devicetree/bindings/i2c/i2c-rk3x.txt deleted file mode 100644 index 22f2eeb2c4c9..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-rk3x.txt +++ /dev/null @@ -1,68 +0,0 @@ -* Rockchip RK3xxx I2C controller - -This driver interfaces with the native I2C controller present in Rockchip -RK3xxx SoCs. - -Required properties : - - - reg : Offset and length of the register set for the device - - compatible: should be one of the following: - - "rockchip,rv1108-i2c": for rv1108 - - "rockchip,rk3066-i2c": for rk3066 - - "rockchip,rk3188-i2c": for rk3188 - - "rockchip,rk3228-i2c": for rk3228 - - "rockchip,rk3288-i2c": for rk3288 - - "rockchip,rk3328-i2c", "rockchip,rk3399-i2c": for rk3328 - - "rockchip,rk3399-i2c": for rk3399 - - interrupts : interrupt number - - clocks: See ../clock/clock-bindings.txt - - For older hardware (rk3066, rk3188, rk3228, rk3288): - - There is one clock that's used both to derive the functional clock - for the device and as the bus clock. - - For newer hardware (rk3399): specified by name - - "i2c": This is used to derive the functional clock. - - "pclk": This is the bus clock. - -Required on RK3066, RK3188 : - - - rockchip,grf : the phandle of the syscon node for the general register - file (GRF) - - on those SoCs an alias with the correct I2C bus ID (bit offset in the GRF) - is also required. - -Optional properties : - - - clock-frequency : SCL frequency to use (in Hz). If omitted, 100kHz is used. - - i2c-scl-rising-time-ns : Number of nanoseconds the SCL signal takes to rise - (t(r) in I2C specification). If not specified this is assumed to be - the maximum the specification allows(1000 ns for Standard-mode, - 300 ns for Fast-mode) which might cause slightly slower communication. - - i2c-scl-falling-time-ns : Number of nanoseconds the SCL signal takes to fall - (t(f) in the I2C specification). If not specified this is assumed to - be the maximum the specification allows (300 ns) which might cause - slightly slower communication. - - i2c-sda-falling-time-ns : Number of nanoseconds the SDA signal takes to fall - (t(f) in the I2C specification). If not specified we'll use the SCL - value since they are the same in nearly all cases. - -Example: - -aliases { - i2c0 = &i2c0; -} - -i2c0: i2c@2002d000 { - compatible = "rockchip,rk3188-i2c"; - reg = <0x2002d000 0x1000>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - - i2c-scl-rising-time-ns = <800>; - i2c-scl-falling-time-ns = <100>; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml b/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml new file mode 100644 index 000000000000..61eac76c84c4 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/i2c-rk3x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3xxx I2C controller + +description: + This driver interfaces with the native I2C controller present in Rockchip + RK3xxx SoCs. + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +# Everything else is described in the common file +properties: + compatible: + oneOf: + - const: rockchip,rv1108-i2c + - const: rockchip,rk3066-i2c + - const: rockchip,rk3188-i2c + - const: rockchip,rk3228-i2c + - const: rockchip,rk3288-i2c + - const: rockchip,rk3399-i2c + - items: + - enum: + - rockchip,rk3036-i2c + - rockchip,rk3368-i2c + - const: rockchip,rk3288-i2c + - items: + - enum: + - rockchip,px30-i2c + - rockchip,rk3308-i2c + - rockchip,rk3328-i2c + - const: rockchip,rk3399-i2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: + For older hardware (rk3066, rk3188, rk3228, rk3288) + there is one clock that is used both to derive the functional clock + for the device and as the bus clock. + For newer hardware (rk3399) this clock is used to derive + the functional clock + - description: + For newer hardware (rk3399) this is the bus clock + + clock-names: + minItems: 1 + items: + - const: i2c + - const: pclk + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Required on RK3066, RK3188 the phandle of the syscon node for + the general register file (GRF) + On those SoCs an alias with the correct I2C bus ID + (bit offset in the GRF) is also required. + + clock-frequency: + default: 100000 + description: + SCL frequency to use (in Hz). If omitted, 100kHz is used. + + i2c-scl-rising-time-ns: + default: 1000 + description: + Number of nanoseconds the SCL signal takes to rise + (t(r) in I2C specification). If not specified this is assumed to be + the maximum the specification allows(1000 ns for Standard-mode, + 300 ns for Fast-mode) which might cause slightly slower communication. + + i2c-scl-falling-time-ns: + default: 300 + description: + Number of nanoseconds the SCL signal takes to fall + (t(f) in the I2C specification). If not specified this is assumed to + be the maximum the specification allows (300 ns) which might cause + slightly slower communication. + + i2c-sda-falling-time-ns: + default: 300 + description: + Number of nanoseconds the SDA signal takes to fall + (t(f) in the I2C specification). If not specified we will use the SCL + value since they are the same in nearly all cases. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +if: + properties: + compatible: + contains: + enum: + - rockchip,rk3066-i2c + - rockchip,rk3188-i2c + +then: + required: + - rockchip,grf + +examples: + - | + #include <dt-bindings/clock/rk3188-cru-common.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + i2c0: i2c@2002d000 { + compatible = "rockchip,rk3188-i2c"; + reg = <0x2002d000 0x1000>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_I2C0>; + clock-names = "i2c"; + rockchip,grf = <&grf>; + i2c-scl-falling-time-ns = <100>; + i2c-scl-rising-time-ns = <800>; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-uniphier-f.txt b/Documentation/devicetree/bindings/i2c/i2c-uniphier-f.txt deleted file mode 100644 index 27fc6f8c798b..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-uniphier-f.txt +++ /dev/null @@ -1,25 +0,0 @@ -UniPhier I2C controller (FIFO-builtin) - -Required properties: -- compatible: should be "socionext,uniphier-fi2c". -- #address-cells: should be 1. -- #size-cells: should be 0. -- reg: offset and length of the register set for the device. -- interrupts: a single interrupt specifier. -- clocks: phandle to the input clock. - -Optional properties: -- clock-frequency: desired I2C bus frequency in Hz. The maximum supported - value is 400000. Defaults to 100000 if not specified. - -Examples: - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-uniphier.txt b/Documentation/devicetree/bindings/i2c/i2c-uniphier.txt deleted file mode 100644 index 26f9d95b3436..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-uniphier.txt +++ /dev/null @@ -1,25 +0,0 @@ -UniPhier I2C controller (FIFO-less) - -Required properties: -- compatible: should be "socionext,uniphier-i2c". -- #address-cells: should be 1. -- #size-cells: should be 0. -- reg: offset and length of the register set for the device. -- interrupts: a single interrupt specifier. -- clocks: phandle to the input clock. - -Optional properties: -- clock-frequency: desired I2C bus frequency in Hz. The maximum supported - value is 400000. Defaults to 100000 if not specified. - -Examples: - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58400000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 1>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; diff --git a/Documentation/devicetree/bindings/i2c/socionext,uniphier-fi2c.yaml b/Documentation/devicetree/bindings/i2c/socionext,uniphier-fi2c.yaml new file mode 100644 index 000000000000..15abc022968e --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/socionext,uniphier-fi2c.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/socionext,uniphier-fi2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier I2C controller (FIFO-builtin) + +maintainers: + - Masahiro Yamada <yamada.masahiro@socionext.com> + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + const: socionext,uniphier-fi2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: + minimum: 100000 + maximum: 400000 + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - interrupts + - clocks + +examples: + - | + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; diff --git a/Documentation/devicetree/bindings/i2c/socionext,uniphier-i2c.yaml b/Documentation/devicetree/bindings/i2c/socionext,uniphier-i2c.yaml new file mode 100644 index 000000000000..ef998def554e --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/socionext,uniphier-i2c.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/socionext,uniphier-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier I2C controller (FIFO-less) + +maintainers: + - Masahiro Yamada <yamada.masahiro@socionext.com> + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + const: socionext,uniphier-i2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: + minimum: 100000 + maximum: 400000 + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - interrupts + - clocks + +examples: + - | + i2c0: i2c@58400000 { + compatible = "socionext,uniphier-i2c"; + reg = <0x58400000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 1>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml index c602b6fe1c0c..d124eba1ce54 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml @@ -17,9 +17,13 @@ description: | properties: compatible: - enum: - - adi,adxl345 - - adi,adxl375 + oneOf: + - items: + - const: adi,adxl346 + - const: adi,adxl345 + - enum: + - adi,adxl345 + - adi,adxl375 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/iio/accel/bosch,bma400.yaml b/Documentation/devicetree/bindings/iio/accel/bosch,bma400.yaml index c1c6d6f223cf..8723a336229e 100644 --- a/Documentation/devicetree/bindings/iio/accel/bosch,bma400.yaml +++ b/Documentation/devicetree/bindings/iio/accel/bosch,bma400.yaml @@ -36,6 +36,8 @@ required: - compatible - reg +additionalProperties: false + examples: - | #include <dt-bindings/gpio/gpio.h> diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml index 84d25bd39488..d0913034b1d8 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml @@ -106,7 +106,6 @@ examples: spi-cpha; clocks = <&ad7192_mclk>; clock-names = "mclk"; - #interrupt-cells = <2>; interrupts = <25 0x2>; interrupt-parent = <&gpio>; dvdd-supply = <&dvdd>; diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml index 9acde6d2e2d9..a67ba67dab51 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml @@ -67,6 +67,8 @@ required: - compatible - reg +additionalProperties: false + examples: - | #include <dt-bindings/gpio/gpio.h> diff --git a/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml b/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml index 91ab9c842273..77605f17901c 100644 --- a/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml +++ b/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml @@ -53,6 +53,8 @@ required: - dout-gpios - avdd-supply +additionalProperties: false + examples: - | #include <dt-bindings/gpio/gpio.h> diff --git a/Documentation/devicetree/bindings/iio/adc/lltc,ltc2496.yaml b/Documentation/devicetree/bindings/iio/adc/lltc,ltc2496.yaml index 59009997dca0..118809a03279 100644 --- a/Documentation/devicetree/bindings/iio/adc/lltc,ltc2496.yaml +++ b/Documentation/devicetree/bindings/iio/adc/lltc,ltc2496.yaml @@ -32,6 +32,8 @@ required: - vref-supply - reg +additionalProperties: false + examples: - | spi { diff --git a/Documentation/devicetree/bindings/iio/adc/microchip,mcp3911.yaml b/Documentation/devicetree/bindings/iio/adc/microchip,mcp3911.yaml index 0ce290473fb0..8ffeceb6abae 100644 --- a/Documentation/devicetree/bindings/iio/adc/microchip,mcp3911.yaml +++ b/Documentation/devicetree/bindings/iio/adc/microchip,mcp3911.yaml @@ -52,6 +52,8 @@ required: - compatible - reg +additionalProperties: false + examples: - | spi { diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml index acf36eef728b..b1627441a0b2 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml @@ -69,6 +69,8 @@ required: - "#address-cells" - "#size-cells" +additionalProperties: false + patternProperties: "^filter@[0-9]+$": type: object diff --git a/Documentation/devicetree/bindings/iio/chemical/plantower,pms7003.yaml b/Documentation/devicetree/bindings/iio/chemical/plantower,pms7003.yaml index 19e53930ebf6..1fe561574019 100644 --- a/Documentation/devicetree/bindings/iio/chemical/plantower,pms7003.yaml +++ b/Documentation/devicetree/bindings/iio/chemical/plantower,pms7003.yaml @@ -38,6 +38,8 @@ required: - compatible - vcc-supply +additionalProperties: false + examples: - | serial { diff --git a/Documentation/devicetree/bindings/iio/chemical/sensirion,sps30.yaml b/Documentation/devicetree/bindings/iio/chemical/sensirion,sps30.yaml index 50a50a0d7070..a93d1972a5c2 100644 --- a/Documentation/devicetree/bindings/iio/chemical/sensirion,sps30.yaml +++ b/Documentation/devicetree/bindings/iio/chemical/sensirion,sps30.yaml @@ -24,6 +24,8 @@ required: - compatible - reg +additionalProperties: false + examples: - | i2c { diff --git a/Documentation/devicetree/bindings/iio/dac/ad5755.txt b/Documentation/devicetree/bindings/iio/dac/ad5755.txt index f0bbd7e1029b..502e1e55adbd 100644 --- a/Documentation/devicetree/bindings/iio/dac/ad5755.txt +++ b/Documentation/devicetree/bindings/iio/dac/ad5755.txt @@ -1,4 +1,4 @@ -* Analog Device AD5755 IIO Multi-Channel DAC Linux Driver +* Analog Devices AD5755 IIO Multi-Channel DAC Linux Driver Required properties: - compatible: Has to contain one of the following: diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml index d9c25cf4b92f..58d81ca43460 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml @@ -2,7 +2,7 @@ # Copyright 2020 Analog Devices Inc. %YAML 1.2 --- -$id: http://devicetree.org/schemas/bindings/iio/dac/adi,ad5770r.yaml# +$id: http://devicetree.org/schemas/iio/dac/adi,ad5770r.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Analog Devices AD5770R DAC device driver @@ -49,93 +49,86 @@ properties: asserted during driver probe. maxItems: 1 - channel0: + channel@0: description: Represents an external channel which are connected to the DAC. Channel 0 can act both as a current source and sink. type: object properties: - num: + reg: description: This represents the channel number. - items: - const: 0 + const: 0 adi,range-microamp: description: Output range of the channel. oneOf: - - $ref: /schemas/types.yaml#/definitions/int32-array - items: - - enum: [0 300000] - - enum: [-60000 0] - - enum: [-60000 300000] + - const: 0 + - const: 300000 + - items: + - const: -60000 + - const: 0 + - items: + - const: -60000 + - const: 300000 - channel1: + channel@1: description: Represents an external channel which are connected to the DAC. type: object properties: - num: + reg: description: This represents the channel number. - items: - const: 1 + const: 1 adi,range-microamp: description: Output range of the channel. - oneOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - items: - - enum: [0 140000] - - enum: [0 250000] + items: + - const: 0 + - enum: [ 140000, 250000 ] - channel2: + channel@2: description: Represents an external channel which are connected to the DAC. type: object properties: - num: + reg: description: This represents the channel number. - items: - const: 2 + const: 2 adi,range-microamp: description: Output range of the channel. - oneOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - items: - - enum: [0 140000] - - enum: [0 250000] + items: + - const: 0 + - enum: [ 55000, 150000 ] patternProperties: "^channel@([3-5])$": type: object description: Represents the external channels which are connected to the DAC. properties: - num: + reg: description: This represents the channel number. - items: - minimum: 3 - maximum: 5 + minimum: 3 + maximum: 5 adi,range-microamp: description: Output range of the channel. - oneOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - items: - - enum: [0 45000] - - enum: [0 100000] + items: + - const: 0 + - enum: [ 45000, 100000 ] required: - reg -- diff-channels -- channel0 -- channel1 -- channel2 -- channel3 -- channel4 -- channel5 +- channel@0 +- channel@1 +- channel@2 +- channel@3 +- channel@4 +- channel@5 examples: - | @@ -144,40 +137,42 @@ examples: #size-cells = <0>; ad5770r@0 { - compatible = "ad5770r"; + compatible = "adi,ad5770r"; reg = <0>; spi-max-frequency = <1000000>; vref-supply = <&vref>; adi,external-resistor; reset-gpios = <&gpio 22 0>; + #address-cells = <1>; + #size-cells = <0>; channel@0 { - num = <0>; - adi,range-microamp = <(-60000) 300000>; + reg = <0>; + adi,range-microamp = <0 300000>; }; channel@1 { - num = <1>; + reg = <1>; adi,range-microamp = <0 140000>; }; channel@2 { - num = <2>; + reg = <2>; adi,range-microamp = <0 55000>; }; channel@3 { - num = <3>; + reg = <3>; adi,range-microamp = <0 45000>; }; channel@4 { - num = <4>; + reg = <4>; adi,range-microamp = <0 45000>; }; channel@5 { - num = <5>; + reg = <5>; adi,range-microamp = <0 45000>; }; }; diff --git a/Documentation/devicetree/bindings/iio/dac/lltc,ltc1660.yaml b/Documentation/devicetree/bindings/iio/dac/lltc,ltc1660.yaml index a285eaba7125..e51a585bd5a3 100644 --- a/Documentation/devicetree/bindings/iio/dac/lltc,ltc1660.yaml +++ b/Documentation/devicetree/bindings/iio/dac/lltc,ltc1660.yaml @@ -34,6 +34,8 @@ required: - reg - vref-supply +additionalProperties: false + examples: - | spi { diff --git a/Documentation/devicetree/bindings/iio/light/adux1020.yaml b/Documentation/devicetree/bindings/iio/light/adux1020.yaml index 69bd5c06319d..d7d14f2f1c20 100644 --- a/Documentation/devicetree/bindings/iio/light/adux1020.yaml +++ b/Documentation/devicetree/bindings/iio/light/adux1020.yaml @@ -28,6 +28,8 @@ required: - compatible - reg +additionalProperties: false + examples: - | #include <dt-bindings/interrupt-controller/irq.h> diff --git a/Documentation/devicetree/bindings/iio/light/bh1750.yaml b/Documentation/devicetree/bindings/iio/light/bh1750.yaml index 1cc60d7ecfa0..1a88b3c253d5 100644 --- a/Documentation/devicetree/bindings/iio/light/bh1750.yaml +++ b/Documentation/devicetree/bindings/iio/light/bh1750.yaml @@ -28,6 +28,8 @@ required: - compatible - reg +additionalProperties: false + examples: - | i2c { diff --git a/Documentation/devicetree/bindings/iio/light/isl29018.yaml b/Documentation/devicetree/bindings/iio/light/isl29018.yaml index cbb00be8f359..0ea278b07d1c 100644 --- a/Documentation/devicetree/bindings/iio/light/isl29018.yaml +++ b/Documentation/devicetree/bindings/iio/light/isl29018.yaml @@ -38,6 +38,8 @@ required: - compatible - reg +additionalProperties: false + examples: - | #include <dt-bindings/interrupt-controller/irq.h> diff --git a/Documentation/devicetree/bindings/iio/light/noa1305.yaml b/Documentation/devicetree/bindings/iio/light/noa1305.yaml index 17e7f140b69b..fe7bfe1adbda 100644 --- a/Documentation/devicetree/bindings/iio/light/noa1305.yaml +++ b/Documentation/devicetree/bindings/iio/light/noa1305.yaml @@ -29,6 +29,8 @@ required: - compatible - reg +additionalProperties: false + examples: - | i2c { diff --git a/Documentation/devicetree/bindings/iio/light/stk33xx.yaml b/Documentation/devicetree/bindings/iio/light/stk33xx.yaml index aae8a6d627c9..f92bf7b2b7f0 100644 --- a/Documentation/devicetree/bindings/iio/light/stk33xx.yaml +++ b/Documentation/devicetree/bindings/iio/light/stk33xx.yaml @@ -30,6 +30,8 @@ required: - compatible - reg +additionalProperties: false + examples: - | #include <dt-bindings/interrupt-controller/irq.h> diff --git a/Documentation/devicetree/bindings/iio/light/tsl2583.yaml b/Documentation/devicetree/bindings/iio/light/tsl2583.yaml index e86ef64ecf03..7b92ba8cbb9f 100644 --- a/Documentation/devicetree/bindings/iio/light/tsl2583.yaml +++ b/Documentation/devicetree/bindings/iio/light/tsl2583.yaml @@ -32,6 +32,8 @@ required: - compatible - reg +additionalProperties: false + examples: - | i2c { diff --git a/Documentation/devicetree/bindings/iio/light/tsl2772.yaml b/Documentation/devicetree/bindings/iio/light/tsl2772.yaml index ed2c3d5eadf5..e8f7d1ada57b 100644 --- a/Documentation/devicetree/bindings/iio/light/tsl2772.yaml +++ b/Documentation/devicetree/bindings/iio/light/tsl2772.yaml @@ -62,6 +62,8 @@ required: - compatible - reg +additionalProperties: false + examples: - | #include <dt-bindings/interrupt-controller/irq.h> diff --git a/Documentation/devicetree/bindings/iio/light/veml6030.yaml b/Documentation/devicetree/bindings/iio/light/veml6030.yaml index 0ff9b11f9d18..fb19a2d7a849 100644 --- a/Documentation/devicetree/bindings/iio/light/veml6030.yaml +++ b/Documentation/devicetree/bindings/iio/light/veml6030.yaml @@ -45,6 +45,8 @@ required: - compatible - reg +additionalProperties: false + examples: - | #include <dt-bindings/interrupt-controller/irq.h> diff --git a/Documentation/devicetree/bindings/iio/pressure/asc,dlhl60d.yaml b/Documentation/devicetree/bindings/iio/pressure/asc,dlhl60d.yaml index 9f5ca9c42025..64c18f1693f0 100644 --- a/Documentation/devicetree/bindings/iio/pressure/asc,dlhl60d.yaml +++ b/Documentation/devicetree/bindings/iio/pressure/asc,dlhl60d.yaml @@ -33,6 +33,8 @@ required: - compatible - reg +additionalProperties: false + examples: - | #include <dt-bindings/interrupt-controller/irq.h> diff --git a/Documentation/devicetree/bindings/iio/pressure/bmp085.yaml b/Documentation/devicetree/bindings/iio/pressure/bmp085.yaml index 519137e5c170..49257f9251e8 100644 --- a/Documentation/devicetree/bindings/iio/pressure/bmp085.yaml +++ b/Documentation/devicetree/bindings/iio/pressure/bmp085.yaml @@ -25,6 +25,9 @@ properties: - bosch,bmp280 - bosch,bme280 + reg: + maxItems: 1 + vddd-supply: description: digital voltage regulator (see regulator/regulator.txt) @@ -49,6 +52,8 @@ required: - vddd-supply - vdda-supply +additionalProperties: false + examples: - | #include <dt-bindings/gpio/gpio.h> diff --git a/Documentation/devicetree/bindings/iio/proximity/devantech-srf04.yaml b/Documentation/devicetree/bindings/iio/proximity/devantech-srf04.yaml index 8afbac24c34e..f86f8b23ef18 100644 --- a/Documentation/devicetree/bindings/iio/proximity/devantech-srf04.yaml +++ b/Documentation/devicetree/bindings/iio/proximity/devantech-srf04.yaml @@ -74,6 +74,8 @@ required: - trig-gpios - echo-gpios +additionalProperties: false + examples: - | #include <dt-bindings/gpio/gpio.h> diff --git a/Documentation/devicetree/bindings/iio/proximity/parallax-ping.yaml b/Documentation/devicetree/bindings/iio/proximity/parallax-ping.yaml index a079c9921af6..ada55f186f3c 100644 --- a/Documentation/devicetree/bindings/iio/proximity/parallax-ping.yaml +++ b/Documentation/devicetree/bindings/iio/proximity/parallax-ping.yaml @@ -42,6 +42,8 @@ required: - compatible - ping-gpios +additionalProperties: false + examples: - | #include <dt-bindings/gpio/gpio.h> diff --git a/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml b/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml index d4922f9f0376..8fb46de6641d 100644 --- a/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml +++ b/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml @@ -123,12 +123,11 @@ patternProperties: sign. allOf: - $ref: /schemas/types.yaml#/definitions/uint64-matrix + minItems: 3 + maxItems: 64 items: - minItems: 3 - maxItems: 64 - items: - minItems: 2 - maxItems: 2 + minItems: 2 + maxItems: 2 "^diode@": type: object @@ -328,12 +327,11 @@ patternProperties: 78 and 79. allOf: - $ref: /schemas/types.yaml#/definitions/uint64-matrix + minItems: 3 + maxItems: 64 items: - minItems: 3 - maxItems: 64 - items: - minItems: 2 - maxItems: 2 + minItems: 2 + maxItems: 2 adi,custom-steinhart: description: @@ -398,6 +396,8 @@ required: - reg - interrupts +additionalProperties: false + examples: - | #include <dt-bindings/interrupt-controller/irq.h> @@ -463,16 +463,16 @@ examples: adi,sensor-type = <9>; //custom thermocouple adi,single-ended; adi,custom-thermocouple = /bits/ 64 - <(-50220000) 0 - (-30200000) 99100000 - (-5300000) 135400000 - 0 273150000 - 40200000 361200000 - 55300000 522100000 - 88300000 720300000 - 132200000 811200000 - 188700000 922500000 - 460400000 1000000000>; //10 pairs + <(-50220000) 0>, + <(-30200000) 99100000>, + <(-5300000) 135400000>, + <0 273150000>, + <40200000 361200000>, + <55300000 522100000>, + <88300000 720300000>, + <132200000 811200000>, + <188700000 922500000>, + <460400000 1000000000>; //10 pairs }; }; diff --git a/Documentation/devicetree/bindings/input/gpio-vibrator.yaml b/Documentation/devicetree/bindings/input/gpio-vibrator.yaml index b98bf9363c8f..2384465eaa19 100644 --- a/Documentation/devicetree/bindings/input/gpio-vibrator.yaml +++ b/Documentation/devicetree/bindings/input/gpio-vibrator.yaml @@ -26,6 +26,8 @@ required: - compatible - enable-gpios +additionalProperties: false + examples: - | #include <dt-bindings/gpio/gpio.h> diff --git a/Documentation/devicetree/bindings/input/iqs62x-keys.yaml b/Documentation/devicetree/bindings/input/iqs62x-keys.yaml new file mode 100644 index 000000000000..5625c222903a --- /dev/null +++ b/Documentation/devicetree/bindings/input/iqs62x-keys.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/iqs62x-keys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Azoteq IQS620A/621/622/624/625 Keys and Switches + +maintainers: + - Jeff LaBundy <jeff@labundy.com> + +description: | + The Azoteq IQS620A, IQS621, IQS622, IQS624 and IQS625 multi-function sensors + feature a variety of self-capacitive, mutual-inductive and Hall-effect sens- + ing capabilities that can facilitate a variety of contactless key and switch + applications. + + These functions are collectively represented by a "keys" child node from the + parent MFD driver. See Documentation/devicetree/bindings/mfd/iqs62x.yaml for + further details and examples. Sensor hardware configuration (self-capacitive + vs. mutual-inductive, etc.) is selected based on the device's firmware. + +properties: + compatible: + enum: + - azoteq,iqs620a-keys + - azoteq,iqs621-keys + - azoteq,iqs622-keys + - azoteq,iqs624-keys + - azoteq,iqs625-keys + + linux,keycodes: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + - minItems: 1 + maxItems: 16 + description: | + Specifies the numeric keycodes associated with each available touch or + proximity event according to the following table. An 'x' indicates the + event is supported for a given device. Specify 0 for unused events. + + ------------------------------------------------------------------------- + | # | Event | IQS620A | IQS621 | IQS622 | IQS624 | IQS625 | + ------------------------------------------------------------------------- + | 0 | CH0 Touch | x | x | x | x | x | + | | Antenna 1 Touch* | x | | | | | + ------------------------------------------------------------------------- + | 1 | CH0 Proximity | x | x | x | x | x | + | | Antenna 1 Prox.* | x | | | | | + ------------------------------------------------------------------------- + | 2 | CH1 Touch | x | x | x | x | x | + | | Ant. 1 Deep Touch* | x | | | | | + ------------------------------------------------------------------------- + | 3 | CH1 Proximity | x | x | x | x | x | + ------------------------------------------------------------------------- + | 4 | CH2 Touch | x | | | | | + ------------------------------------------------------------------------- + | 5 | CH2 Proximity | x | | | | | + | | Antenna 2 Prox.* | x | | | | | + ------------------------------------------------------------------------- + | 6 | Metal (+) Touch** | x | x | | | | + | | Ant. 2 Deep Touch* | x | | | | | + ------------------------------------------------------------------------- + | 7 | Metal (+) Prox.** | x | x | | | | + | | Antenna 2 Touch* | x | | | | | + ------------------------------------------------------------------------- + | 8 | Metal (-) Touch** | x | x | | | | + ------------------------------------------------------------------------- + | 9 | Metal (-) Prox.** | x | x | | | | + ------------------------------------------------------------------------- + | 10 | SAR Active*** | x | | x | | | + ------------------------------------------------------------------------- + | 11 | SAR Quick Rel.*** | x | | x | | | + ------------------------------------------------------------------------- + | 12 | SAR Movement*** | x | | x | | | + ------------------------------------------------------------------------- + | 13 | SAR Filter Halt*** | x | | x | | | + ------------------------------------------------------------------------- + | 14 | Wheel Up | | | | x | | + ------------------------------------------------------------------------- + | 15 | Wheel Down | | | | x | | + ------------------------------------------------------------------------- + * Two-channel SAR. Replaces CH0-2 plus metal touch and proximity events + if enabled via firmware. + ** "+" and "-" refer to the polarity of a channel's delta (LTA - counts), + where "LTA" is defined as the channel's long-term average. + *** One-channel SAR. Replaces CH0-2 touch and proximity events if enabled + via firmware. + +patternProperties: + "^hall-switch-(north|south)$": + type: object + description: + Represents north/south-field Hall-effect sensor touch or proximity + events. Note that north/south-field orientation is reversed on the + IQS620AXzCSR device due to its flip-chip package. + + properties: + linux,code: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Numeric switch code associated with the event. + + azoteq,use-prox: + $ref: /schemas/types.yaml#/definitions/flag + description: + If present, specifies that Hall-effect sensor reporting should + use the device's wide-range proximity threshold instead of its + close-range touch threshold (default). + + required: + - linux,code + + additionalProperties: false + +if: + properties: + compatible: + contains: + enum: + - azoteq,iqs624-keys + - azoteq,iqs625-keys +then: + patternProperties: + "^hall-switch-(north|south)$": false + +required: + - compatible + - linux,keycodes + +additionalProperties: false + +... diff --git a/Documentation/devicetree/bindings/input/max77650-onkey.yaml b/Documentation/devicetree/bindings/input/max77650-onkey.yaml index 2f2e0b6ebbbd..3a2ad6ec64db 100644 --- a/Documentation/devicetree/bindings/input/max77650-onkey.yaml +++ b/Documentation/devicetree/bindings/input/max77650-onkey.yaml @@ -33,3 +33,6 @@ properties: required: - compatible +additionalProperties: false + +... diff --git a/Documentation/devicetree/bindings/input/st,stpmic1-onkey.txt b/Documentation/devicetree/bindings/input/st,stpmic1-onkey.txt deleted file mode 100644 index eb8e83736c02..000000000000 --- a/Documentation/devicetree/bindings/input/st,stpmic1-onkey.txt +++ /dev/null @@ -1,28 +0,0 @@ -STMicroelectronics STPMIC1 Onkey - -Required properties: - -- compatible = "st,stpmic1-onkey"; -- interrupts: interrupt line to use -- interrupt-names = "onkey-falling", "onkey-rising" - onkey-falling: happens when onkey is pressed; IT_PONKEY_F of pmic - onkey-rising: happens when onkey is released; IT_PONKEY_R of pmic - -Optional properties: - -- st,onkey-clear-cc-flag: onkey is able power on after an - over-current shutdown event. -- st,onkey-pu-inactive: onkey pull up is not active -- power-off-time-sec: Duration in seconds which the key should be kept - pressed for device to power off automatically (from 1 to 16 seconds). - see See Documentation/devicetree/bindings/input/input.yaml - -Example: - -onkey { - compatible = "st,stpmic1-onkey"; - interrupt-parent = <&pmic>; - interrupts = <IT_PONKEY_F 0>,<IT_PONKEY_R 1>; - interrupt-names = "onkey-falling", "onkey-rising"; - power-off-time-sec = <10>; -}; diff --git a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt deleted file mode 100644 index 0e57315e9cbd..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt +++ /dev/null @@ -1,77 +0,0 @@ -FocalTech EDT-FT5x06 Polytouch driver -===================================== - -There are 5 variants of the chip for various touch panel sizes -FT5206GE1 2.8" .. 3.8" -FT5306DE4 4.3" .. 7" -FT5406EE8 7" .. 8.9" -FT5506EEG 7" .. 8.9" -FT5726NEI 5.7” .. 11.6" - -The software interface is identical for all those chips, so that -currently there is no need for the driver to distinguish between the -different chips. Nevertheless distinct compatible strings are used so -that a distinction can be added if necessary without changing the DT -bindings. - - -Required properties: - - compatible: "edt,edt-ft5206" - or: "edt,edt-ft5306" - or: "edt,edt-ft5406" - or: "edt,edt-ft5506" - or: "evervision,ev-ft5726" - or: "focaltech,ft6236" - - - reg: I2C slave address of the chip (0x38) - - interrupts: interrupt specification for the touchdetect - interrupt - -Optional properties: - - reset-gpios: GPIO specification for the RESET input - - wake-gpios: GPIO specification for the WAKE input - - vcc-supply: Regulator that supplies the touchscreen - - - pinctrl-names: should be "default" - - pinctrl-0: a phandle pointing to the pin settings for the - control gpios - - - wakeup-source: If present the device will act as wakeup-source - - - threshold: allows setting the "click"-threshold in the range - from 0 to 80. - - - gain: allows setting the sensitivity in the range from 0 to - 31. Note that lower values indicate higher - sensitivity. - - - offset: allows setting the edge compensation in the range from - 0 to 31. - - - offset-x: Same as offset, but applies only to the horizontal position. - Range from 0 to 80, only supported by evervision,ev-ft5726 - devices. - - - offset-y: Same as offset, but applies only to the vertical position. - Range from 0 to 80, only supported by evervision,ev-ft5726 - devices. - - - touchscreen-size-x : See touchscreen.txt - - touchscreen-size-y : See touchscreen.txt - - touchscreen-fuzz-x : See touchscreen.txt - - touchscreen-fuzz-y : See touchscreen.txt - - touchscreen-inverted-x : See touchscreen.txt - - touchscreen-inverted-y : See touchscreen.txt - - touchscreen-swapped-x-y : See touchscreen.txt - -Example: - polytouch: edt-ft5x06@38 { - compatible = "edt,edt-ft5406", "edt,edt-ft5x06"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&edt_ft5x06_pins>; - interrupt-parent = <&gpio2>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; - wake-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml new file mode 100644 index 000000000000..383d64a91854 --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/edt-ft5x06.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FocalTech EDT-FT5x06 Polytouch Bindings + +description: | + There are 5 variants of the chip for various touch panel sizes + FT5206GE1 2.8" .. 3.8" + FT5306DE4 4.3" .. 7" + FT5406EE8 7" .. 8.9" + FT5506EEG 7" .. 8.9" + FT5726NEI 5.7” .. 11.6" + +maintainers: + - Dmitry Torokhov <dmitry.torokhov@gmail.com> + +allOf: + - $ref: touchscreen.yaml# + - if: + properties: + compatible: + contains: + enum: + - evervision,ev-ft5726 + + then: + properties: + offset-x: true + offset-y: true + +properties: + compatible: + enum: + - edt,edt-ft5206 + - edt,edt-ft5306 + - edt,edt-ft5406 + - edt,edt-ft5506 + - evervision,ev-ft5726 + - focaltech,ft6236 + + reg: + const: 0x38 + + interrupts: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + wake-gpios: + maxItems: 1 + + wakeup-source: true + + vcc-supply: + maxItems: 1 + + gain: + description: Allows setting the sensitivity in the range from 0 to 31. + Note that lower values indicate higher sensitivity. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + - maximum: 31 + + offset: + description: Allows setting the edge compensation in the range from 0 to 31. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + - maximum: 31 + + offset-x: + description: Same as offset, but applies only to the horizontal position. + Range from 0 to 80, only supported by evervision,ev-ft5726 devices. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + - maximum: 80 + + offset-y: + description: Same as offset, but applies only to the vertical position. + Range from 0 to 80, only supported by evervision,ev-ft5726 devices. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + - maximum: 80 + + touchscreen-size-x: true + touchscreen-size-y: true + touchscreen-fuzz-x: true + touchscreen-fuzz-y: true + touchscreen-inverted-x: true + touchscreen-inverted-y: true + touchscreen-swapped-x-y: true + interrupt-controller: true + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + edt-ft5x06@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&gpio2>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + wake-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml b/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml index c99ed3934d7e..c8ea9434c9cc 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml @@ -21,6 +21,8 @@ properties: - goodix,gt911 - goodix,gt9110 - goodix,gt912 + - goodix,gt9147 + - goodix,gt917s - goodix,gt927 - goodix,gt9271 - goodix,gt928 diff --git a/Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml b/Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml new file mode 100644 index 000000000000..5971fc1df08d --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,bcm-voter.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm BCM-Voter Interconnect + +maintainers: + - Georgi Djakov <georgi.djakov@linaro.org> + +description: | + The Bus Clock Manager (BCM) is a dedicated hardware accelerator that manages + shared system resources by aggregating requests from multiple Resource State + Coordinators (RSC). Interconnect providers are able to vote for aggregated + thresholds values from consumers by communicating through their respective + RSCs. + +properties: + compatible: + enum: + - qcom,bcm-voter + +required: + - compatible + +additionalProperties: false + +examples: + # Example 1: apps bcm_voter on SDM845 SoC should be defined inside &apps_rsc node + # as defined in Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt + - | + + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; + + # Example 2: disp bcm_voter on SDM845 should be defined inside &disp_rsc node + # as defined in Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt + - | + + disp_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; +... diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml new file mode 100644 index 000000000000..91f70c9067d1 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider + +maintainers: + - Sibi Sankar <sibis@codeaurora.org> + +description: + L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM. + The OSM L3 interconnect provider aggregates the L3 bandwidth requests + from CPU/GPU and relays it to the OSM. + +properties: + compatible: + enum: + - qcom,sc7180-osm-l3 + - qcom,sdm845-osm-l3 + + reg: + maxItems: 1 + + clocks: + items: + - description: xo clock + - description: alternate clock + + clock-names: + items: + - const: xo + - const: alternate + + '#interconnect-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#interconnect-cells' + +additionalProperties: false + +examples: + - | + + #define GPLL0 165 + #define RPMH_CXO_CLK 0 + + osm_l3: interconnect@17d41000 { + compatible = "qcom,sdm845-osm-l3"; + reg = <0x17d41000 0x1400>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sc7180.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sc7180.yaml new file mode 100644 index 000000000000..50f78f87f3fb --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,sc7180.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,sc7180.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC7180 Network-On-Chip Interconnect + +maintainers: + - Odelu Kukatla <okukatla@codeaurora.org> + +description: | + SC7180 interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is + able to communicate with the BCM through the Resource State Coordinator (RSC) + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. + +properties: + reg: + maxItems: 1 + + compatible: + enum: + - qcom,sc7180-aggre1-noc + - qcom,sc7180-aggre2-noc + - qcom,sc7180-camnoc-virt + - qcom,sc7180-compute-noc + - qcom,sc7180-config-noc + - qcom,sc7180-dc-noc + - qcom,sc7180-gem-noc + - qcom,sc7180-ipa-virt + - qcom,sc7180-mc-virt + - qcom,sc7180-mmss-noc + - qcom,sc7180-npu-noc + - qcom,sc7180-qup-virt + - qcom,sc7180-system-noc + + '#interconnect-cells': + const: 1 + + qcom,bcm-voters: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + List of phandles to qcom,bcm-voter nodes that are required by + this interconnect to send RPMh commands. + + qcom,bcm-voter-names: + $ref: /schemas/types.yaml#/definitions/string-array + description: | + Names for each of the qcom,bcm-voters specified. + +required: + - compatible + - reg + - '#interconnect-cells' + - qcom,bcm-voters + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interconnect/qcom,sc7180.h> + + config_noc: interconnect@1500000 { + compatible = "qcom,sc7180-config-noc"; + reg = <0 0x01500000 0 0x28000>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + compatible = "qcom,sc7180-system-noc"; + reg = <0 0x01620000 0 0x17080>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,sc7180-mmss-noc"; + reg = <0 0x01740000 0 0x1c100>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sdm845.txt b/Documentation/devicetree/bindings/interconnect/qcom,sdm845.txt deleted file mode 100644 index 5c4f1d911630..000000000000 --- a/Documentation/devicetree/bindings/interconnect/qcom,sdm845.txt +++ /dev/null @@ -1,24 +0,0 @@ -Qualcomm SDM845 Network-On-Chip interconnect driver binding ------------------------------------------------------------ - -SDM845 interconnect providers support system bandwidth requirements through -RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is -able to communicate with the BCM through the Resource State Coordinator (RSC) -associated with each execution environment. Provider nodes must reside within -an RPMh device node pertaining to their RSC and each provider maps to a single -RPMh resource. - -Required properties : -- compatible : shall contain only one of the following: - "qcom,sdm845-rsc-hlos" -- #interconnect-cells : should contain 1 - -Examples: - -apps_rsc: rsc { - rsc_hlos: interconnect { - compatible = "qcom,sdm845-rsc-hlos"; - #interconnect-cells = <1>; - }; -}; - diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml new file mode 100644 index 000000000000..8b087e0b0b81 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,sdm845.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM845 Network-On-Chip Interconnect + +maintainers: + - Georgi Djakov <georgi.djakov@linaro.org> + +description: | + SDM845 interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is + able to communicate with the BCM through the Resource State Coordinator (RSC) + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. + +properties: + reg: + maxItems: 1 + + compatible: + enum: + - qcom,sdm845-aggre1-noc + - qcom,sdm845-aggre2-noc + - qcom,sdm845-config-noc + - qcom,sdm845-dc-noc + - qcom,sdm845-gladiator-noc + - qcom,sdm845-mem-noc + - qcom,sdm845-mmss-noc + - qcom,sdm845-system-noc + + '#interconnect-cells': + const: 1 + + qcom,bcm-voters: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + List of phandles to qcom,bcm-voter nodes that are required by + this interconnect to send RPMh commands. + + qcom,bcm-voter-names: + $ref: /schemas/types.yaml#/definitions/string-array + description: | + Names for each of the qcom,bcm-voters specified. + +required: + - compatible + - reg + - '#interconnect-cells' + - qcom,bcm-voters + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interconnect/qcom,sdm845.h> + + mem_noc: interconnect@1380000 { + compatible = "qcom,sdm845-mem-noc"; + reg = <0 0x01380000 0 0x27200>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,sdm845-mmss-noc"; + reg = <0 0x01740000 0 0x1c1000>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "apps", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml index 507c141ea760..ccc507f384d2 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml @@ -44,6 +44,8 @@ required: - interrupt-controller - '#interrupt-cells' +additionalProperties: false + examples: - | intcon: interrupt-controller@c8003000 { diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml index 9c6b91fee477..26f1fcf0857a 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml @@ -56,9 +56,8 @@ properties: cell with zero. allOf: - $ref: /schemas/types.yaml#/definitions/uint32-array - - items: - minItems: 4 - maxItems: 4 + - minItems: 4 + maxItems: 4 required: diff --git a/Documentation/devicetree/bindings/interrupt-controller/msi.txt b/Documentation/devicetree/bindings/interrupt-controller/msi.txt index c60c034dcf19..c20b51df7138 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/msi.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/msi.txt @@ -98,7 +98,7 @@ Example }; msi_c: msi-controller@c { - reg = <0xb 0xf00>; + reg = <0xc 0xf00>; compatible = "vendor-b,another-controller"; msi-controller; /* Each device has some unique ID */ diff --git a/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.txt b/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.txt deleted file mode 100644 index 48e71d3ac2ad..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.txt +++ /dev/null @@ -1,32 +0,0 @@ -UniPhier AIDET - -UniPhier AIDET (ARM Interrupt Detector) is an add-on block for ARM GIC (Generic -Interrupt Controller). GIC itself can handle only high level and rising edge -interrupts. The AIDET provides logic inverter to support low level and falling -edge interrupts. - -Required properties: -- compatible: Should be one of the following: - "socionext,uniphier-ld4-aidet" - for LD4 SoC - "socionext,uniphier-pro4-aidet" - for Pro4 SoC - "socionext,uniphier-sld8-aidet" - for sLD8 SoC - "socionext,uniphier-pro5-aidet" - for Pro5 SoC - "socionext,uniphier-pxs2-aidet" - for PXs2/LD6b SoC - "socionext,uniphier-ld11-aidet" - for LD11 SoC - "socionext,uniphier-ld20-aidet" - for LD20 SoC - "socionext,uniphier-pxs3-aidet" - for PXs3 SoC -- reg: Specifies offset and length of the register set for the device. -- interrupt-controller: Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an interrupt - source. The value should be 2. The first cell defines the interrupt number - (corresponds to the SPI interrupt number of GIC). The second cell specifies - the trigger type as defined in interrupts.txt in this directory. - -Example: - - aidet: aidet@5fc20000 { - compatible = "socionext,uniphier-pro4-aidet"; - reg = <0x5fc20000 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.yaml b/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.yaml new file mode 100644 index 000000000000..f89ebde76dab --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/socionext,uniphier-aidet.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier AIDET + +description: | + UniPhier AIDET (ARM Interrupt Detector) is an add-on block for ARM GIC + (Generic Interrupt Controller). GIC itself can handle only high level and + rising edge interrupts. The AIDET provides logic inverter to support low + level and falling edge interrupts. + +maintainers: + - Masahiro Yamada <yamada.masahiro@socionext.com> + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + enum: + - socionext,uniphier-ld4-aidet + - socionext,uniphier-pro4-aidet + - socionext,uniphier-sld8-aidet + - socionext,uniphier-pro5-aidet + - socionext,uniphier-pxs2-aidet + - socionext,uniphier-ld6b-aidet + - socionext,uniphier-ld11-aidet + - socionext,uniphier-ld20-aidet + - socionext,uniphier-pxs3-aidet + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + description: | + The first cell defines the interrupt number (corresponds to the SPI + interrupt number of GIC). The second cell specifies the trigger type as + defined in interrupts.txt in this directory. + const: 2 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller@5fc20000 { + compatible = "socionext,uniphier-pro4-aidet"; + reg = <0x5fc20000 0x200>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/iommu/samsung,sysmmu.yaml b/Documentation/devicetree/bindings/iommu/samsung,sysmmu.yaml index 7cdd3aaa2ba4..0e33cd9e010e 100644 --- a/Documentation/devicetree/bindings/iommu/samsung,sysmmu.yaml +++ b/Documentation/devicetree/bindings/iommu/samsung,sysmmu.yaml @@ -80,6 +80,8 @@ required: - clock-names - "#iommu-cells" +additionalProperties: false + examples: - | #include <dt-bindings/clock/exynos5250.h> diff --git a/Documentation/devicetree/bindings/ipmi/aspeed-kcs-bmc.txt b/Documentation/devicetree/bindings/ipmi/aspeed-kcs-bmc.txt index d98a9bf45d6c..193e71ca96b0 100644 --- a/Documentation/devicetree/bindings/ipmi/aspeed-kcs-bmc.txt +++ b/Documentation/devicetree/bindings/ipmi/aspeed-kcs-bmc.txt @@ -1,9 +1,10 @@ -* Aspeed KCS (Keyboard Controller Style) IPMI interface +# Aspeed KCS (Keyboard Controller Style) IPMI interface The Aspeed SOCs (AST2400 and AST2500) are commonly used as BMCs (Baseboard Management Controllers) and the KCS interface can be used to perform in-band IPMI communication with their host. +## v1 Required properties: - compatible : should be one of "aspeed,ast2400-kcs-bmc" @@ -12,14 +13,21 @@ Required properties: - kcs_chan : The LPC channel number in the controller - kcs_addr : The host CPU IO map address +## v2 +Required properties: +- compatible : should be one of + "aspeed,ast2400-kcs-bmc-v2" + "aspeed,ast2500-kcs-bmc-v2" +- reg : The address and size of the IDR, ODR and STR registers +- interrupts : interrupt generated by the controller +- aspeed,lpc-io-reg : The host CPU LPC IO address for the device Example: - kcs3: kcs3@0 { - compatible = "aspeed,ast2500-kcs-bmc"; - reg = <0x0 0x80>; + kcs3: kcs@24 { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; + aspeed,lpc-reg = <0xca2>; interrupts = <8>; - kcs_chan = <3>; - kcs_addr = <0xCA2>; status = "okay"; }; diff --git a/Documentation/devicetree/bindings/leds/common.yaml b/Documentation/devicetree/bindings/leds/common.yaml index c60b994fe116..4c270fde4567 100644 --- a/Documentation/devicetree/bindings/leds/common.yaml +++ b/Documentation/devicetree/bindings/leds/common.yaml @@ -167,13 +167,13 @@ examples: led-controller { compatible = "gpio-leds"; - led0 { + led-0 { function = LED_FUNCTION_STATUS; linux,default-trigger = "heartbeat"; gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; }; - led1 { + led-1 { function = LED_FUNCTION_USB; gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; trigger-sources = <&ohci_port1>, <&ehci_port1>; diff --git a/Documentation/devicetree/bindings/leds/leds-max77650.yaml b/Documentation/devicetree/bindings/leds/leds-max77650.yaml index 8c43f1e1bf7d..c6f96cabd4d1 100644 --- a/Documentation/devicetree/bindings/leds/leds-max77650.yaml +++ b/Documentation/devicetree/bindings/leds/leds-max77650.yaml @@ -49,3 +49,6 @@ required: - compatible - "#address-cells" - "#size-cells" +additionalProperties: false + +... diff --git a/Documentation/devicetree/bindings/leds/rohm,bd71828-leds.yaml b/Documentation/devicetree/bindings/leds/rohm,bd71828-leds.yaml index b50f4bcc98f1..90edf9d33b33 100644 --- a/Documentation/devicetree/bindings/leds/rohm,bd71828-leds.yaml +++ b/Documentation/devicetree/bindings/leds/rohm,bd71828-leds.yaml @@ -50,3 +50,6 @@ patternProperties: required: - compatible +additionalProperties: false + +... diff --git a/Documentation/devicetree/bindings/mailbox/amlogic,meson-gxbb-mhu.yaml b/Documentation/devicetree/bindings/mailbox/amlogic,meson-gxbb-mhu.yaml index 319280563648..aa2b3bf56b57 100644 --- a/Documentation/devicetree/bindings/mailbox/amlogic,meson-gxbb-mhu.yaml +++ b/Documentation/devicetree/bindings/mailbox/amlogic,meson-gxbb-mhu.yaml @@ -41,6 +41,8 @@ required: - interrupts - "#mbox-cells" +additionalProperties: false + examples: - | mailbox@c883c404 { diff --git a/Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml b/Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml index 335717e15970..37d77e065491 100644 --- a/Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml +++ b/Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml @@ -124,6 +124,8 @@ required: - amlogic,ao-sysctrl - amlogic,canvas +additionalProperties: false + examples: - | vdec: video-decoder@c8820000 { diff --git a/Documentation/devicetree/bindings/media/amlogic,meson-gx-ao-cec.yaml b/Documentation/devicetree/bindings/media/amlogic,meson-gx-ao-cec.yaml index 41197578f19a..95ffa8bc0533 100644 --- a/Documentation/devicetree/bindings/media/amlogic,meson-gx-ao-cec.yaml +++ b/Documentation/devicetree/bindings/media/amlogic,meson-gx-ao-cec.yaml @@ -24,6 +24,12 @@ properties: reg: maxItems: 1 + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + interrupts: maxItems: 1 @@ -47,7 +53,6 @@ allOf: - description: AO-CEC clock clock-names: - maxItems: 1 items: - const: core @@ -66,7 +71,6 @@ allOf: - description: AO-CEC clock generator source clock-names: - maxItems: 1 items: - const: oscin @@ -78,6 +82,8 @@ required: - clocks - clock-names +additionalProperties: false + examples: - | cec_AO: cec@100 { @@ -88,4 +94,3 @@ examples: clock-names = "core"; hdmi-phandle = <&hdmi_tx>; }; - diff --git a/Documentation/devicetree/bindings/media/renesas,ceu.yaml b/Documentation/devicetree/bindings/media/renesas,ceu.yaml index 8e9251a0f9ef..fcb5f13704a5 100644 --- a/Documentation/devicetree/bindings/media/renesas,ceu.yaml +++ b/Documentation/devicetree/bindings/media/renesas,ceu.yaml @@ -59,6 +59,8 @@ required: - interrupts - port +additionalProperties: false + examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> diff --git a/Documentation/devicetree/bindings/media/renesas,vin.txt b/Documentation/devicetree/bindings/media/renesas,vin.txt deleted file mode 100644 index 5eefd62ac5c5..000000000000 --- a/Documentation/devicetree/bindings/media/renesas,vin.txt +++ /dev/null @@ -1,217 +0,0 @@ -Renesas R-Car Video Input driver (rcar_vin) -------------------------------------------- - -The rcar_vin device provides video input capabilities for the Renesas R-Car -family of devices. - -Each VIN instance has a single parallel input that supports RGB and YUV video, -with both external synchronization and BT.656 synchronization for the latter. -Depending on the instance the VIN input is connected to external SoC pins, or -on Gen3 and RZ/G2 platforms to a CSI-2 receiver. - - - compatible: Must be one or more of the following - - "renesas,vin-r8a7743" for the R8A7743 device - - "renesas,vin-r8a7744" for the R8A7744 device - - "renesas,vin-r8a7745" for the R8A7745 device - - "renesas,vin-r8a77470" for the R8A77470 device - - "renesas,vin-r8a774a1" for the R8A774A1 device - - "renesas,vin-r8a774b1" for the R8A774B1 device - - "renesas,vin-r8a774c0" for the R8A774C0 device - - "renesas,vin-r8a7778" for the R8A7778 device - - "renesas,vin-r8a7779" for the R8A7779 device - - "renesas,vin-r8a7790" for the R8A7790 device - - "renesas,vin-r8a7791" for the R8A7791 device - - "renesas,vin-r8a7792" for the R8A7792 device - - "renesas,vin-r8a7793" for the R8A7793 device - - "renesas,vin-r8a7794" for the R8A7794 device - - "renesas,vin-r8a7795" for the R8A7795 device - - "renesas,vin-r8a7796" for the R8A7796 device - - "renesas,vin-r8a77965" for the R8A77965 device - - "renesas,vin-r8a77970" for the R8A77970 device - - "renesas,vin-r8a77980" for the R8A77980 device - - "renesas,vin-r8a77990" for the R8A77990 device - - "renesas,vin-r8a77995" for the R8A77995 device - - "renesas,rcar-gen2-vin" for a generic R-Car Gen2 or RZ/G1 compatible - device. - - When compatible with the generic version nodes must list the - SoC-specific version corresponding to the platform first - followed by the generic version. - - - reg: the register base and size for the device registers - - interrupts: the interrupt for the device - - clocks: Reference to the parent clock - -The per-board settings for Gen2 and RZ/G1 platforms: - -- port - sub-node describing a single endpoint connected to the VIN - from external SoC pins as described in video-interfaces.txt[1]. - Only the first one will be considered as each vin interface has one - input port. - - - Optional properties for endpoint nodes: - - hsync-active: see [1] for description. Default is active high. - - vsync-active: see [1] for description. Default is active high. - If both HSYNC and VSYNC polarities are not specified, embedded - synchronization is selected. - - field-active-even: see [1] for description. Default is active high. - - bus-width: see [1] for description. The selected bus width depends on - the SoC type and selected input image format. - Valid values are: 8, 10, 12, 16, 24 and 32. - - data-shift: see [1] for description. Valid values are 0 and 8. - - data-enable-active: polarity of CLKENB signal, see [1] for - description. Default is active high. - -The per-board settings for Gen3 and RZ/G2 platforms: - -Gen3 and RZ/G2 platforms can support both a single connected parallel input -source from external SoC pins (port@0) and/or multiple parallel input sources -from local SoC CSI-2 receivers (port@1) depending on SoC. - -- renesas,id - ID number of the VIN, VINx in the documentation. -- ports - - port@0 - sub-node describing a single endpoint connected to the VIN - from external SoC pins as described in video-interfaces.txt[1]. - Describing more than one endpoint in port@0 is invalid. Only VIN - instances that are connected to external pins should have port@0. - - Endpoint nodes of port@0 support the optional properties listed in - the Gen2 per-board settings description. - - - port@1 - sub-nodes describing one or more endpoints connected to - the VIN from local SoC CSI-2 receivers. The endpoint numbers must - use the following schema. - - - endpoint@0 - sub-node describing the endpoint connected to CSI20 - - endpoint@1 - sub-node describing the endpoint connected to CSI21 - - endpoint@2 - sub-node describing the endpoint connected to CSI40 - - endpoint@3 - sub-node describing the endpoint connected to CSI41 - - Endpoint nodes of port@1 do not support any optional endpoint property. - -Device node example for Gen2 platforms --------------------------------------- - - aliases { - vin0 = &vin0; - }; - - vin0: vin@e6ef0000 { - compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; - clocks = <&mstp8_clks R8A7790_CLK_VIN0>; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - -Board setup example for Gen2 platforms (vin1 composite video input) -------------------------------------------------------------------- - -&i2c2 { - status = "okay"; - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; - - adv7180@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - remote = <&vin1>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin1ep0>; - }; - }; - }; -}; - -/* composite video input */ -&vin1 { - pinctrl-0 = <&vin1_pins>; - pinctrl-names = "default"; - - status = "okay"; - - port { - vin1ep0: endpoint { - remote-endpoint = <&adv7180>; - bus-width = <8>; - }; - }; -}; - -Device node example for Gen3 platforms --------------------------------------- - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin0csi20: endpoint@0 { - reg = <0>; - remote-endpoint= <&csi20vin0>; - }; - vin0csi21: endpoint@1 { - reg = <1>; - remote-endpoint= <&csi21vin0>; - }; - vin0csi40: endpoint@2 { - reg = <2>; - remote-endpoint= <&csi40vin0>; - }; - }; - }; - }; - - csi20: csi2@fea80000 { - compatible = "renesas,r8a7795-csi2"; - reg = <0 0xfea80000 0 0x10000>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 714>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 714>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - csi20_in: endpoint { - clock-lanes = <0>; - data-lanes = <1>; - remote-endpoint = <&adv7482_txb>; - }; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi20vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi20>; - }; - }; - }; - }; - -[1] video-interfaces.txt common video media interface diff --git a/Documentation/devicetree/bindings/media/renesas,vin.yaml b/Documentation/devicetree/bindings/media/renesas,vin.yaml new file mode 100644 index 000000000000..1ec947b4781f --- /dev/null +++ b/Documentation/devicetree/bindings/media/renesas,vin.yaml @@ -0,0 +1,402 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Copyright (C) 2020 Renesas Electronics Corp. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/renesas,vin.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car Video Input (VIN) + +maintainers: + - Niklas Söderlund <niklas.soderlund@ragnatech.se> + +description: + The R-Car Video Input (VIN) device provides video input capabilities for the + Renesas R-Car family of devices. + + Each VIN instance has a single parallel input that supports RGB and YUV video, + with both external synchronization and BT.656 synchronization for the latter. + Depending on the instance the VIN input is connected to external SoC pins, or + on Gen3 and RZ/G2 platforms to a CSI-2 receiver. + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,vin-r8a7743 # RZ/G1M + - renesas,vin-r8a7744 # RZ/G1N + - renesas,vin-r8a7745 # RZ/G1E + - renesas,vin-r8a77470 # RZ/G1C + - renesas,vin-r8a7790 # R-Car H2 + - renesas,vin-r8a7791 # R-Car M2-W + - renesas,vin-r8a7792 # R-Car V2H + - renesas,vin-r8a7793 # R-Car M2-N + - renesas,vin-r8a7794 # R-Car E2 + - const: renesas,rcar-gen2-vin # Generic R-Car Gen2 or RZ/G1 + + - items: + - enum: + - renesas,vin-r8a774a1 # RZ/G2M + - renesas,vin-r8a774b1 # RZ/G2N + - renesas,vin-r8a774c0 # RZ/G2E + - renesas,vin-r8a7778 # R-Car M1 + - renesas,vin-r8a7779 # R-Car H1 + - renesas,vin-r8a7795 # R-Car H3 + - renesas,vin-r8a7796 # R-Car M3-W + - renesas,vin-r8a77965 # R-Car M3-N + - renesas,vin-r8a77970 # R-Car V3M + - renesas,vin-r8a77980 # R-Car V3H + - renesas,vin-r8a77990 # R-Car E3 + - renesas,vin-r8a77995 # R-Car D3 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + #The per-board settings for Gen2 and RZ/G1 platforms: + port: + type: object + description: + A node containing a parallel input with a single endpoint definitions as + documented in + Documentation/devicetree/bindings/media/video-interfaces.txt + + properties: + endpoint: + type: object + + properties: + hsync-active: + description: + If both HSYNC and VSYNC polarities are not specified, embedded + synchronization is selected. + default: 1 + + vsync-active: + description: + If both HSYNC and VSYNC polarities are not specified, embedded + synchronization is selected. + default: 1 + + field-active-even: true + + bus-width: true + + data-shift: true + + data-enable-active: + description: Polarity of CLKENB signal + default: 1 + + pclk-sample: true + + data-active: true + + remote-endpoint: true + + required: + - remote-endpoint + + additionalProperties: false + + additionalProperties: false + + #The per-board settings for Gen3 and RZ/G2 platforms: + renesas,id: + description: VIN channel number + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + - maximum: 15 + + ports: + type: object + description: + A node containing input nodes with endpoint definitions as documented in + Documentation/devicetree/bindings/media/video-interfaces.txt + + properties: + port@0: + type: object + description: + Input port node, single endpoint describing a parallel input source. + + properties: + reg: + const: 0 + + endpoint: + type: object + + properties: + hsync-active: + description: + If both HSYNC and VSYNC polarities are not specified, embedded + synchronization is selected. + default: 1 + + vsync-active: + description: + If both HSYNC and VSYNC polarities are not specified, embedded + synchronization is selected. + default: 1 + + field-active-even: true + + bus-width: true + + data-shift: true + + data-enable-active: + description: Polarity of CLKENB signal + default: 1 + + pclk-sample: true + + data-active: true + + remote-endpoint: true + + required: + - remote-endpoint + + additionalProperties: false + + required: + - endpoint + + additionalProperties: false + + port@1: + type: object + description: + Input port node, multiple endpoints describing all the R-Car CSI-2 + modules connected the VIN. + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reg: + const: 1 + + endpoint@0: + type: object + description: Endpoint connected to CSI20. + + properties: + reg: + const: 0 + + remote-endpoint: true + + required: + - reg + - remote-endpoint + + additionalProperties: false + + endpoint@1: + type: object + description: Endpoint connected to CSI21. + + properties: + reg: + const: 1 + + remote-endpoint: true + + required: + - reg + - remote-endpoint + + additionalProperties: false + + endpoint@2: + type: object + description: Endpoint connected to CSI40. + + properties: + reg: + const: 2 + + remote-endpoint: true + + required: + - reg + - remote-endpoint + + additionalProperties: false + + endpoint@3: + type: object + description: Endpoint connected to CSI41. + + properties: + reg: + const: 3 + + remote-endpoint: true + + required: + - reg + - remote-endpoint + + additionalProperties: false + + anyOf: + - required: + - endpoint@0 + - required: + - endpoint@1 + - required: + - endpoint@2 + - required: + - endpoint@3 + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - power-domains + - resets + +if: + properties: + compatible: + contains: + enum: + - renesas,vin-r8a7778 + - renesas,vin-r8a7779 + - renesas,rcar-gen2-vin +then: + required: + - port +else: + required: + - renesas,id + - ports + +additionalProperties: false + +examples: + # Device node example for Gen2 platform + - | + #include <dt-bindings/clock/r8a7790-cpg-mssr.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/r8a7790-sysc.h> + + vin1: vin@e6ef1000 { + compatible = "renesas,vin-r8a7790", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 810>; + + port { + vin1ep0: endpoint { + remote-endpoint = <&adv7180>; + bus-width = <8>; + }; + }; + }; + + # Device node example for Gen3 platform with only CSI-2 + - | + #include <dt-bindings/clock/r8a7795-cpg-mssr.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/r8a7795-sysc.h> + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7795"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 811>; + renesas,id = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin0csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin0>; + }; + vin0csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin0>; + }; + }; + }; + }; + + # Device node example for Gen3 platform with CSI-2 and parallel + - | + #include <dt-bindings/clock/r8a77970-cpg-mssr.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/r8a77970-sysc.h> + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a77970"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 809>; + renesas,id = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vin2_in: endpoint { + remote-endpoint = <&adv7612_out>; + hsync-active = <0>; + vsync-active = <0>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin2csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin2>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml index 12516bd89cf9..611bda38d187 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml @@ -97,30 +97,35 @@ examples: #include <dt-bindings/clock/tegra186-clock.h> #include <dt-bindings/interrupt-controller/arm-gic.h> - memory-controller@2c00000 { - compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; - interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; - + bus { #address-cells = <2>; #size-cells = <2>; - ranges = <0x0 0x02c00000 0x02c00000 0x0 0xb0000>; + memory-controller@2c00000 { + compatible = "nvidia,tegra186-mc"; + reg = <0x0 0x02c00000 0x0 0xb0000>; + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; - /* - * Memory clients have access to all 40 bits that the memory - * controller can address. - */ - dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; + /* + * Memory clients have access to all 40 bits that the memory + * controller can address. + */ + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; - external-memory-controller@2c60000 { - compatible = "nvidia,tegra186-emc"; - reg = <0x0 0x02c60000 0x0 0x50000>; - interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&bpmp TEGRA186_CLK_EMC>; - clock-names = "emc"; + external-memory-controller@2c60000 { + compatible = "nvidia,tegra186-emc"; + reg = <0x0 0x02c60000 0x0 0x50000>; + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA186_CLK_EMC>; + clock-names = "emc"; - nvidia,bpmp = <&bpmp>; + nvidia,bpmp = <&bpmp>; + }; }; }; diff --git a/Documentation/devicetree/bindings/mfd/iqs62x.yaml b/Documentation/devicetree/bindings/mfd/iqs62x.yaml new file mode 100644 index 000000000000..541b06d80e73 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/iqs62x.yaml @@ -0,0 +1,179 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/iqs62x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Azoteq IQS620A/621/622/624/625 Multi-Function Sensors + +maintainers: + - Jeff LaBundy <jeff@labundy.com> + +description: | + The Azoteq IQS620A, IQS621, IQS622, IQS624 and IQS625 multi-function sensors + integrate multiple sensing technologies in a single package. + + Link to datasheets: https://www.azoteq.com/ + +properties: + compatible: + enum: + - azoteq,iqs620a + - azoteq,iqs621 + - azoteq,iqs622 + - azoteq,iqs624 + - azoteq,iqs625 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: + Specifies the name of the calibration and configuration file selected by + the driver. If this property is omitted, the name is chosen based on the + device name with ".bin" as the extension (e.g. iqs620a.bin for IQS620A). + + keys: + $ref: ../input/iqs62x-keys.yaml + + pwm: + $ref: ../pwm/iqs620a-pwm.yaml + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + /* + * Dual capacitive buttons with proximity-activated function, unipolar lid + * switch and panel-mounted LED. + */ + #include <dt-bindings/input/input.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + iqs620a@44 { + compatible = "azoteq,iqs620a"; + reg = <0x44>; + interrupt-parent = <&gpio>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + + keys { + compatible = "azoteq,iqs620a-keys"; + + linux,keycodes = <KEY_SELECT>, + <KEY_MENU>, + <KEY_OK>, + <KEY_MENU>; + + hall-switch-south { + linux,code = <SW_LID>; + azoteq,use-prox; + }; + }; + + iqs620a_pwm: pwm { + compatible = "azoteq,iqs620a-pwm"; + #pwm-cells = <2>; + }; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + panel { + pwms = <&iqs620a_pwm 0 1000000>; + max-brightness = <255>; + }; + }; + + - | + /* Single inductive button with bipolar dock/tablet-mode switch. */ + #include <dt-bindings/input/input.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + iqs620a@44 { + compatible = "azoteq,iqs620a"; + reg = <0x44>; + interrupt-parent = <&gpio>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + + firmware-name = "iqs620a_coil.bin"; + + keys { + compatible = "azoteq,iqs620a-keys"; + + linux,keycodes = <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <KEY_MUTE>; + + hall-switch-north { + linux,code = <SW_DOCK>; + }; + + hall-switch-south { + linux,code = <SW_TABLET_MODE>; + }; + }; + }; + }; + + - | + /* Dual capacitive buttons with volume knob. */ + #include <dt-bindings/input/input.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + iqs624@44 { + compatible = "azoteq,iqs624"; + reg = <0x44>; + interrupt-parent = <&gpio>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + + keys { + compatible = "azoteq,iqs624-keys"; + + linux,keycodes = <BTN_0>, + <0>, + <BTN_1>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <KEY_VOLUMEUP>, + <KEY_VOLUMEDOWN>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/mfd/max77650.yaml b/Documentation/devicetree/bindings/mfd/max77650.yaml index 480385789394..b0a0f0d3d9d4 100644 --- a/Documentation/devicetree/bindings/mfd/max77650.yaml +++ b/Documentation/devicetree/bindings/mfd/max77650.yaml @@ -73,6 +73,8 @@ required: - gpio-controller - "#gpio-cells" +additionalProperties: false + examples: - | #include <dt-bindings/interrupt-controller/irq.h> diff --git a/Documentation/devicetree/bindings/mfd/rn5t618.txt b/Documentation/devicetree/bindings/mfd/rn5t618.txt index b74e5e94d1cb..16778ea00dbc 100644 --- a/Documentation/devicetree/bindings/mfd/rn5t618.txt +++ b/Documentation/devicetree/bindings/mfd/rn5t618.txt @@ -15,6 +15,8 @@ Required properties: - reg: the I2C slave address of the device Optional properties: + - interrupts: interrupt mapping for IRQ + See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - system-power-controller: See Documentation/devicetree/bindings/power/power-controller.txt @@ -32,6 +34,8 @@ Example: pmic@32 { compatible = "ricoh,rn5t618"; reg = <0x32>; + interrupt-parent = <&gpio5>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; system-power-controller; regulators { diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml b/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml index 4fbb9e734284..3a6a1a26e2b3 100644 --- a/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml +++ b/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml @@ -41,6 +41,9 @@ properties: "#clock-cells": const: 0 + clock-output-names: + const: bd71828-32k-out + rohm,charger-sense-resistor-ohms: minimum: 10000000 maximum: 50000000 @@ -74,6 +77,8 @@ required: - gpio-controller - "#gpio-cells" +additionalProperties: false + examples: - | #include <dt-bindings/interrupt-controller/irq.h> diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd71837-pmic.txt b/Documentation/devicetree/bindings/mfd/rohm,bd71837-pmic.txt deleted file mode 100644 index f22d74c7a8db..000000000000 --- a/Documentation/devicetree/bindings/mfd/rohm,bd71837-pmic.txt +++ /dev/null @@ -1,90 +0,0 @@ -* ROHM BD71837 and BD71847 Power Management Integrated Circuit bindings - -BD71837MWV and BD71847MWV are programmable Power Management ICs for powering -single-core, dual-core, and quad-core SoCs such as NXP-i.MX 8M. They are -optimized for low BOM cost and compact solution footprint. BD71837MWV -integrates 8 Buck regulators and 7 LDOs. BD71847MWV contains 6 Buck regulators -and 6 LDOs. - -Datasheet for BD71837 is available at: -https://www.rohm.com/datasheet/BD71837MWV/bd71837mwv-e -Datasheet for BD71847 is available at: -https://www.rohm.com/datasheet/BD71847AMWV/bd71847amwv-e - -Required properties: - - compatible : Should be "rohm,bd71837" for bd71837 - "rohm,bd71847" for bd71847. - - reg : I2C slave address. - - interrupt-parent : Phandle to the parent interrupt controller. - - interrupts : The interrupt line the device is connected to. - - clocks : The parent clock connected to PMIC. If this is missing - 32768 KHz clock is assumed. - - #clock-cells : Should be 0. - - regulators: : List of child nodes that specify the regulators. - Please see ../regulator/rohm,bd71837-regulator.txt - -Optional properties: -- clock-output-names : Should contain name for output clock. -- rohm,reset-snvs-powered : Transfer BD718x7 to SNVS state at reset. - -The BD718x7 supports two different HW states as reset target states. States -are called as SNVS and READY. At READY state all the PMIC power outputs go -down and OTP is reload. At the SNVS state all other logic and external -devices apart from the SNVS power domain are shut off. Please refer to NXP -i.MX8 documentation for further information regarding SNVS state. When a -reset is done via SNVS state the PMIC OTP data is not reload. This causes -power outputs that have been under SW control to stay down when reset has -switched power state to SNVS. If reset is done via READY state the power -outputs will be returned to HW control by OTP loading. Thus the reset -target state is set to READY by default. If SNVS state is used the boot -crucial regulators must have the regulator-always-on and regulator-boot-on -properties set in regulator node. - -- rohm,short-press-ms : Short press duration in milliseconds -- rohm,long-press-ms : Long press duration in milliseconds - -Configure the "short press" and "long press" timers for the power button. -Values are rounded to what hardware supports (500ms multiple for short and -1000ms multiple for long). If these properties are not present the existing -configuration (from bootloader or OTP) is not touched. - -Example: - - /* external oscillator node */ - osc: oscillator { - compatible = "fixed-clock"; - #clock-cells = <1>; - clock-frequency = <32768>; - clock-output-names = "osc"; - }; - - pmic: pmic@4b { - compatible = "rohm,bd71837"; - reg = <0x4b>; - interrupt-parent = <&gpio1>; - interrupts = <29 GPIO_ACTIVE_LOW>; - interrupt-names = "irq"; - #clock-cells = <0>; - clocks = <&osc 0>; - clock-output-names = "bd71837-32k-out"; - rohm,reset-snvs-powered; - - regulators { - buck1: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - // [...] - }; - }; - - /* Clock consumer node */ - rtc@0 { - compatible = "company,my-rtc"; - clock-names = "my-clock"; - clocks = <&pmic>; - }; diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd71837-pmic.yaml b/Documentation/devicetree/bindings/mfd/rohm,bd71837-pmic.yaml new file mode 100644 index 000000000000..65018a019e1d --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/rohm,bd71837-pmic.yaml @@ -0,0 +1,238 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/rohm,bd71837-pmic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ROHM BD71837 Power Management Integrated Circuit bindings + +maintainers: + - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> + +description: | + BD71837MWV is programmable Power Management ICs for powering single-core, + dual-core, and quad-core SoCs such as NXP-i.MX 8M. It is optimized for low + BOM cost and compact solution footprint. BD71837MWV integrates 8 Buck + regulators and 7 LDOs. + Datasheet for BD71837 is available at + https://www.rohm.com/products/power-management/power-management-ic-for-system/industrial-consumer-applications/nxp-imx/bd71837amwv-product + +properties: + compatible: + const: rohm,bd71837 + + reg: + description: + I2C slave address. + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + "#clock-cells": + const: 0 + +# The BD718x7 supports two different HW states as reset target states. States +# are called as SNVS and READY. At READY state all the PMIC power outputs go +# down and OTP is reload. At the SNVS state all other logic and external +# devices apart from the SNVS power domain are shut off. Please refer to NXP +# i.MX8 documentation for further information regarding SNVS state. When a +# reset is done via SNVS state the PMIC OTP data is not reload. This causes +# power outputs that have been under SW control to stay down when reset has +# switched power state to SNVS. If reset is done via READY state the power +# outputs will be returned to HW control by OTP loading. Thus the reset +# target state is set to READY by default. If SNVS state is used the boot +# crucial regulators must have the regulator-always-on and regulator-boot-on +# properties set in regulator node. + + rohm,reset-snvs-powered: + description: | + Transfer PMIC to SNVS state at reset + type: boolean + +# Configure the "short press" and "long press" timers for the power button. +# Values are rounded to what hardware supports +# Short-press: +# Shortest being 10ms, next 500ms and then multiple of 500ms up to 7,5s +# Long-press: +# Shortest being 10ms, next 1000ms and then multiple of 1000ms up to 15s +# If these properties are not present the existing configuration (from +# bootloader or OTP) is not touched. + + rohm,short-press-ms: + description: + Short press duration in milliseconds + enum: + - 10 + - 500 + - 1000 + - 1500 + - 2000 + - 2500 + - 3000 + - 3500 + - 4000 + - 4500 + - 5000 + - 5500 + - 6000 + - 6500 + - 7000 + + rohm,long-press-ms: + description: + Long press duration in milliseconds + enum: + - 10 + - 1000 + - 2000 + - 3000 + - 4000 + - 5000 + - 6000 + - 7000 + - 8000 + - 9000 + - 10000 + - 11000 + - 12000 + - 13000 + - 14000 + + regulators: + $ref: ../regulator/rohm,bd71837-regulator.yaml + description: + List of child nodes that specify the regulators. + +required: + - compatible + - reg + - interrupts + - clocks + - "#clock-cells" + - regulators + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/leds/common.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + pmic: pmic@4b { + compatible = "rohm,bd71837"; + reg = <0x4b>; + interrupt-parent = <&gpio1>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <0>; + clocks = <&osc 0>; + rohm,reset-snvs-powered; + rohm,short-press-ms = <10>; + rohm,long-press-ms = <2000>; + + regulators { + buck1: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <900000>; + rohm,dvs-idle-voltage = <850000>; + rohm,dvs-suspend-voltage = <800000>; + }; + buck2: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + buck3: BUCK3 { + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + rohm,dvs-run-voltage = <1000000>; + }; + buck4: BUCK4 { + regulator-name = "buck4"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + rohm,dvs-run-voltage = <1000000>; + }; + buck5: BUCK5 { + regulator-name = "buck5"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + }; + buck6: BUCK6 { + regulator-name = "buck6"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + buck7: BUCK7 { + regulator-name = "buck7"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + }; + buck8: BUCK8 { + regulator-name = "buck8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + }; + + ldo1: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + ldo2: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + }; + ldo3: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + ldo4: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + }; + ldo5: LDO5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + ldo6: LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + }; + ldo7_reg: LDO7 { + regulator-name = "ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd71847-pmic.yaml b/Documentation/devicetree/bindings/mfd/rohm,bd71847-pmic.yaml new file mode 100644 index 000000000000..77bcca2d414f --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/rohm,bd71847-pmic.yaml @@ -0,0 +1,224 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/rohm,bd71847-pmic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ROHM BD71847 and BD71850 Power Management Integrated Circuit bindings + +maintainers: + - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> + +description: | + BD71847AMWV and BD71850MWV are programmable Power Management ICs for powering + single-core, dual-core, and quad-core SoCs such as NXP-i.MX 8M. It is + optimized for low BOM cost and compact solution footprint. BD71847MWV and + BD71850MWV integrate 6 Buck regulators and 6 LDOs. + Datasheets are available at + https://www.rohm.com/products/power-management/power-management-ic-for-system/industrial-consumer-applications/nxp-imx/bd71847amwv-product + https://www.rohm.com/products/power-management/power-management-ic-for-system/industrial-consumer-applications/nxp-imx/bd71850mwv-product + +properties: + compatible: + enum: + - rohm,bd71847 + - rohm,bd71850 + + reg: + description: + I2C slave address. + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + "#clock-cells": + const: 0 + +# The BD71847 abd BD71850 support two different HW states as reset target +# states. States are called as SNVS and READY. At READY state all the PMIC +# power outputs go down and OTP is reload. At the SNVS state all other logic +# and external devices apart from the SNVS power domain are shut off. Please +# refer to NXP i.MX8 documentation for further information regarding SNVS +# state. When a reset is done via SNVS state the PMIC OTP data is not reload. +# This causes power outputs that have been under SW control to stay down when +# reset has switched power state to SNVS. If reset is done via READY state the +# power outputs will be returned to HW control by OTP loading. Thus the reset +# target state is set to READY by default. If SNVS state is used the boot +# crucial regulators must have the regulator-always-on and regulator-boot-on +# properties set in regulator node. + + rohm,reset-snvs-powered: + description: + Transfer PMIC to SNVS state at reset. + type: boolean + +# Configure the "short press" and "long press" timers for the power button. +# Values are rounded to what hardware supports +# Short-press: +# Shortest being 10ms, next 500ms and then multiple of 500ms up to 7,5s +# Long-press: +# Shortest being 10ms, next 1000ms and then multiple of 1000ms up to 15s +# If these properties are not present the existing # configuration (from +# bootloader or OTP) is not touched. + + rohm,short-press-ms: + description: + Short press duration in milliseconds + enum: + - 10 + - 500 + - 1000 + - 1500 + - 2000 + - 2500 + - 3000 + - 3500 + - 4000 + - 4500 + - 5000 + - 5500 + - 6000 + - 6500 + - 7000 + - 7500 + + rohm,long-press-ms: + description: + Long press duration in milliseconds + enum: + - 10 + - 1000 + - 2000 + - 3000 + - 4000 + - 5000 + - 6000 + - 7000 + - 8000 + - 9000 + - 10000 + - 11000 + - 12000 + - 13000 + - 14000 + - 15000 + + regulators: + $ref: ../regulator/rohm,bd71847-regulator.yaml + description: + List of child nodes that specify the regulators. + +required: + - compatible + - reg + - interrupts + - clocks + - "#clock-cells" + - regulators + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/leds/common.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + pmic: pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + interrupt-parent = <&gpio1>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <0>; + clocks = <&osc 0>; + rohm,reset-snvs-powered; + rohm,short-press-ms = <10>; + rohm,long-press-ms = <2000>; + + regulators { + buck1: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <900000>; + rohm,dvs-idle-voltage = <850000>; + rohm,dvs-suspend-voltage = <800000>; + }; + buck2: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + buck3: BUCK3 { + regulator-name = "buck3"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + }; + buck4: BUCK4 { + regulator-name = "buck4"; + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + buck5: BUCK5 { + regulator-name = "buck5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + }; + buck8: BUCK6 { + regulator-name = "buck6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + }; + + ldo1: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + ldo2: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + }; + ldo3: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + ldo4: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + }; + ldo5: LDO5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + ldo6: LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml index 1a4cc5f3fb33..ddf190cb800b 100644 --- a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml @@ -39,6 +39,8 @@ properties: "#size-cells": const: 0 + wakeup-source: true + pwm: type: object @@ -81,6 +83,16 @@ patternProperties: required: - compatible + timer: + type: object + + properties: + compatible: + const: st,stm32-lptimer-timer + + required: + - compatible + required: - "#address-cells" - "#size-cells" @@ -115,6 +127,10 @@ examples: counter { compatible = "st,stm32-lptimer-counter"; }; + + timer { + compatible = "st,stm32-lptimer-timer"; + }; }; ... diff --git a/Documentation/devicetree/bindings/mfd/st,stpmic1.txt b/Documentation/devicetree/bindings/mfd/st,stpmic1.txt deleted file mode 100644 index afd45c089585..000000000000 --- a/Documentation/devicetree/bindings/mfd/st,stpmic1.txt +++ /dev/null @@ -1,61 +0,0 @@ -* STMicroelectronics STPMIC1 Power Management IC - -Required properties: -- compatible: : "st,stpmic1" -- reg: : The I2C slave address for the STPMIC1 chip. -- interrupts: : The interrupt line the device is connected to. -- #interrupt-cells: : Should be 1. -- interrupt-controller: : Marks the device node as an interrupt controller. - Interrupt numbers are defined at - dt-bindings/mfd/st,stpmic1.h. - -STPMIC1 consists in a varied group of sub-devices. -Each sub-device binding is be described in own documentation file. - -Device Description ------- ------------ -st,stpmic1-onkey : Power on key, see ../input/st,stpmic1-onkey.txt -st,stpmic1-regulators : Regulators, see ../regulator/st,stpmic1-regulator.txt -st,stpmic1-wdt : Watchdog, see ../watchdog/st,stpmic1-wdt.txt - -Example: - -#include <dt-bindings/mfd/st,stpmic1.h> - -pmic: pmic@33 { - compatible = "st,stpmic1"; - reg = <0x33>; - interrupt-parent = <&gpioa>; - interrupts = <0 2>; - - interrupt-controller; - #interrupt-cells = <2>; - - onkey { - compatible = "st,stpmic1-onkey"; - interrupts = <IT_PONKEY_F 0>,<IT_PONKEY_R 1>; - interrupt-names = "onkey-falling", "onkey-rising"; - power-off-time-sec = <10>; - }; - - watchdog { - compatible = "st,stpmic1-wdt"; - }; - - regulators { - compatible = "st,stpmic1-regulators"; - - vdd_core: buck1 { - regulator-name = "vdd_core"; - regulator-boot-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1200000>; - }; - vdd: buck3 { - regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-pull-down; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/st,stpmic1.yaml b/Documentation/devicetree/bindings/mfd/st,stpmic1.yaml new file mode 100644 index 000000000000..f88d13d70441 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/st,stpmic1.yaml @@ -0,0 +1,339 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/st,stpmic1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectonics STPMIC1 Power Management IC bindings + +description: STMicroelectronics STPMIC1 Power Management IC + +maintainers: + - pascal Paillet <p.paillet@st.com> + +properties: + compatible: + const: st,stpmic1 + + reg: + const: 0x33 + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 2 + + interrupt-controller: true + + onkey: + type: object + + allOf: + - $ref: ../input/input.yaml + + properties: + compatible: + const: st,stpmic1-onkey + + interrupts: + items: + - description: onkey-falling, happens when onkey is pressed. IT_PONKEY_F of pmic + - description: onkey-rising, happens when onkey is released. IT_PONKEY_R of pmic + + interrupt-names: + items: + - const: onkey-falling + - const: onkey-rising + + st,onkey-clear-cc-flag: + description: onkey is able power on after an over-current shutdown event. + $ref: /schemas/types.yaml#/definitions/flag + + st,onkey-pu-inactive: + description: onkey pull up is not active + $ref: /schemas/types.yaml#/definitions/flag + + power-off-time-sec: + minimum: 1 + maximum: 16 + + required: + - compatible + - interrupts + - interrupt-names + + additionalProperties: false + + watchdog: + type: object + + allOf: + - $ref: ../watchdog/watchdog.yaml + + properties: + compatible: + const: st,stpmic1-wdt + + timeout-sec: true + + required: + - compatible + + additionalProperties: false + + regulators: + type: object + + description: | + Available Regulators in STPMIC1 device are: + - buck1 for Buck BUCK1 + - buck2 for Buck BUCK2 + - buck3 for Buck BUCK3 + - buck4 for Buck BUCK4 + - ldo1 for LDO LDO1 + - ldo2 for LDO LDO2 + - ldo3 for LDO LDO3 + - ldo4 for LDO LDO4 + - ldo5 for LDO LDO5 + - ldo6 for LDO LDO6 + - vref_ddr for LDO Vref DDR + - boost for Buck BOOST + - pwr_sw1 for VBUS_OTG switch + - pwr_sw2 for SW_OUT switch + Switches are fixed voltage regulators with only enable/disable capability. + + properties: + compatible: + const: st,stpmic1-regulators + + ldo3: + type: object + + properties: + interrupts: + maxItems: 1 + + st,mask-reset: + description: mask reset for this regulator, + the regulator configuration is maintained during pmic reset. + $ref: /schemas/types.yaml#/definitions/flag + + regulator-name: true + regulator-boot-on: true + regulator-always-on: true + regulator-min-microvolt: true + regulator-max-microvolt: true + regulator-allow-bypass: true + regulator-over-current-protection: true + + additionalProperties: false + + ldo4: + type: object + + properties: + interrupts: + maxItems: 1 + + st,mask-reset: + description: mask reset for this regulator, + the regulator configuration is maintained during pmic reset. + $ref: /schemas/types.yaml#/definitions/flag + + regulator-name: true + regulator-boot-on: true + regulator-always-on: true + regulator-over-current-protection: true + + additionalProperties: false + + vref_ddr: + type: object + + properties: + interrupts: + maxItems: 1 + + st,mask-reset: + description: mask reset for this regulator, + the regulator configuration is maintained during pmic reset. + $ref: /schemas/types.yaml#/definitions/flag + + regulator-name: true + regulator-boot-on: true + regulator-always-on: true + + additionalProperties: false + + boost: + type: object + + properties: + interrupts: + maxItems: 1 + + st,mask-reset: + description: mask reset for this regulator, + the regulator configuration is maintained during pmic reset. + $ref: /schemas/types.yaml#/definitions/flag + + regulator-name: true + regulator-boot-on: true + regulator-always-on: true + regulator-over-current-protection: true + + additionalProperties: false + + patternProperties: + "^(buck[1-4]|ldo[1-6]|boost|pwr_sw[1-2])-supply$": + description: STPMIC1 voltage regulators supplies + + "^(buck[1-4]|ldo[1-6]|boost|vref_ddr|pwr_sw[1-2])$": + allOf: + - $ref: ../regulator/regulator.yaml + + "^ldo[1-2,5-6]$": + type: object + + properties: + interrupts: + maxItems: 1 + + st,mask-reset: + description: mask reset for this regulator, + the regulator configuration is maintained during pmic reset. + $ref: /schemas/types.yaml#/definitions/flag + + regulator-name: true + regulator-boot-on: true + regulator-always-on: true + regulator-min-microvolt: true + regulator-max-microvolt: true + regulator-over-current-protection: true + regulator-enable-ramp-delay: true + + additionalProperties: false + + "^buck[1-4]$": + type: object + + properties: + interrupts: + maxItems: 1 + + st,mask-reset: + description: mask reset for this regulator, + the regulator configuration is maintained during pmic reset. + $ref: /schemas/types.yaml#/definitions/flag + + regulator-name: true + regulator-boot-on: true + regulator-always-on: true + regulator-min-microvolt: true + regulator-max-microvolt: true + regulator-initial-mode: true + regulator-pull-down: true + regulator-over-current-protection: true + regulator-enable-ramp-delay: true + + additionalProperties: false + + "^pwr_sw[1-2]$": + type: object + + properties: + interrupts: + maxItems: 1 + + regulator-name: true + regulator-boot-on: true + regulator-always-on: true + regulator-over-current-protection: true + regulator-active-discharge: true + + additionalProperties: false + + required: + - compatible + + additionalProperties: false + + additionalProperties: false + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - "#interrupt-cells" + - interrupt-controller + +examples: + - | + #include <dt-bindings/mfd/st,stpmic1.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + pmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupt-parent = <&gpioa>; + interrupts = <0 2>; + + interrupt-controller; + #interrupt-cells = <2>; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = <IT_PONKEY_F 0>,<IT_PONKEY_R 1>; + interrupt-names = "onkey-falling", "onkey-rising"; + power-off-time-sec = <10>; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + }; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo6-supply = <&v3v3>; + + buck1 { + regulator-name = "vdd_core"; + interrupts = <IT_CURLIM_BUCK1 0>; + st,mask-reset; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1200000>; + }; + + buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-pull-down; + }; + + buck4 { + regulator-name = "v3v3"; + interrupts = <IT_CURLIM_BUCK4 0>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-over-current-protection; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml b/Documentation/devicetree/bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml index 0ea21a6f70b4..38ab0499102d 100644 --- a/Documentation/devicetree/bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml +++ b/Documentation/devicetree/bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml @@ -38,6 +38,8 @@ required: - reg - interrupts +additionalProperties: false + examples: - | #include <dt-bindings/interrupt-controller/irq.h> diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml new file mode 100644 index 000000000000..2f45dd0d04db --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence SD/SDIO/eMMC Host Controller (SD4HC) + +maintainers: + - Masahiro Yamada <yamada.masahiro@socionext.com> + - Piotr Sroka <piotrs@cadence.com> + +allOf: + - $ref: mmc-controller.yaml + +properties: + compatible: + items: + - enum: + - socionext,uniphier-sd4hc + - const: cdns,sd4hc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + # PHY DLL input delays: + # They are used to delay the data valid window, and align the window to + # sampling clock. The delay starts from 5ns (for delay parameter equal to 0) + # and it is increased by 2.5ns in each step. + + cdns,phy-input-delay-sd-highspeed: + description: Value of the delay in the input path for SD high-speed timing + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + - maximum: 0x1f + + cdns,phy-input-delay-legacy: + description: Value of the delay in the input path for legacy timing + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + - maximum: 0x1f + + cdns,phy-input-delay-sd-uhs-sdr12: + description: Value of the delay in the input path for SD UHS SDR12 timing + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + - maximum: 0x1f + + cdns,phy-input-delay-sd-uhs-sdr25: + description: Value of the delay in the input path for SD UHS SDR25 timing + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + - maximum: 0x1f + + cdns,phy-input-delay-sd-uhs-sdr50: + description: Value of the delay in the input path for SD UHS SDR50 timing + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + - maximum: 0x1f + + cdns,phy-input-delay-sd-uhs-ddr50: + description: Value of the delay in the input path for SD UHS DDR50 timing + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + - maximum: 0x1f + + cdns,phy-input-delay-mmc-highspeed: + description: Value of the delay in the input path for MMC high-speed timing + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + - maximum: 0x1f + + cdns,phy-input-delay-mmc-ddr: + description: Value of the delay in the input path for eMMC high-speed DDR timing + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + - maximum: 0x1f + + # PHY DLL clock delays: + # Each delay property represents the fraction of the clock period. + # The approximate delay value will be + # (<delay property value>/128)*sdmclk_clock_period. + + cdns,phy-dll-delay-sdclk: + description: | + Value of the delay introduced on the sdclk output for all modes except + HS200, HS400 and HS400_ES. + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + - maximum: 0x7f + + cdns,phy-dll-delay-sdclk-hsmmc: + description: | + Value of the delay introduced on the sdclk output for HS200, HS400 and + HS400_ES speed modes. + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + - maximum: 0x7f + + cdns,phy-dll-delay-strobe: + description: | + Value of the delay introduced on the dat_strobe input used in + HS400 / HS400_ES speed modes. + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + - maximum: 0x7f + +required: + - compatible + - reg + - interrupts + - clocks + +examples: + - | + emmc: mmc@5a000000 { + compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; + reg = <0x5a000000 0x400>; + interrupts = <0 78 4>; + clocks = <&clk 4>; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cdns,phy-dll-delay-sdclk = <0>; + }; diff --git a/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt b/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt deleted file mode 100644 index fa423c277853..000000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt +++ /dev/null @@ -1,80 +0,0 @@ -* Cadence SD/SDIO/eMMC Host Controller - -Required properties: -- compatible: should be one of the following: - "cdns,sd4hc" - default of the IP - "socionext,uniphier-sd4hc" - for Socionext UniPhier SoCs -- reg: offset and length of the register set for the device. -- interrupts: a single interrupt specifier. -- clocks: phandle to the input clock. - -Optional properties: -For eMMC configuration, supported speed modes are not indicated by the SDHCI -Capabilities Register. Instead, the following properties should be specified -if supported. See mmc.txt for details. -- mmc-ddr-1_8v -- mmc-ddr-1_2v -- mmc-hs200-1_8v -- mmc-hs200-1_2v -- mmc-hs400-1_8v -- mmc-hs400-1_2v - -Some PHY delays can be configured by following properties. -PHY DLL input delays: -They are used to delay the data valid window, and align the window -to sampling clock. The delay starts from 5ns (for delay parameter equal to 0) -and it is increased by 2.5ns in each step. -- cdns,phy-input-delay-sd-highspeed: - Value of the delay in the input path for SD high-speed timing - Valid range = [0:0x1F]. -- cdns,phy-input-delay-legacy: - Value of the delay in the input path for legacy timing - Valid range = [0:0x1F]. -- cdns,phy-input-delay-sd-uhs-sdr12: - Value of the delay in the input path for SD UHS SDR12 timing - Valid range = [0:0x1F]. -- cdns,phy-input-delay-sd-uhs-sdr25: - Value of the delay in the input path for SD UHS SDR25 timing - Valid range = [0:0x1F]. -- cdns,phy-input-delay-sd-uhs-sdr50: - Value of the delay in the input path for SD UHS SDR50 timing - Valid range = [0:0x1F]. -- cdns,phy-input-delay-sd-uhs-ddr50: - Value of the delay in the input path for SD UHS DDR50 timing - Valid range = [0:0x1F]. -- cdns,phy-input-delay-mmc-highspeed: - Value of the delay in the input path for MMC high-speed timing - Valid range = [0:0x1F]. -- cdns,phy-input-delay-mmc-ddr: - Value of the delay in the input path for eMMC high-speed DDR timing - Valid range = [0:0x1F]. - -PHY DLL clock delays: -Each delay property represents the fraction of the clock period. -The approximate delay value will be -(<delay property value>/128)*sdmclk_clock_period. -- cdns,phy-dll-delay-sdclk: - Value of the delay introduced on the sdclk output - for all modes except HS200, HS400 and HS400_ES. - Valid range = [0:0x7F]. -- cdns,phy-dll-delay-sdclk-hsmmc: - Value of the delay introduced on the sdclk output - for HS200, HS400 and HS400_ES speed modes. - Valid range = [0:0x7F]. -- cdns,phy-dll-delay-strobe: - Value of the delay introduced on the dat_strobe input - used in HS400 / HS400_ES speed modes. - Valid range = [0:0x7F]. - -Example: - emmc: sdhci@5a000000 { - compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; - reg = <0x5a000000 0x400>; - interrupts = <0 78 4>; - clocks = <&clk 4>; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - cdns,phy-dll-delay-sdclk = <0>; - }; diff --git a/Documentation/devicetree/bindings/mmc/socionext,uniphier-sd.yaml b/Documentation/devicetree/bindings/mmc/socionext,uniphier-sd.yaml new file mode 100644 index 000000000000..cdfac9b4411b --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/socionext,uniphier-sd.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/socionext,uniphier-sd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier SD/SDIO/eMMC controller + +maintainers: + - Masahiro Yamada <yamada.masahiro@socionext.com> + +properties: + compatible: + description: version 2.91, 3.1, 3.1.1, respectively + enum: + - socionext,uniphier-sd-v2.91 + - socionext,uniphier-sd-v3.1 + - socionext,uniphier-sd-v3.1.1 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + reset-names: + description: | + There are three reset signals at maximum + host: mandatory for all variants + bridge: exist only for version 2.91 + hw: optional. exist if eMMC hw reset line is available + oneOf: + - const: host + - items: + - const: host + - const: bridge + - items: + - const: host + - const: hw + - items: + - const: host + - const: bridge + - const: hw + + resets: + minItems: 1 + maxItems: 3 + +allOf: + - $ref: mmc-controller.yaml + + - if: + properties: + compatible: + contains: + const: socionext,uniphier-sd-v2.91 + then: + properties: + reset-names: + contains: + const: bridge + else: + properties: + reset-names: + not: + contains: + const: bridge + +required: + - compatible + - reg + - interrupts + - clocks + - reset-names + - resets + +examples: + - | + sd: mmc@5a400000 { + compatible = "socionext,uniphier-sd-v2.91"; + reg = <0x5a400000 0x200>; + interrupts = <0 76 4>; + pinctrl-names = "default", "uhs"; + pinctrl-0 = <&pinctrl_sd>; + pinctrl-1 = <&pinctrl_sd_uhs>; + clocks = <&mio_clk 0>; + reset-names = "host", "bridge"; + resets = <&mio_rst 0>, <&mio_rst 3>; + dma-names = "rx-tx"; + dmas = <&dmac 4>; + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + }; diff --git a/Documentation/devicetree/bindings/mmc/uniphier-sd.txt b/Documentation/devicetree/bindings/mmc/uniphier-sd.txt deleted file mode 100644 index e1d658755722..000000000000 --- a/Documentation/devicetree/bindings/mmc/uniphier-sd.txt +++ /dev/null @@ -1,55 +0,0 @@ -UniPhier SD/eMMC controller - -Required properties: -- compatible: should be one of the following: - "socionext,uniphier-sd-v2.91" - IP version 2.91 - "socionext,uniphier-sd-v3.1" - IP version 3.1 - "socionext,uniphier-sd-v3.1.1" - IP version 3.1.1 -- reg: offset and length of the register set for the device. -- interrupts: a single interrupt specifier. -- clocks: a single clock specifier of the controller clock. -- reset-names: should contain the following: - "host" - mandatory for all versions - "bridge" - should exist only for "socionext,uniphier-sd-v2.91" - "hw" - should exist if eMMC hw reset line is available -- resets: a list of reset specifiers, corresponding to the reset-names - -Optional properties: -- pinctrl-names: if present, should contain the following: - "default" - should exist for all instances - "uhs" - should exist for SD instance with UHS support -- pinctrl-0: pin control state for the default mode -- pinctrl-1: pin control state for the UHS mode -- dma-names: should be "rx-tx" if present. - This property can exist only for "socionext,uniphier-sd-v2.91". -- dmas: a single DMA channel specifier - This property can exist only for "socionext,uniphier-sd-v2.91". -- bus-width: see mmc.txt -- cap-sd-highspeed: see mmc.txt -- cap-mmc-highspeed: see mmc.txt -- sd-uhs-sdr12: see mmc.txt -- sd-uhs-sdr25: see mmc.txt -- sd-uhs-sdr50: see mmc.txt -- cap-mmc-hw-reset: should exist if reset-names contains "hw". see mmc.txt -- non-removable: see mmc.txt - -Example: - - sd: sdhc@5a400000 { - compatible = "socionext,uniphier-sd-v2.91"; - reg = <0x5a400000 0x200>; - interrupts = <0 76 4>; - pinctrl-names = "default", "uhs"; - pinctrl-0 = <&pinctrl_sd>; - pinctrl-1 = <&pinctrl_sd_uhs>; - clocks = <&mio_clk 0>; - reset-names = "host", "bridge"; - resets = <&mio_rst 0>, <&mio_rst 3>; - dma-names = "rx-tx"; - dmas = <&dmac 4>; - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - }; diff --git a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt index 82156dc8f304..05651a654c66 100644 --- a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt +++ b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt @@ -35,11 +35,11 @@ Required properties: (optional) NAND flash cache range (if at non-standard offset) - reg-names : a list of the names corresponding to the previous register ranges. Should contain "nand" and (optionally) - "flash-dma" and/or "nand-cache". -- interrupts : The NAND CTLRDY interrupt and (if Flash DMA is available) - FLASH_DMA_DONE -- interrupt-names : May be "nand_ctlrdy" or "flash_dma_done", if broken out as - individual interrupts. + "flash-dma" or "flash-edu" and/or "nand-cache". +- interrupts : The NAND CTLRDY interrupt, (if Flash DMA is available) + FLASH_DMA_DONE and if EDU is avaialble and used FLASH_EDU_DONE +- interrupt-names : May be "nand_ctlrdy" or "flash_dma_done" or "flash_edu_done", + if broken out as individual interrupts. May be "nand", if the SoC has the individual NAND interrupts multiplexed behind another custom piece of hardware diff --git a/Documentation/devicetree/bindings/mtd/denali,nand.yaml b/Documentation/devicetree/bindings/mtd/denali,nand.yaml new file mode 100644 index 000000000000..46e6b6726bc0 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/denali,nand.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/denali,nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Denali NAND controller + +maintainers: + - Masahiro Yamada <yamada.masahiro@socionext.com> + +properties: + compatible: + enum: + - altr,socfpga-denali-nand + - socionext,uniphier-denali-nand-v5a + - socionext,uniphier-denali-nand-v5b + + reg-names: + description: | + There are two register regions: + nand_data: host data/command interface + denali_reg: register interface + items: + - const: nand_data + - const: denali_reg + + reg: + minItems: 2 + maxItems: 2 + + interrupts: + maxItems: 1 + + clock-names: + description: | + There are three clocks: + nand: controller core clock + nand_x: bus interface clock + ecc: ECC circuit clock + items: + - const: nand + - const: nand_x + - const: ecc + + clocks: + minItems: 3 + maxItems: 3 + + reset-names: + description: | + There are two optional resets: + nand: controller core reset + reg: register reset + oneOf: + - items: + - const: nand + - const: reg + - const: nand + - const: reg + + resets: + minItems: 1 + maxItems: 2 + +allOf: + - $ref: nand-controller.yaml + + - if: + properties: + compatible: + contains: + const: altr,socfpga-denali-nand + then: + patternProperties: + "^nand@[a-f0-9]$": + type: object + properties: + nand-ecc-strength: + enum: + - 8 + - 15 + nand-ecc-step-size: + enum: + - 512 + + - if: + properties: + compatible: + contains: + const: socionext,uniphier-denali-nand-v5a + then: + patternProperties: + "^nand@[a-f0-9]$": + type: object + properties: + nand-ecc-strength: + enum: + - 8 + - 16 + - 24 + nand-ecc-step-size: + enum: + - 1024 + + - if: + properties: + compatible: + contains: + const: socionext,uniphier-denali-nand-v5b + then: + patternProperties: + "^nand@[a-f0-9]$": + type: object + properties: + nand-ecc-strength: + enum: + - 8 + - 16 + nand-ecc-step-size: + enum: + - 1024 + +required: + - compatible + - reg + - interrupts + - clock-names + - clocks + +examples: + - | + nand-controller@ff900000 { + compatible = "altr,socfpga-denali-nand"; + reg-names = "nand_data", "denali_reg"; + reg = <0xff900000 0x20>, <0xffb80000 0x1000>; + interrupts = <0 144 4>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; + reset-names = "nand", "reg"; + resets = <&nand_rst>, <&nand_reg_rst>; + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/mtd/denali-nand.txt b/Documentation/devicetree/bindings/mtd/denali-nand.txt deleted file mode 100644 index 98916a84bbf6..000000000000 --- a/Documentation/devicetree/bindings/mtd/denali-nand.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Denali NAND controller - -Required properties: - - compatible : should be one of the following: - "altr,socfpga-denali-nand" - for Altera SOCFPGA - "socionext,uniphier-denali-nand-v5a" - for Socionext UniPhier (v5a) - "socionext,uniphier-denali-nand-v5b" - for Socionext UniPhier (v5b) - - reg : should contain registers location and length for data and reg. - - reg-names: Should contain the reg names "nand_data" and "denali_reg" - - #address-cells: should be 1. The cell encodes the chip select connection. - - #size-cells : should be 0. - - interrupts : The interrupt number. - - clocks: should contain phandle of the controller core clock, the bus - interface clock, and the ECC circuit clock. - - clock-names: should contain "nand", "nand_x", "ecc" - -Optional properties: - - resets: may contain phandles to the controller core reset, the register - reset - - reset-names: may contain "nand", "reg" - -Sub-nodes: - Sub-nodes represent available NAND chips. - - Required properties: - - reg: should contain the bank ID of the controller to which each chip - select is connected. - - Optional properties: - - nand-ecc-step-size: see nand-controller.yaml for details. - If present, the value must be - 512 for "altr,socfpga-denali-nand" - 1024 for "socionext,uniphier-denali-nand-v5a" - 1024 for "socionext,uniphier-denali-nand-v5b" - - nand-ecc-strength: see nand-controller.yaml for details. Valid values are: - 8, 15 for "altr,socfpga-denali-nand" - 8, 16, 24 for "socionext,uniphier-denali-nand-v5a" - 8, 16 for "socionext,uniphier-denali-nand-v5b" - - nand-ecc-maximize: see nand-controller.yaml for details - -The chip nodes may optionally contain sub-nodes describing partitions of the -address space. See partition.txt for more detail. - -Examples: - -nand: nand@ff900000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "altr,socfpga-denali-nand"; - reg = <0xff900000 0x20>, <0xffb80000 0x1000>; - reg-names = "nand_data", "denali_reg"; - clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; - clock-names = "nand", "nand_x", "ecc"; - resets = <&nand_rst>, <&nand_reg_rst>; - reset-names = "nand", "reg"; - interrupts = <0 144 4>; - - nand@0 { - reg = <0>; - } -}; diff --git a/Documentation/devicetree/bindings/mtd/nand-macronix.txt b/Documentation/devicetree/bindings/mtd/nand-macronix.txt new file mode 100644 index 000000000000..ffab28a2c4d1 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/nand-macronix.txt @@ -0,0 +1,27 @@ +Macronix NANDs Device Tree Bindings +----------------------------------- + +Macronix NANDs support randomizer operation for scrambling user data, +which can be enabled with a SET_FEATURE. The penalty when using the +randomizer are subpage accesses prohibited and more time period needed +for program operation, i.e., tPROG 300us to 340us (randomizer enabled). +Enabling the randomizer is a one time persistent and non reversible +operation. + +For more high-reliability concern, if subpage write is not available +with hardware ECC and not enabled at UBI level, then enabling the +randomizer is recommended by default by adding a new specific property +in children nodes. + +Required NAND chip properties in children mode: +- randomizer enable: should be "mxic,enable-randomizer-otp" + +Example: + + nand: nand-controller@unit-address { + + nand@0 { + reg = <0>; + mxic,enable-randomizer-otp; + }; + }; diff --git a/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt b/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt index dd258674633c..a7d57ba5f2ac 100644 --- a/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt +++ b/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt @@ -20,7 +20,7 @@ Required properties: Optional properties: - - max-speed: see Documentation/devicetree/bindings/serial/slave-device.txt + - max-speed: see Documentation/devicetree/bindings/serial/serial.yaml - shutdown-gpios: GPIO specifier, used to enable the BT module - device-wakeup-gpios: GPIO specifier, used to wakeup the controller - host-wakeup-gpios: GPIO specifier, used to wakeup the host processor. diff --git a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml new file mode 100644 index 000000000000..cccf8202c8f7 --- /dev/null +++ b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/can/bosch,m_can.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bosch MCAN controller Bindings + +description: Bosch MCAN controller for CAN bus + +maintainers: + - Sriram Dash <sriram.dash@samsung.com> + +properties: + compatible: + const: bosch,m_can + + reg: + items: + - description: M_CAN registers map + - description: message RAM + + reg-names: + items: + - const: m_can + - const: message_ram + + interrupts: + items: + - description: interrupt line0 + - description: interrupt line1 + minItems: 1 + maxItems: 2 + + interrupt-names: + items: + - const: int0 + - const: int1 + minItems: 1 + maxItems: 2 + + clocks: + items: + - description: peripheral clock + - description: bus clock + + clock-names: + items: + - const: hclk + - const: cclk + + bosch,mram-cfg: + description: | + Message RAM configuration data. + Multiple M_CAN instances can share the same Message RAM + and each element(e.g Rx FIFO or Tx Buffer and etc) number + in Message RAM is also configurable, so this property is + telling driver how the shared or private Message RAM are + used by this M_CAN controller. + + The format should be as follows: + <offset sidf_elems xidf_elems rxf0_elems rxf1_elems rxb_elems txe_elems txb_elems> + The 'offset' is an address offset of the Message RAM where + the following elements start from. This is usually set to + 0x0 if you're using a private Message RAM. The remain cells + are used to specify how many elements are used for each FIFO/Buffer. + + M_CAN includes the following elements according to user manual: + 11-bit Filter 0-128 elements / 0-128 words + 29-bit Filter 0-64 elements / 0-128 words + Rx FIFO 0 0-64 elements / 0-1152 words + Rx FIFO 1 0-64 elements / 0-1152 words + Rx Buffers 0-64 elements / 0-1152 words + Tx Event FIFO 0-32 elements / 0-64 words + Tx Buffers 0-32 elements / 0-576 words + + Please refer to 2.4.1 Message RAM Configuration in Bosch + M_CAN user manual for details. + allOf: + - $ref: /schemas/types.yaml#/definitions/int32-array + - items: + items: + - description: The 'offset' is an address offset of the Message RAM + where the following elements start from. This is usually + set to 0x0 if you're using a private Message RAM. + default: 0 + - description: 11-bit Filter 0-128 elements / 0-128 words + minimum: 0 + maximum: 128 + - description: 29-bit Filter 0-64 elements / 0-128 words + minimum: 0 + maximum: 64 + - description: Rx FIFO 0 0-64 elements / 0-1152 words + minimum: 0 + maximum: 64 + - description: Rx FIFO 1 0-64 elements / 0-1152 words + minimum: 0 + maximum: 64 + - description: Rx Buffers 0-64 elements / 0-1152 words + minimum: 0 + maximum: 64 + - description: Tx Event FIFO 0-32 elements / 0-64 words + minimum: 0 + maximum: 32 + - description: Tx Buffers 0-32 elements / 0-576 words + minimum: 0 + maximum: 32 + maxItems: 1 + + can-transceiver: + $ref: can-transceiver.yaml# + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - clocks + - clock-names + - bosch,mram-cfg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx6sx-clock.h> + can@20e8000 { + compatible = "bosch,m_can"; + reg = <0x020e8000 0x4000>, <0x02298000 0x4000>; + reg-names = "m_can", "message_ram"; + interrupts = <0 114 0x04>, <0 114 0x04>; + interrupt-names = "int0", "int1"; + clocks = <&clks IMX6SX_CLK_CANFD>, + <&clks IMX6SX_CLK_CANFD>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>; + + can-transceiver { + max-bitrate = <5000000>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/net/can/can-transceiver.txt b/Documentation/devicetree/bindings/net/can/can-transceiver.txt deleted file mode 100644 index 0011f53ff159..000000000000 --- a/Documentation/devicetree/bindings/net/can/can-transceiver.txt +++ /dev/null @@ -1,24 +0,0 @@ -Generic CAN transceiver Device Tree binding ------------------------------- - -CAN transceiver typically limits the max speed in standard CAN and CAN FD -modes. Typically these limitations are static and the transceivers themselves -provide no way to detect this limitation at runtime. For this situation, -the "can-transceiver" node can be used. - -Required Properties: - max-bitrate: a positive non 0 value that determines the max - speed that CAN/CAN-FD can run. Any other value - will be ignored. - -Examples: - -Based on Texas Instrument's TCAN1042HGV CAN Transceiver - -m_can0 { - .... - can-transceiver { - max-bitrate = <5000000>; - }; - ... -}; diff --git a/Documentation/devicetree/bindings/net/can/can-transceiver.yaml b/Documentation/devicetree/bindings/net/can/can-transceiver.yaml new file mode 100644 index 000000000000..6396977d29e5 --- /dev/null +++ b/Documentation/devicetree/bindings/net/can/can-transceiver.yaml @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/can/can-transceiver.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CAN transceiver Bindings + +description: CAN transceiver generic properties bindings + +maintainers: + - Rob Herring <robh@kernel.org> + +properties: + max-bitrate: + $ref: /schemas/types.yaml#/definitions/uint32 + description: a positive non 0 value that determines the max speed that CAN/CAN-FD can run. + minimum: 1 diff --git a/Documentation/devicetree/bindings/net/can/m_can.txt b/Documentation/devicetree/bindings/net/can/m_can.txt deleted file mode 100644 index ed614383af9c..000000000000 --- a/Documentation/devicetree/bindings/net/can/m_can.txt +++ /dev/null @@ -1,75 +0,0 @@ -Bosch MCAN controller Device Tree Bindings -------------------------------------------------- - -Required properties: -- compatible : Should be "bosch,m_can" for M_CAN controllers -- reg : physical base address and size of the M_CAN - registers map and Message RAM -- reg-names : Should be "m_can" and "message_ram" -- interrupts : Should be the interrupt number of M_CAN interrupt - line 0 and line 1, could be same if sharing - the same interrupt. -- interrupt-names : Should contain "int0" and "int1" -- clocks : Clocks used by controller, should be host clock - and CAN clock. -- clock-names : Should contain "hclk" and "cclk" -- pinctrl-<n> : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt -- pinctrl-names : Names corresponding to the numbered pinctrl states -- bosch,mram-cfg : Message RAM configuration data. - Multiple M_CAN instances can share the same Message - RAM and each element(e.g Rx FIFO or Tx Buffer and etc) - number in Message RAM is also configurable, - so this property is telling driver how the shared or - private Message RAM are used by this M_CAN controller. - - The format should be as follows: - <offset sidf_elems xidf_elems rxf0_elems rxf1_elems - rxb_elems txe_elems txb_elems> - The 'offset' is an address offset of the Message RAM - where the following elements start from. This is - usually set to 0x0 if you're using a private Message - RAM. The remain cells are used to specify how many - elements are used for each FIFO/Buffer. - - M_CAN includes the following elements according to user manual: - 11-bit Filter 0-128 elements / 0-128 words - 29-bit Filter 0-64 elements / 0-128 words - Rx FIFO 0 0-64 elements / 0-1152 words - Rx FIFO 1 0-64 elements / 0-1152 words - Rx Buffers 0-64 elements / 0-1152 words - Tx Event FIFO 0-32 elements / 0-64 words - Tx Buffers 0-32 elements / 0-576 words - - Please refer to 2.4.1 Message RAM Configuration in - Bosch M_CAN user manual for details. - -Optional Subnode: -- can-transceiver : Can-transceiver subnode describing maximum speed - that can be used for CAN/CAN-FD modes. See - Documentation/devicetree/bindings/net/can/can-transceiver.txt - for details. -Example: -SoC dtsi: -m_can1: can@20e8000 { - compatible = "bosch,m_can"; - reg = <0x020e8000 0x4000>, <0x02298000 0x4000>; - reg-names = "m_can", "message_ram"; - interrupts = <0 114 0x04>, - <0 114 0x04>; - interrupt-names = "int0", "int1"; - clocks = <&clks IMX6SX_CLK_CANFD>, - <&clks IMX6SX_CLK_CANFD>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>; -}; - -Board dts: -&m_can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_m_can1>; - status = "enabled"; - - can-transceiver { - max-bitrate = <5000000>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/can/tcan4x5x.txt b/Documentation/devicetree/bindings/net/can/tcan4x5x.txt index 6bdcc3f84bd3..3613c2c8f75d 100644 --- a/Documentation/devicetree/bindings/net/can/tcan4x5x.txt +++ b/Documentation/devicetree/bindings/net/can/tcan4x5x.txt @@ -14,7 +14,7 @@ Required properties: the interrupt. - interrupts: interrupt specification for data-ready. -See Documentation/devicetree/bindings/net/can/m_can.txt for additional +See Documentation/devicetree/bindings/net/can/bosch,m_can.yaml for additional required property details. Optional properties: diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml index 8927941c74bb..5aa141ccc113 100644 --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml @@ -45,6 +45,9 @@ properties: bits of a vendor specific ID. - items: - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" + - const: ethernet-phy-ieee802.3-c22 + - items: + - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" - const: ethernet-phy-ieee802.3-c45 reg: diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt index 5b88fae0307d..ff8b0f211aa1 100644 --- a/Documentation/devicetree/bindings/net/fsl-fec.txt +++ b/Documentation/devicetree/bindings/net/fsl-fec.txt @@ -22,6 +22,8 @@ Optional properties: - fsl,err006687-workaround-present: If present indicates that the system has the hardware workaround for ERR006687 applied and does not need a software workaround. +- gpr: phandle of SoC general purpose register mode. Required for wake on LAN + on some SoCs -interrupt-names: names of the interrupts listed in interrupts property in the same order. The defaults if not specified are __Number of interrupts__ __Default__ diff --git a/Documentation/devicetree/bindings/net/marvell,mvusb.yaml b/Documentation/devicetree/bindings/net/marvell,mvusb.yaml index 9458f6659be1..68573762294b 100644 --- a/Documentation/devicetree/bindings/net/marvell,mvusb.yaml +++ b/Documentation/devicetree/bindings/net/marvell,mvusb.yaml @@ -38,28 +38,27 @@ required: examples: - | /* USB host controller */ - &usb1 { - mvusb: mdio@1 { + usb { + #address-cells = <1>; + #size-cells = <0>; + + mdio@1 { compatible = "usb1286,1fa4"; reg = <1>; #address-cells = <1>; #size-cells = <0>; - }; - }; - /* MV88E6390X devboard */ - &mvusb { - switch@0 { - compatible = "marvell,mv88e6190"; - status = "ok"; - reg = <0x0>; + switch@0 { + compatible = "marvell,mv88e6190"; + reg = <0x0>; - ports { - /* Port definitions */ - }; + ports { + /* Port definitions */ + }; - mdio { - /* PHY definitions */ + mdio { + /* PHY definitions */ + }; }; }; }; diff --git a/Documentation/devicetree/bindings/net/mediatek-bluetooth.txt b/Documentation/devicetree/bindings/net/mediatek-bluetooth.txt index 112011c51d5e..219bcbd0d344 100644 --- a/Documentation/devicetree/bindings/net/mediatek-bluetooth.txt +++ b/Documentation/devicetree/bindings/net/mediatek-bluetooth.txt @@ -42,7 +42,7 @@ child node of the serial node with UART. Please refer to the following documents for generic properties: - Documentation/devicetree/bindings/serial/slave-device.txt + Documentation/devicetree/bindings/serial/serial.yaml Required properties: diff --git a/Documentation/devicetree/bindings/net/qca,qca7000.txt b/Documentation/devicetree/bindings/net/qca,qca7000.txt index 21c36e524993..8f5ae0b84eec 100644 --- a/Documentation/devicetree/bindings/net/qca,qca7000.txt +++ b/Documentation/devicetree/bindings/net/qca,qca7000.txt @@ -68,7 +68,7 @@ Required properties: Optional properties: - local-mac-address : see ./ethernet.txt - current-speed : current baud rate of QCA7000 which defaults to 115200 - if absent, see also ../serial/slave-device.txt + if absent, see also ../serial/serial.yaml UART Example: diff --git a/Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml b/Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml index b9f90081046f..67df3fe861ee 100644 --- a/Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml @@ -48,6 +48,7 @@ examples: switch@10 { compatible = "qca,qca8337"; + reg = <0x10>; /* ... */ }; }; diff --git a/Documentation/devicetree/bindings/net/qualcomm-bluetooth.txt b/Documentation/devicetree/bindings/net/qualcomm-bluetooth.txt index beca6466d59a..d2202791c1d4 100644 --- a/Documentation/devicetree/bindings/net/qualcomm-bluetooth.txt +++ b/Documentation/devicetree/bindings/net/qualcomm-bluetooth.txt @@ -29,7 +29,7 @@ Required properties for compatible string qcom,wcn399x-bt: Optional properties for compatible string qcom,wcn399x-bt: - - max-speed: see Documentation/devicetree/bindings/serial/slave-device.txt + - max-speed: see Documentation/devicetree/bindings/serial/serial.yaml - firmware-name: specify the name of nvm firmware to load - clocks: clock provided to the controller diff --git a/Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml b/Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml index ac8c76369a86..976f139bb66e 100644 --- a/Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml +++ b/Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml @@ -37,6 +37,12 @@ properties: description: The physical base address and size of full the CPSW module IO range + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + ranges: true clocks: @@ -111,13 +117,6 @@ properties: - reg - phys - mdio: - type: object - allOf: - - $ref: "ti,davinci-mdio.yaml#" - description: - CPSW MDIO bus. - cpts: type: object description: @@ -148,6 +147,15 @@ properties: - clocks - clock-names +patternProperties: + "^mdio@": + type: object + allOf: + - $ref: "ti,davinci-mdio.yaml#" + description: + CPSW MDIO bus. + + required: - compatible - reg @@ -159,6 +167,8 @@ required: - '#address-cells' - '#size-cells' +additionalProperties: false + examples: - | #include <dt-bindings/interrupt-controller/irq.h> @@ -174,7 +184,6 @@ examples: #address-cells = <1>; #size-cells = <1>; syscon = <&scm_conf>; - inctrl-names = "default", "sleep"; interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, diff --git a/Documentation/devicetree/bindings/net/ti-bluetooth.txt b/Documentation/devicetree/bindings/net/ti-bluetooth.txt index 6d03ff8c7068..f48c17b38f58 100644 --- a/Documentation/devicetree/bindings/net/ti-bluetooth.txt +++ b/Documentation/devicetree/bindings/net/ti-bluetooth.txt @@ -15,8 +15,7 @@ standard BT HCI protocol with additional channels for the other functions. TI WiLink devices also have a separate WiFi interface as described in wireless/ti,wlcore.txt. -This bindings follows the UART slave device binding in -../serial/slave-device.txt. +This bindings follows the UART slave device binding in ../serial/serial.yaml. Required properties: - compatible: should be one of the following: diff --git a/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml new file mode 100644 index 000000000000..1485d3fbabfd --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/ingenic,jz4780-efuse.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic JZ EFUSE driver bindings + +maintainers: + - PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com> + +allOf: + - $ref: "nvmem.yaml#" + +properties: + compatible: + enum: + - ingenic,jz4780-efuse + + reg: + maxItems: 1 + + clocks: + # Handle for the ahb for the efuse. + maxItems: 1 + +required: + - compatible + - reg + - clocks + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/jz4780-cgu.h> + + efuse@134100d0 { + compatible = "ingenic,jz4780-efuse"; + reg = <0x134100d0 0x2c>; + + clocks = <&cgu JZ4780_CLK_AHB2>; + }; + +... diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt index 84fdc422792e..b6acbe694ffb 100644 --- a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt @@ -18,7 +18,6 @@ Required properties: - reg-names: Must be - "elbi" External local bus interface registers - "cfg" Meson specific registers - - "phy" Meson PCIE PHY registers for AXG SoC Family - "config" PCIe configuration space - reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. - clocks: Must contain an entry for each entry in clock-names. @@ -26,13 +25,13 @@ Required properties: - "pclk" PCIe GEN 100M PLL clock - "port" PCIe_x(A or B) RC clock gate - "general" PCIe Phy clock - - "mipi" PCIe_x(A or B) 100M ref clock gate for AXG SoC Family - resets: phandle to the reset lines. -- reset-names: must contain "phy" "port" and "apb" - - "phy" Share PHY reset for AXG SoC Family +- reset-names: must contain "port" and "apb" - "port" Port A or B reset - "apb" Share APB reset -- phys: should contain a phandle to the shared phy for G12A SoC Family +- phys: should contain a phandle to the PCIE phy +- phy-names: must contain "pcie" + - device_type: should be "pci". As specified in designware-pcie.txt @@ -43,9 +42,8 @@ Example configuration: compatible = "amlogic,axg-pcie", "snps,dw-pcie"; reg = <0x0 0xf9800000 0x0 0x400000 0x0 0xff646000 0x0 0x2000 - 0x0 0xff644000 0x0 0x2000 0x0 0xf9f00000 0x0 0x100000>; - reg-names = "elbi", "cfg", "phy", "config"; + reg-names = "elbi", "cfg", "config"; reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>; #interrupt-cells = <1>; @@ -58,17 +56,15 @@ Example configuration: ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>; clocks = <&clkc CLKID_USB - &clkc CLKID_MIPI_ENABLE &clkc CLKID_PCIE_A &clkc CLKID_PCIE_CML_EN0>; clock-names = "general", - "mipi", "pclk", "port"; - resets = <&reset RESET_PCIE_PHY>, - <&reset RESET_PCIE_A>, + resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>; - reset-names = "phy", - "port", + reset-names = "port", "apb"; + phys = <&pcie_phy>; + phy-names = "pcie"; }; diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt deleted file mode 100644 index 4a0475e2ba7e..000000000000 --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Cadence PCIe endpoint controller - -Required properties: -- compatible: Should contain "cdns,cdns-pcie-ep" to identify the IP used. -- reg: Should contain the controller register base address and AXI interface - region base address respectively. -- reg-names: Must be "reg" and "mem" respectively. -- cdns,max-outbound-regions: Set to maximum number of outbound regions - -Optional properties: -- max-functions: Maximum number of functions that can be configured (default 1). -- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more - than one in the list. If only one PHY listed it must manage all lanes. -- phy-names: List of names to identify the PHY. - -Example: - -pcie@fc000000 { - compatible = "cdns,cdns-pcie-ep"; - reg = <0x0 0xfc000000 0x0 0x01000000>, - <0x0 0x80000000 0x0 0x40000000>; - reg-names = "reg", "mem"; - cdns,max-outbound-regions = <16>; - max-functions = /bits/ 8 <8>; - phys = <&ep_phy0 &ep_phy1>; - phy-names = "pcie-lane0","pcie-lane1"; -}; diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml new file mode 100644 index 000000000000..2996f8d4777c --- /dev/null +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence PCIe EP Controller + +maintainers: + - Tom Joseph <tjoseph@cadence.com> + +allOf: + - $ref: "cdns-pcie.yaml#" + - $ref: "pci-ep.yaml#" + +properties: + compatible: + const: cdns,cdns-pcie-ep + + reg: + maxItems: 2 + + reg-names: + items: + - const: reg + - const: mem + +required: + - reg + - reg-names + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie-ep@fc000000 { + compatible = "cdns,cdns-pcie-ep"; + reg = <0x0 0xfc000000 0x0 0x01000000>, + <0x0 0x80000000 0x0 0x40000000>; + reg-names = "reg", "mem"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <8>; + phys = <&pcie_phy0>; + phy-names = "pcie-phy"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt deleted file mode 100644 index 91de69c713a9..000000000000 --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt +++ /dev/null @@ -1,66 +0,0 @@ -* Cadence PCIe host controller - -This PCIe controller inherits the base properties defined in -host-generic-pci.txt. - -Required properties: -- compatible: Should contain "cdns,cdns-pcie-host" to identify the IP used. -- reg: Should contain the controller register base address, PCIe configuration - window base address, and AXI interface region base address respectively. -- reg-names: Must be "reg", "cfg" and "mem" respectively. -- #address-cells: Set to <3> -- #size-cells: Set to <2> -- device_type: Set to "pci" -- ranges: Ranges for the PCI memory and I/O regions -- #interrupt-cells: Set to <1> -- interrupt-map-mask and interrupt-map: Standard PCI properties to define the - mapping of the PCIe interface to interrupt numbers. - -Optional properties: -- cdns,max-outbound-regions: Set to maximum number of outbound regions - (default 32) -- cdns,no-bar-match-nbits: Set into the no BAR match register to configure the - number of least significant bits kept during inbound (PCIe -> AXI) address - translations (default 32) -- vendor-id: The PCI vendor ID (16 bits, default is design dependent) -- device-id: The PCI device ID (16 bits, default is design dependent) -- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more - than one in the list. If only one PHY listed it must manage all lanes. -- phy-names: List of names to identify the PHY. - -Example: - -pcie@fb000000 { - compatible = "cdns,cdns-pcie-host"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - linux,pci-domain = <0>; - cdns,max-outbound-regions = <16>; - cdns,no-bar-match-nbits = <32>; - vendor-id = /bits/ 16 <0x17cd>; - device-id = /bits/ 16 <0x0200>; - - reg = <0x0 0xfb000000 0x0 0x01000000>, - <0x0 0x41000000 0x0 0x00001000>, - <0x0 0x40000000 0x0 0x04000000>; - reg-names = "reg", "cfg", "mem"; - - ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>, - <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>; - - #interrupt-cells = <0x1>; - - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1 - 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1 - 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1 - 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>; - - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - - msi-parent = <&its_pci>; - - phys = <&pcie_phy0>; - phy-names = "pcie-phy"; -}; diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml new file mode 100644 index 000000000000..cabbe46ff578 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence PCIe host controller + +maintainers: + - Tom Joseph <tjoseph@cadence.com> + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: "cdns-pcie-host.yaml#" + +properties: + compatible: + const: cdns,cdns-pcie-host + + reg: + maxItems: 3 + + reg-names: + items: + - const: reg + - const: cfg + - const: mem + + msi-parent: true + +required: + - reg + - reg-names + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie@fb000000 { + compatible = "cdns,cdns-pcie-host"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + linux,pci-domain = <0>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <32>; + vendor-id = <0x17cd>; + device-id = <0x0200>; + + reg = <0x0 0xfb000000 0x0 0x01000000>, + <0x0 0x41000000 0x0 0x00001000>, + <0x0 0x40000000 0x0 0x04000000>; + reg-names = "reg", "cfg", "mem"; + + ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>, + <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>; + + #interrupt-cells = <0x1>; + + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1>, + <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1>, + <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1>, + <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>; + + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + + msi-parent = <&its_pci>; + + phys = <&pcie_phy0>; + phy-names = "pcie-phy"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml new file mode 100644 index 000000000000..ab6e43b636ec --- /dev/null +++ b/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/pci/cdns-pcie-host.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Cadence PCIe Host + +maintainers: + - Tom Joseph <tjoseph@cadence.com> + +allOf: + - $ref: "/schemas/pci/pci-bus.yaml#" + - $ref: "cdns-pcie.yaml#" + +properties: + cdns,no-bar-match-nbits: + description: + Set into the no BAR match register to configure the number of least + significant bits kept during inbound (PCIe -> AXI) address translations + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 64 + default: 32 + + msi-parent: true diff --git a/Documentation/devicetree/bindings/pci/cdns-pcie.yaml b/Documentation/devicetree/bindings/pci/cdns-pcie.yaml new file mode 100644 index 000000000000..6887ccc339cc --- /dev/null +++ b/Documentation/devicetree/bindings/pci/cdns-pcie.yaml @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/pci/cdns-pcie.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Cadence PCIe Core + +maintainers: + - Tom Joseph <tjoseph@cadence.com> + +properties: + cdns,max-outbound-regions: + description: maximum number of outbound regions + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 32 + default: 32 + + phys: + description: + One per lane if more than one in the list. If only one PHY listed it must + manage all lanes. + minItems: 1 + maxItems: 16 + + phy-names: + items: + - const: pcie-phy + # FIXME: names when more than 1 diff --git a/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt b/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt new file mode 100644 index 000000000000..b40fb5d15d3d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt @@ -0,0 +1,52 @@ +NXP Layerscape PCIe Gen4 controller + +This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all +the common properties defined in mobiveil-pcie.txt. + +Required properties: +- compatible: should contain the platform identifier such as: + "fsl,lx2160a-pcie" +- reg: base addresses and lengths of the PCIe controller register blocks. + "csr_axi_slave": Bridge config registers + "config_axi_slave": PCIe controller registers +- interrupts: A list of interrupt outputs of the controller. Must contain an + entry for each entry in the interrupt-names property. +- interrupt-names: It could include the following entries: + "intr": The interrupt that is asserted for controller interrupts + "aer": Asserted for aer interrupt when chip support the aer interrupt with + none MSI/MSI-X/INTx mode,but there is interrupt line for aer. + "pme": Asserted for pme interrupt when chip support the pme interrupt with + none MSI/MSI-X/INTx mode,but there is interrupt line for pme. +- dma-coherent: Indicates that the hardware IP block can ensure the coherency + of the data transferred from/to the IP block. This can avoid the software + cache flush/invalid actions, and improve the performance significantly. +- msi-parent : See the generic MSI binding described in + Documentation/devicetree/bindings/interrupt-controller/msi.txt. + +Example: + + pcie@3400000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x80 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + apio-wins = <8>; + ppio-wins = <8>; + dma-coherent; + bus-range = <0x0 0xff>; + msi-parent = <&its>; + ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt index b739f92da58e..bd43f3c3ece4 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt @@ -1,11 +1,11 @@ NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based) -This PCIe host controller is based on the Synopsis Designware PCIe IP +This PCIe controller is based on the Synopsis Designware PCIe IP and thus inherits all the common properties defined in designware-pcie.txt. +Some of the controller instances are dual mode where in they can work either +in root port mode or endpoint mode but one at a time. Required properties: -- compatible: For Tegra19x, must contain "nvidia,tegra194-pcie". -- device_type: Must be "pci" - power-domains: A phandle to the node that controls power to the respective PCIe controller and a specifier name for the PCIe controller. Following are the specifiers for the different PCIe controllers @@ -32,6 +32,32 @@ Required properties: entry for each entry in the interrupt-names property. - interrupt-names: Must include the following entries: "intr": The Tegra interrupt that is asserted for controller interrupts +- clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: Must include the following entries: + - core +- resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names: Must include the following entries: + - apb + - core +- phys: Must contain a phandle to P2U PHY for each entry in phy-names. +- phy-names: Must include an entry for each active lane. + "p2u-N": where N ranges from 0 to one less than the total number of lanes +- nvidia,bpmp: Must contain a pair of phandle to BPMP controller node followed + by controller-id. Following are the controller ids for each controller. + 0: C0 + 1: C1 + 2: C2 + 3: C3 + 4: C4 + 5: C5 +- vddio-pex-ctl-supply: Regulator supply for PCIe side band signals + +RC mode: +- compatible: Tegra19x must contain "nvidia,tegra194-pcie" +- device_type: Must be "pci" for RC mode +- interrupt-names: Must include the following entries: "msi": The Tegra interrupt that is asserted when an MSI is received - bus-range: Range of bus numbers associated with this controller - #address-cells: Address representation for root ports (must be 3) @@ -60,27 +86,15 @@ Required properties: - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties Please refer to the standard PCI bus binding document for a more detailed explanation. -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - core -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - apb - - core -- phys: Must contain a phandle to P2U PHY for each entry in phy-names. -- phy-names: Must include an entry for each active lane. - "p2u-N": where N ranges from 0 to one less than the total number of lanes -- nvidia,bpmp: Must contain a pair of phandle to BPMP controller node followed - by controller-id. Following are the controller ids for each controller. - 0: C0 - 1: C1 - 2: C2 - 3: C3 - 4: C4 - 5: C5 -- vddio-pex-ctl-supply: Regulator supply for PCIe side band signals + +EP mode: +In Tegra194, Only controllers C0, C4 & C5 support EP mode. +- compatible: Tegra19x must contain "nvidia,tegra194-pcie-ep" +- reg-names: Must include the following entries: + "addr_space": Used to map remote RC address space +- reset-gpios: Must contain a phandle to a GPIO controller followed by + GPIO that is being used as PERST input signal. Please refer to pci.txt + document. Optional properties: - pinctrl-names: A list of pinctrl state names. @@ -104,6 +118,8 @@ Optional properties: specified in microseconds - nvidia,aspm-l0s-entrance-latency-us: ASPM L0s entrance latency to be specified in microseconds + +RC mode: - vpcie3v3-supply: A phandle to the regulator node that supplies 3.3V to the slot if the platform has one such slot. (Ex:- x16 slot owned by C5 controller in p2972-0000 platform). @@ -111,14 +127,21 @@ Optional properties: if the platform has one such slot. (Ex:- x16 slot owned by C5 controller in p2972-0000 platform). +EP mode: +- nvidia,refclk-select-gpios: Must contain a phandle to a GPIO controller + followed by GPIO that is being used to enable REFCLK to controller from host + +NOTE:- On Tegra194's P2972-0000 platform, only C5 controller can be enabled to +operate in the endpoint mode because of the way the platform is designed. + Examples: ========= -Tegra194: --------- +Tegra194 RC mode: +----------------- pcie@14180000 { - compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; + compatible = "nvidia,tegra194-pcie"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */ 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */ @@ -169,3 +192,53 @@ Tegra194: <&p2u_hsio_5>; phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; }; + +Tegra194 EP mode: +----------------- + + pcie_ep@141a0000 { + compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; + reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */ + 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ + 0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */ + 0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ + reg-names = "appl", "atu_dma", "dbi", "addr_space"; + + num-lanes = <8>; + num-ib-windows = <2>; + num-ob-windows = <8>; + + pinctrl-names = "default"; + pinctrl-0 = <&clkreq_c5_bi_dir_state>; + + clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; + clock-names = "core"; + + resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, + <&bpmp TEGRA194_RESET_PEX1_CORE_5>; + reset-names = "apb", "core"; + + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 5>; + + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; + + vddio-pex-ctl-supply = <&vdd_1v8ao>; + + reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>; + + nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5) + GPIO_ACTIVE_HIGH>; + + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, + <&p2u_nvhs_6>, <&p2u_nvhs_7>; + + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", + "p2u-5", "p2u-6", "p2u-7"; + }; diff --git a/Documentation/devicetree/bindings/pci/pci-ep.yaml b/Documentation/devicetree/bindings/pci/pci-ep.yaml new file mode 100644 index 000000000000..b3df100705b0 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/pci-ep.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/pci-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCI Endpoint Controller Schema + +description: | + Common properties for PCI Endpoint Controller Nodes. + +maintainers: + - Kishon Vijay Abraham I <kishon@ti.com> + +properties: + $nodename: + pattern: "^pcie-ep@" + + max-functions: + description: Maximum number of functions that can be configured + allOf: + - $ref: /schemas/types.yaml#/definitions/uint8 + minimum: 1 + default: 1 + maximum: 255 + + max-link-speed: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 1, 2, 3, 4 ] + + num-lanes: + description: maximum number of lanes + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + default: 1 + maximum: 16 + +required: + - compatible diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun50i-h6-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun50i-h6-usb3-phy.yaml index e5922b427342..c03b83103e87 100644 --- a/Documentation/devicetree/bindings/phy/allwinner,sun50i-h6-usb3-phy.yaml +++ b/Documentation/devicetree/bindings/phy/allwinner,sun50i-h6-usb3-phy.yaml @@ -34,6 +34,8 @@ required: - resets - "#phy-cells" +additionalProperties: false + examples: - | #include <dt-bindings/clock/sun50i-h6-ccu.h> diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml new file mode 100644 index 000000000000..88683db6cf81 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/amlogic,meson-axg-mipi-pcie-analog.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic AXG shared MIPI/PCIE analog PHY + +maintainers: + - Remi Pommarel <repk@triplefau.lt> + +properties: + compatible: + const: amlogic,axg-mipi-pcie-analog-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 1 + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + mpphy: phy@0 { + compatible = "amlogic,axg-mipi-pcie-analog-phy"; + reg = <0x0 0x0 0x0 0xc>; + #phy-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml new file mode 100644 index 000000000000..086478aec946 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/amlogic,meson-axg-pcie.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic AXG PCIE PHY + +maintainers: + - Remi Pommarel <repk@triplefau.lt> + +properties: + compatible: + const: amlogic,axg-pcie-phy + + reg: + maxItems: 1 + + resets: + maxItems: 1 + + phys: + maxItems: 1 + + phy-names: + const: analog + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - phys + - phy-names + - resets + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/reset/amlogic,meson-axg-reset.h> + #include <dt-bindings/phy/phy.h> + pcie_phy: pcie-phy@ff644000 { + compatible = "amlogic,axg-pcie-phy"; + reg = <0x0 0xff644000 0x0 0x1c>; + resets = <&reset RESET_PCIE_PHY>; + phys = <&mipi_analog_phy PHY_TYPE_PCIE>; + phy-names = "analog"; + #phy-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml index 346f9c35427c..453c083cf44c 100644 --- a/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml @@ -44,6 +44,8 @@ required: - reset-names - "#phy-cells" +additionalProperties: false + examples: - | phy@46000 { diff --git a/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml b/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml index 0ccee64c6962..9a346d6290d9 100644 --- a/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml +++ b/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml @@ -40,6 +40,8 @@ required: - reg - clocks +additionalProperties: false + examples: - | sysconf: chiptop@e0200000 { diff --git a/Documentation/devicetree/bindings/phy/marvell,mmp3-hsic-phy.yaml b/Documentation/devicetree/bindings/phy/marvell,mmp3-hsic-phy.yaml index 5ab436189f3b..00609ace677c 100644 --- a/Documentation/devicetree/bindings/phy/marvell,mmp3-hsic-phy.yaml +++ b/Documentation/devicetree/bindings/phy/marvell,mmp3-hsic-phy.yaml @@ -31,6 +31,8 @@ required: - reset-gpios - "#phy-cells" +additionalProperties: false + examples: - | #include <dt-bindings/gpio/gpio.h> diff --git a/Documentation/devicetree/bindings/phy/marvell,mmp3-usb-phy.yaml b/Documentation/devicetree/bindings/phy/marvell,mmp3-usb-phy.yaml new file mode 100644 index 000000000000..c97043eaa8fb --- /dev/null +++ b/Documentation/devicetree/bindings/phy/marvell,mmp3-usb-phy.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +# Copyright 2019,2020 Lubomir Rintel <lkundrak@v3.sk> +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/marvell,mmp3-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell MMP3 USB PHY bindings + +maintainers: + - Lubomir Rintel <lkundrak@v3.sk> + +properties: + $nodename: + pattern: '^usb-phy@[a-f0-9]+$' + + compatible: + const: marvell,mmp3-usb-phy + + reg: + maxItems: 1 + description: base address of the device + + '#phy-cells': + const: 0 + +required: + - compatible + - reg + - '#phy-cells' + +additionalProperties: false + +examples: + - | + usb-phy@d4207000 { + compatible = "marvell,mmp3-usb-phy"; + reg = <0xd4207000 0x40>; + #phy-cells = <0>; + }; + +... diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt index 9fb682e47c29..38c5fa21f435 100644 --- a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt @@ -37,6 +37,7 @@ Required properties: - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl" - Tegra210: "nvidia,tegra210-xusb-padctl" - Tegra186: "nvidia,tegra186-xusb-padctl" + - Tegra194: "nvidia,tegra194-xusb-padctl" - reg: Physical base address and length of the controller's registers. - resets: Must contain an entry for each entry in reset-names. - reset-names: Must include the following entries: @@ -62,6 +63,10 @@ For Tegra186: - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V. - vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V. +For Tegra194: +- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply + 3.3 V. +- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V. Pad nodes: ========== @@ -154,6 +159,11 @@ For Tegra210, the list of valid PHY nodes is given below: - sata: sata-0 - functions: "usb3-ss", "sata" +For Tegra194, the list of valid PHY nodes is given below: +- usb2: usb2-0, usb2-1, usb2-2, usb2-3 + - functions: "xusb" +- usb3: usb3-0, usb3-1, usb3-2, usb3-3 + - functions: "xusb" Port nodes: =========== @@ -174,6 +184,12 @@ Required properties: - "device": for USB device mode - "otg": for USB OTG mode +Required properties for OTG/Peripheral capable USB2 ports: +- usb-role-switch: Boolean property to indicate that the port support OTG or + peripheral mode. If present, the port supports switching between USB host + and peripheral roles. Connector should be added as subnode. + See usb/usb-conn-gpio.txt. + Optional properties: - nvidia,internal: A boolean property whose presence determines that a port is internal. In the absence of this property the port is considered to be @@ -221,6 +237,11 @@ Optional properties: is internal. In the absence of this property the port is considered to be external. +- maximum-speed: Only for Tegra194. A string property that specifies maximum + supported speed of a usb3 port. Valid values are: + - "super-speed-plus": default, the usb3 port supports USB 3.1 Gen 2 speed. + - "super-speed": the usb3 port supports USB 3.1 Gen 1 speed only. + For Tegra124 and Tegra132, the XUSB pad controller exposes the following ports: - 3x USB2: usb2-0, usb2-1, usb2-2 @@ -233,6 +254,9 @@ For Tegra210, the XUSB pad controller exposes the following ports: - 2x HSIC: hsic-0, hsic-1 - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3 +For Tegra194, the XUSB pad controller exposes the following ports: +- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3 +- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3 Examples: ========= diff --git a/Documentation/devicetree/bindings/phy/phy-mmp3-usb.txt b/Documentation/devicetree/bindings/phy/phy-mmp3-usb.txt deleted file mode 100644 index 7183b9102f91..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-mmp3-usb.txt +++ /dev/null @@ -1,13 +0,0 @@ -Marvell MMP3 USB PHY --------------------- - -Required properties: -- compatible: must be "marvell,mmp3-usb-phy" -- #phy-cells: must be 0 - -Example: - usb-phy: usb-phy@d4207000 { - compatible = "marvell,mmp3-usb-phy"; - reg = <0xd4207000 0x40>; - #phy-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt deleted file mode 100644 index 541f5298827c..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt +++ /dev/null @@ -1,81 +0,0 @@ -ROCKCHIP USB2.0 PHY WITH INNO IP BLOCK - -Required properties (phy (parent) node): - - compatible : should be one of the listed compatibles: - * "rockchip,px30-usb2phy" - * "rockchip,rk3228-usb2phy" - * "rockchip,rk3328-usb2phy" - * "rockchip,rk3366-usb2phy" - * "rockchip,rk3399-usb2phy" - * "rockchip,rv1108-usb2phy" - - reg : the address offset of grf for usb-phy configuration. - - #clock-cells : should be 0. - - clock-output-names : specify the 480m output clock name. - -Optional properties: - - clocks : phandle + phy specifier pair, for the input clock of phy. - - clock-names : input clock name of phy, must be "phyclk". - - assigned-clocks : phandle of usb 480m clock. - - assigned-clock-parents : parent of usb 480m clock, select between - usb-phy output 480m and xin24m. - Refer to clk/clock-bindings.txt for generic clock - consumer properties. - - rockchip,usbgrf : phandle to the syscon managing the "usb general - register files". When set driver will request its - phandle as one companion-grf for some special SoCs - (e.g RV1108). - - extcon : phandle to the extcon device providing the cable state for - the otg phy. - -Required nodes : a sub-node is required for each port the phy provides. - The sub-node name is used to identify host or otg port, - and shall be the following entries: - * "otg-port" : the name of otg port. - * "host-port" : the name of host port. - -Required properties (port (child) node): - - #phy-cells : must be 0. See ./phy-bindings.txt for details. - - interrupts : specify an interrupt for each entry in interrupt-names. - - interrupt-names : a list which should be one of the following cases: - Regular case: - * "otg-id" : for the otg id interrupt. - * "otg-bvalid" : for the otg vbus interrupt. - * "linestate" : for the host/otg linestate interrupt. - Some SoCs use one interrupt with the above muxed together, so for these - * "otg-mux" : otg-port interrupt, which mux otg-id/otg-bvalid/linestate - to one. - -Optional properties: - - phy-supply : phandle to a regulator that provides power to VBUS. - See ./phy-bindings.txt for details. - -Example: - -grf: syscon@ff770000 { - compatible = "rockchip,rk3366-grf", "syscon", "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - -... - - u2phy: usb2-phy@700 { - compatible = "rockchip,rk3366-usb2phy"; - reg = <0x700 0x2c>; - #clock-cells = <0>; - clock-output-names = "sclk_otgphy0_480m"; - - u2phy_otg: otg-port { - #phy-cells = <0>; - interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "otg-id", "otg-bvalid", "linestate"; - }; - - u2phy_host: host-port { - #phy-cells = <0>; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "linestate"; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml new file mode 100644 index 000000000000..cb71561a21b4 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml @@ -0,0 +1,155 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/phy-rockchip-inno-usb2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip USB2.0 phy with inno IP block + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + enum: + - rockchip,px30-usb2phy + - rockchip,rk3228-usb2phy + - rockchip,rk3328-usb2phy + - rockchip,rk3366-usb2phy + - rockchip,rk3399-usb2phy + - rockchip,rv1108-usb2phy + + reg: + maxItems: 1 + + clock-output-names: + description: + The usb 480m output clock name. + + "#clock-cells": + const: 0 + + "#phy-cells": + const: 0 + + clocks: + maxItems: 1 + + clock-names: + const: phyclk + + assigned-clocks: + description: + Phandle of the usb 480m clock. + + assigned-clock-parents: + description: + Parent of the usb 480m clock. + Select between usb-phy output 480m and xin24m. + Refer to clk/clock-bindings.txt for generic clock consumer properties. + + extcon: + description: + Phandle to the extcon device providing the cable state for the otg phy. + + rockchip,usbgrf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the 'usb general register files'. + When set the driver will request its phandle as one companion-grf + for some special SoCs (e.g rv1108). + + host-port: + type: object + additionalProperties: false + + properties: + "#phy-cells": + const: 0 + + interrupts: + description: host linestate interrupt + + interrupt-names: + const: linestate + + phy-supply: + description: + Phandle to a regulator that provides power to VBUS. + See ./phy-bindings.txt for details. + + required: + - "#phy-cells" + - interrupts + - interrupt-names + + otg-port: + type: object + additionalProperties: false + + properties: + "#phy-cells": + const: 0 + + interrupts: + minItems: 1 + maxItems: 3 + + interrupt-names: + oneOf: + - const: linestate + - const: otg-mux + - items: + - const: otg-bvalid + - const: otg-id + - const: linestate + + phy-supply: + description: + Phandle to a regulator that provides power to VBUS. + See ./phy-bindings.txt for details. + + required: + - "#phy-cells" + - interrupts + - interrupt-names + +required: + - compatible + - reg + - clock-output-names + - "#clock-cells" + - "#phy-cells" + - host-port + - otg-port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3399-cru.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + u2phy0: usb2-phy@e450 { + compatible = "rockchip,rk3399-usb2phy"; + reg = <0xe450 0x10>; + clocks = <&cru SCLK_USB2PHY0_REF>; + clock-names = "phyclk"; + clock-output-names = "clk_usbphy0_480m"; + #clock-cells = <0>; + #phy-cells = <0>; + + u2phy0_host: host-port { + #phy-cells = <0>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "linestate"; + }; + + u2phy0_otg: otg-port { + #phy-cells = <0>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "otg-bvalid", "otg-id", "linestate"; + }; + }; diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml index 452cee1aed32..3f913d6d1c3d 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml @@ -146,7 +146,7 @@ patternProperties: bindings specified in Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt Torrent SERDES should follow the bindings specified in - Documentation/devicetree/bindings/phy/phy-cadence-dp.txt + Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml required: - compatible @@ -159,6 +159,8 @@ required: - "#reset-cells" - ranges +additionalProperties: false + examples: - | #include <dt-bindings/soc/ti,sci_pm_domain.h> diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml index 135c7dfbc180..7651a675ab2d 100644 --- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml @@ -57,6 +57,8 @@ patternProperties: required: - compatible +additionalProperties: false + examples: - | syscon: scu@1e6e2000 { diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml index 824f7fd1d51b..36feaf5e2dff 100644 --- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml @@ -70,6 +70,8 @@ required: - compatible - aspeed,external-nodes +additionalProperties: false + examples: - | apb { diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml index ac8d1c30a8ed..45af29bc3202 100644 --- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml @@ -92,6 +92,8 @@ patternProperties: required: - compatible +additionalProperties: false + examples: - | syscon: scu@1e6e2000 { diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt index eb39f5051159..e8abbdad7b5d 100644 --- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt @@ -38,7 +38,7 @@ Bank: 3 (A, B and C) 0xffffffff 0x7fff3ccf /* pioB */ 0xffffffff 0x007fffff /* pioC */ -For each peripheral/bank we will descibe in a u32 if a pin can be +For each peripheral/bank we will describe in a u32 if a pin can be configured in it by putting 1 to the pin bit (1 << pin) Let's take the pioA on peripheral B diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt deleted file mode 100644 index e4e01c05cf83..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt +++ /dev/null @@ -1,36 +0,0 @@ -* Freescale IMX8MM IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory -for common binding part and usage. - -Required properties: -- compatible: "fsl,imx8mm-iomuxc" -- reg: should contain the base physical address and size of the iomuxc - registers. - -Required properties in sub-nodes: -- fsl,pins: each entry consists of 6 integers and represents the mux and config - setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val - input_val> are specified using a PIN_FUNC_ID macro, which can be found in - <arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h>. The last integer CONFIG is - the pad setting value like pull-up on this pin. Please refer to i.MX8M Mini - Reference Manual for detailed CONFIG settings. - -Examples: - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; -}; - -iomuxc: pinctrl@30330000 { - compatible = "fsl,imx8mm-iomuxc"; - reg = <0x0 0x30330000 0x0 0x10000>; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - >; - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.yaml new file mode 100644 index 000000000000..d98a3866add8 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mm-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale IMX8MM IOMUX Controller + +maintainers: + - Anson Huang <Anson.Huang@nxp.com> + +description: + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory + for common binding part and usage. + +properties: + compatible: + const: fsl,imx8mm-iomuxc + + reg: + maxItems: 1 + +# Client device subnode's properties +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg + mux_val input_val> are specified using a PIN_FUNC_ID macro, which can + be found in <arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h>. The last + integer CONFIG is the pad setting value like pull-up on this pin. Please + refer to i.MX8M Mini Reference Manual for detailed CONFIG settings. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-matrix + - items: + items: + - description: | + "mux_reg" indicates the offset of mux register. + - description: | + "conf_reg" indicates the offset of pad configuration register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_val" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied. + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + # Pinmux controller node + - | + iomuxc: pinctrl@30330000 { + compatible = "fsl,imx8mm-iomuxc"; + reg = <0x30330000 0x10000>; + + pinctrl_uart2: uart2grp { + fsl,pins = + <0x23C 0x4A4 0x4FC 0x0 0x0 0x140>, + <0x240 0x4A8 0x000 0x0 0x0 0x140>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.txt deleted file mode 100644 index 330716c971b9..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.txt +++ /dev/null @@ -1,39 +0,0 @@ -* Freescale IMX8MN IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory -for common binding part and usage. - -Required properties: -- compatible: "fsl,imx8mn-iomuxc" -- reg: should contain the base physical address and size of the iomuxc - registers. - -Required properties in sub-nodes: -- fsl,pins: each entry consists of 6 integers and represents the mux and config - setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val - input_val> are specified using a PIN_FUNC_ID macro, which can be found in - <arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h>. The last integer CONFIG is - the pad setting value like pull-up on this pin. Please refer to i.MX8M Nano - Reference Manual for detailed CONFIG settings. - -Examples: - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; -}; - -iomuxc: pinctrl@30330000 { - compatible = "fsl,imx8mn-iomuxc"; - reg = <0x0 0x30330000 0x0 0x10000>; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 - MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 - MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 - >; - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.yaml new file mode 100644 index 000000000000..b9aa180e07e4 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mn-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale IMX8MN IOMUX Controller + +maintainers: + - Anson Huang <Anson.Huang@nxp.com> + +description: + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory + for common binding part and usage. + +properties: + compatible: + const: fsl,imx8mn-iomuxc + + reg: + maxItems: 1 + +# Client device subnode's properties +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg + mux_val input_val> are specified using a PIN_FUNC_ID macro, which can + be found in <arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h>. The last + integer CONFIG is the pad setting value like pull-up on this pin. Please + refer to i.MX8M Nano Reference Manual for detailed CONFIG settings. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-matrix + - items: + items: + - description: | + "mux_reg" indicates the offset of mux register. + - description: | + "conf_reg" indicates the offset of pad configuration register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_val" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied. + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + # Pinmux controller node + - | + iomuxc: pinctrl@30330000 { + compatible = "fsl,imx8mn-iomuxc"; + reg = <0x30330000 0x10000>; + + pinctrl_uart2: uart2grp { + fsl,pins = + <0x23C 0x4A4 0x4FC 0x0 0x0 0x140>, + <0x240 0x4A8 0x000 0x0 0x0 0x140>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml index 2e31e120395e..6297e78418cf 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml @@ -30,8 +30,6 @@ patternProperties: properties: fsl,pins: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array description: each entry consists of 6 integers and represents the mux and config setting for one pin. The first 5 integers <mux_reg conf_reg input_reg @@ -39,6 +37,22 @@ patternProperties: be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last integer CONFIG is the pad setting value like pull-up on this pin. Please refer to i.MX8M Plus Reference Manual for detailed CONFIG settings. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-matrix + - items: + items: + - description: | + "mux_reg" indicates the offset of mux register. + - description: | + "conf_reg" indicates the offset of pad configuration register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_val" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied. required: - fsl,pins @@ -59,10 +73,9 @@ examples: reg = <0x30330000 0x10000>; pinctrl_uart2: uart2grp { - fsl,pins = < - 0x228 0x488 0x5F0 0x0 0x6 0x49 - 0x228 0x488 0x000 0x0 0x0 0x49 - >; + fsl,pins = + <0x228 0x488 0x5F0 0x0 0x6 0x49>, + <0x228 0x488 0x000 0x0 0x0 0x49>; }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt deleted file mode 100644 index 66de75090458..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt +++ /dev/null @@ -1,36 +0,0 @@ -* Freescale IMX8MQ IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory -for common binding part and usage. - -Required properties: -- compatible: "fsl,imx8mq-iomuxc" -- reg: should contain the base physical address and size of the iomuxc - registers. - -Required properties in sub-nodes: -- fsl,pins: each entry consists of 6 integers and represents the mux and config - setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val - input_val> are specified using a PIN_FUNC_ID macro, which can be found in - imx8mq-pinfunc.h under device tree source folder. The last integer CONFIG is - the pad setting value like pull-up on this pin. Please refer to i.MX8M Quad - Reference Manual for detailed CONFIG settings. - -Examples: - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; -}; - -iomuxc: pinctrl@30330000 { - compatible = "fsl,imx8mq-iomuxc"; - reg = <0x0 0x30330000 0x0 0x10000>; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - >; - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.yaml new file mode 100644 index 000000000000..b30c704fcfa1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mq-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale IMX8MQ IOMUX Controller + +maintainers: + - Anson Huang <Anson.Huang@nxp.com> + +description: + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory + for common binding part and usage. + +properties: + compatible: + const: fsl,imx8mq-iomuxc + + reg: + maxItems: 1 + +# Client device subnode's properties +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg + mux_val input_val> are specified using a PIN_FUNC_ID macro, which can + be found in <arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h>. The last + integer CONFIG is the pad setting value like pull-up on this pin. Please + refer to i.MX8M Quad Reference Manual for detailed CONFIG settings. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-matrix + - items: + items: + - description: | + "mux_reg" indicates the offset of mux register. + - description: | + "conf_reg" indicates the offset of pad configuration register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_val" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied. + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + # Pinmux controller node + - | + iomuxc: pinctrl@30330000 { + compatible = "fsl,imx8mq-iomuxc"; + reg = <0x30330000 0x10000>; + + pinctrl_uart1: uart1grp { + fsl,pins = + <0x234 0x49C 0x4F4 0x0 0x0 0x49>, + <0x238 0x4A0 0x4F4 0x0 0x0 0x49>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml new file mode 100644 index 000000000000..63d1cfe86c6e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq6018-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. IPQ6018 TLMM block + +maintainers: + - Sricharan R <sricharan@codeaurora.org> + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + IPQ6018 platform. + +properties: + compatible: + const: qcom,ipq6018-pinctrl + + reg: + maxItems: 1 + + interrupts: + description: Specifies the TLMM summary IRQ + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + description: + Specifies the PIN numbers and Flags, as defined in defined in + include/dt-bindings/interrupt-controller/irq.h + const: 2 + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '-pinmux$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + allOf: + - $ref: "/schemas/pinctrl/pincfg-node.yaml" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([1-9]|[1-7][0-9]|80)$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, + sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2, + qdsd_data3 ] + minItems: 1 + maxItems: 4 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, atest_char, + atest_char0, atest_char1, atest_char2, atest_char3, atest_combodac, + atest_gpsadc0, atest_gpsadc1, atest_tsens, atest_wlan0, + atest_wlan1, backlight_en, bimc_dte0, bimc_dte1, blsp1_i2c, + blsp2_i2c, blsp3_i2c, blsp4_i2c, blsp5_i2c, blsp6_i2c, blsp1_spi, + blsp1_spi_cs1, blsp1_spi_cs2, blsp1_spi_cs3, blsp2_spi, + blsp2_spi_cs1, blsp2_spi_cs2, blsp2_spi_cs3, blsp3_spi, + blsp3_spi_cs1, blsp3_spi_cs2, blsp3_spi_cs3, blsp4_spi, blsp5_spi, + blsp6_spi, blsp1_uart, blsp2_uart, blsp1_uim, blsp2_uim, cam1_rst, + cam1_standby, cam_mclk0, cam_mclk1, cci_async, cci_i2c, cci_timer0, + cci_timer1, cci_timer2, cdc_pdm0, codec_mad, dbg_out, display_5v, + dmic0_clk, dmic0_data, dsi_rst, ebi0_wrcdc, euro_us, ext_lpass, + flash_strobe, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, + gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gpio, gsm0_tx0, + gsm0_tx1, gsm1_tx0, gsm1_tx1, gyro_accl, kpsns0, kpsns1, kpsns2, + ldo_en, ldo_update, mag_int, mdp_vsync, modem_tsync, m_voc, + nav_pps, nav_tsync, pa_indicator, pbs0, pbs1, pbs2, pri_mi2s, + pri_mi2s_ws, prng_rosc, pwr_crypto_enabled_a, pwr_crypto_enabled_b, + pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a, + pwr_nav_enabled_b, qdss_ctitrig_in_a0, qdss_ctitrig_in_a1, + qdss_ctitrig_in_b0, qdss_ctitrig_in_b1, qdss_ctitrig_out_a0, + qdss_ctitrig_out_a1, qdss_ctitrig_out_b0, qdss_ctitrig_out_b1, + qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, + qdss_tracedata_a, qdss_tracedata_b, reset_n, sd_card, sd_write, + sec_mi2s, smb_int, ssbi_wtr0, ssbi_wtr1, uim1, uim2, uim3, + uim_batt, wcss_bt, wcss_fm, wcss_wlan, webcam1_rst ] + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq6018-pinctrl"; + reg = <0x01000000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 80>; + + serial3-pinmux { + pins = "gpio44", "gpio45"; + function = "blsp2_uart"; + drive-strength = <8>; + bias-pull-down; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt deleted file mode 100644 index 8173b12138ad..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt +++ /dev/null @@ -1,27 +0,0 @@ -UniPhier SoCs pin controller - -Required properties: -- compatible: should be one of the following: - "socionext,uniphier-ld4-pinctrl" - for LD4 SoC - "socionext,uniphier-pro4-pinctrl" - for Pro4 SoC - "socionext,uniphier-sld8-pinctrl" - for sLD8 SoC - "socionext,uniphier-pro5-pinctrl" - for Pro5 SoC - "socionext,uniphier-pxs2-pinctrl" - for PXs2 SoC - "socionext,uniphier-ld6b-pinctrl" - for LD6b SoC - "socionext,uniphier-ld11-pinctrl" - for LD11 SoC - "socionext,uniphier-ld20-pinctrl" - for LD20 SoC - "socionext,uniphier-pxs3-pinctrl" - for PXs3 SoC - -Note: -The UniPhier pinctrl should be a subnode of a "syscon" compatible node. - -Example: - soc-glue@5f800000 { - compatible = "socionext,uniphier-pro4-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - - pinctrl: pinctrl { - compatible = "socionext,uniphier-pro4-pinctrl"; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml new file mode 100644 index 000000000000..f8a93d8680f9 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/socionext,uniphier-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier SoCs pin controller + +maintainers: + - Masahiro Yamada <yamada.masahiro@socionext.com> + +properties: + $nodename: + pattern: "pinctrl" + + compatible: + enum: + - socionext,uniphier-ld4-pinctrl + - socionext,uniphier-pro4-pinctrl + - socionext,uniphier-sld8-pinctrl + - socionext,uniphier-pro5-pinctrl + - socionext,uniphier-pxs2-pinctrl + - socionext,uniphier-ld6b-pinctrl + - socionext,uniphier-ld11-pinctrl + - socionext,uniphier-ld20-pinctrl + - socionext,uniphier-pxs3-pinctrl + +required: + - compatible + +examples: + - | + // The UniPhier pinctrl should be a subnode of a "syscon" compatible node. + + soc-glue@5f800000 { + compatible = "socionext,uniphier-pro4-soc-glue", "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-pro4-pinctrl"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml index ef4de32cb17c..46a0478cb924 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml @@ -194,6 +194,8 @@ required: - ranges - pins-are-numbered +additionalProperties: false + examples: - | #include <dt-bindings/pinctrl/stm32-pinfunc.h> diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml b/Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml index d3098c924b25..6c6079fe1351 100644 --- a/Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml +++ b/Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml @@ -68,6 +68,8 @@ required: - "#power-domain-cells" - amlogic,ao-sysctrl +additionalProperties: false + examples: - | pwrc: power-controller { diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml new file mode 100644 index 000000000000..bc4e037f3f73 --- /dev/null +++ b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) +# Copyright (c) 2019 Amlogic, Inc +# Author: Jianxin Pan <jianxin.pan@amlogic.com> +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/power/amlogic,meson-sec-pwrc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic Meson Secure Power Domains + +maintainers: + - Jianxin Pan <jianxin.pan@amlogic.com> + +description: |+ + Secure Power Domains used in Meson A1/C1 SoCs, and should be the child node + of secure-monitor. + +properties: + compatible: + enum: + - amlogic,meson-a1-pwrc + + "#power-domain-cells": + const: 1 + +required: + - compatible + - "#power-domain-cells" + +examples: + - | + secure-monitor { + compatible = "amlogic,meson-gxbb-sm"; + + pwrc: power-controller { + compatible = "amlogic,meson-a1-pwrc"; + #power-domain-cells = <1>; + }; + }; + diff --git a/Documentation/devicetree/bindings/power/power-domain.yaml b/Documentation/devicetree/bindings/power/power-domain.yaml index 6047aacd7766..ff5936e4a215 100644 --- a/Documentation/devicetree/bindings/power/power-domain.yaml +++ b/Documentation/devicetree/bindings/power/power-domain.yaml @@ -114,18 +114,18 @@ examples: domain-idle-states = <&DOMAIN_PWR_DN>; }; - DOMAIN_RET: state@0 { - compatible = "domain-idle-state"; - reg = <0x0 0x0>; - entry-latency-us = <1000>; - exit-latency-us = <2000>; - min-residency-us = <10000>; - }; - - DOMAIN_PWR_DN: state@1 { - compatible = "domain-idle-state"; - reg = <0x1 0x0>; - entry-latency-us = <5000>; - exit-latency-us = <8000>; - min-residency-us = <7000>; + domain-idle-states { + DOMAIN_RET: domain-retention { + compatible = "domain-idle-state"; + entry-latency-us = <1000>; + exit-latency-us = <2000>; + min-residency-us = <10000>; + }; + + DOMAIN_PWR_DN: domain-pwr-dn { + compatible = "domain-idle-state"; + entry-latency-us = <5000>; + exit-latency-us = <8000>; + min-residency-us = <7000>; + }; }; diff --git a/Documentation/devicetree/bindings/power/renesas,apmu.txt b/Documentation/devicetree/bindings/power/renesas,apmu.txt deleted file mode 100644 index 5f24586c8cf3..000000000000 --- a/Documentation/devicetree/bindings/power/renesas,apmu.txt +++ /dev/null @@ -1,35 +0,0 @@ -DT bindings for the Renesas Advanced Power Management Unit - -Renesas R-Car and RZ/G1 SoCs utilize one or more APMU hardware units -for CPU core power domain control including SMP boot and CPU Hotplug. - -Required properties: - -- compatible: Should be "renesas,<soctype>-apmu", "renesas,apmu" as fallback. - Examples with soctypes are: - - "renesas,r8a7743-apmu" (RZ/G1M) - - "renesas,r8a7744-apmu" (RZ/G1N) - - "renesas,r8a7745-apmu" (RZ/G1E) - - "renesas,r8a77470-apmu" (RZ/G1C) - - "renesas,r8a7790-apmu" (R-Car H2) - - "renesas,r8a7791-apmu" (R-Car M2-W) - - "renesas,r8a7792-apmu" (R-Car V2H) - - "renesas,r8a7793-apmu" (R-Car M2-N) - - "renesas,r8a7794-apmu" (R-Car E2) - -- reg: Base address and length of the I/O registers used by the APMU. - -- cpus: This node contains a list of CPU cores, which should match the order - of CPU cores used by the WUPCR and PSTR registers in the Advanced Power - Management Unit section of the device's datasheet. - - -Example: - -This shows the r8a7791 APMU that can control CPU0 and CPU1. - - apmu@e6152000 { - compatible = "renesas,r8a7791-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0 &cpu1>; - }; diff --git a/Documentation/devicetree/bindings/power/renesas,apmu.yaml b/Documentation/devicetree/bindings/power/renesas,apmu.yaml new file mode 100644 index 000000000000..078b2cb40fe3 --- /dev/null +++ b/Documentation/devicetree/bindings/power/renesas,apmu.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/power/renesas,apmu.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Renesas Advanced Power Management Unit + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + - Magnus Damm <magnus.damm@gmail.com> + +description: + Renesas R-Car Gen2 and RZ/G1 SoCs utilize one or more APMU hardware units for + CPU core power domain control including SMP boot and CPU Hotplug. + +properties: + compatible: + items: + - enum: + - renesas,r8a7743-apmu # RZ/G1M + - renesas,r8a7744-apmu # RZ/G1N + - renesas,r8a7745-apmu # RZ/G1E + - renesas,r8a77470-apmu # RZ/G1C + - renesas,r8a7790-apmu # R-Car H2 + - renesas,r8a7791-apmu # R-Car M2-W + - renesas,r8a7792-apmu # R-Car V2H + - renesas,r8a7793-apmu # R-Car M2-N + - renesas,r8a7794-apmu # R-Car E2 + - const: renesas,apmu + + reg: + maxItems: 1 + + cpus: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + Array of phandles pointing to CPU cores, which should match the order of + CPU cores used by the WUPCR and PSTR registers in the Advanced Power + Management Unit section of the device's datasheet. + +required: + - compatible + - reg + - cpus + +additionalProperties: false + +examples: + - | + apmu@e6152000 { + compatible = "renesas,r8a7791-apmu", "renesas,apmu"; + reg = <0xe6152000 0x188>; + cpus = <&cpu0 &cpu1>; + }; diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt deleted file mode 100644 index acb41fade926..000000000000 --- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt +++ /dev/null @@ -1,62 +0,0 @@ -DT bindings for the Renesas R-Car (RZ/G) System Controller - -== System Controller Node == - -The R-Car (RZ/G) System Controller provides power management for the CPU cores -and various coprocessors. - -Required properties: - - compatible: Must contain exactly one of the following: - - "renesas,r8a7743-sysc" (RZ/G1M) - - "renesas,r8a7744-sysc" (RZ/G1N) - - "renesas,r8a7745-sysc" (RZ/G1E) - - "renesas,r8a77470-sysc" (RZ/G1C) - - "renesas,r8a774a1-sysc" (RZ/G2M) - - "renesas,r8a774b1-sysc" (RZ/G2N) - - "renesas,r8a774c0-sysc" (RZ/G2E) - - "renesas,r8a7779-sysc" (R-Car H1) - - "renesas,r8a7790-sysc" (R-Car H2) - - "renesas,r8a7791-sysc" (R-Car M2-W) - - "renesas,r8a7792-sysc" (R-Car V2H) - - "renesas,r8a7793-sysc" (R-Car M2-N) - - "renesas,r8a7794-sysc" (R-Car E2) - - "renesas,r8a7795-sysc" (R-Car H3) - - "renesas,r8a7796-sysc" (R-Car M3-W) - - "renesas,r8a77961-sysc" (R-Car M3-W+) - - "renesas,r8a77965-sysc" (R-Car M3-N) - - "renesas,r8a77970-sysc" (R-Car V3M) - - "renesas,r8a77980-sysc" (R-Car V3H) - - "renesas,r8a77990-sysc" (R-Car E3) - - "renesas,r8a77995-sysc" (R-Car D3) - - reg: Address start and address range for the device. - - #power-domain-cells: Must be 1. - - -Example: - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7791-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; - - -== PM Domain Consumers == - -Devices residing in a power area must refer to that power area, as documented -by the generic PM domain bindings in -Documentation/devicetree/bindings/power/power_domain.txt. - -Required properties: - - power-domains: A phandle and symbolic PM domain specifier, as defined in - <dt-bindings/power/r8a77*-sysc.h>. - - -Example: - - L2_CA15: cache-controller@0 { - compatible = "cache"; - power-domains = <&sysc R8A7791_PD_CA15_SCU>; - cache-unified; - cache-level = <2>; - }; diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml new file mode 100644 index 000000000000..e59331e1d944 --- /dev/null +++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/power/renesas,rcar-sysc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Renesas R-Car and RZ/G System Controller + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + - Magnus Damm <magnus.damm@gmail.com> + +description: + The R-Car (RZ/G) System Controller provides power management for the CPU + cores and various coprocessors. + +properties: + compatible: + enum: + - renesas,r8a7743-sysc # RZ/G1M + - renesas,r8a7744-sysc # RZ/G1N + - renesas,r8a7745-sysc # RZ/G1E + - renesas,r8a77470-sysc # RZ/G1C + - renesas,r8a774a1-sysc # RZ/G2M + - renesas,r8a774b1-sysc # RZ/G2N + - renesas,r8a774c0-sysc # RZ/G2E + - renesas,r8a7779-sysc # R-Car H1 + - renesas,r8a7790-sysc # R-Car H2 + - renesas,r8a7791-sysc # R-Car M2-W + - renesas,r8a7792-sysc # R-Car V2H + - renesas,r8a7793-sysc # R-Car M2-N + - renesas,r8a7794-sysc # R-Car E2 + - renesas,r8a7795-sysc # R-Car H3 + - renesas,r8a77961-sysc # R-Car M3-W+ + - renesas,r8a77965-sysc # R-Car M3-N + - renesas,r8a7796-sysc # R-Car M3-W + - renesas,r8a77970-sysc # R-Car V3M + - renesas,r8a77980-sysc # R-Car V3H + - renesas,r8a77990-sysc # R-Car E3 + - renesas,r8a77995-sysc # R-Car D3 + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + // System Controller node + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7791-sysc"; + reg = <0xe6180000 0x0200>; + #power-domain-cells = <1>; + }; + + - | + // Power Domain consumers + #include <dt-bindings/power/r8a7791-sysc.h> + + cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A7791_PD_CA15_SCU>; + cache-unified; + cache-level = <2>; + }; diff --git a/Documentation/devicetree/bindings/power/reset/syscon-poweroff.yaml b/Documentation/devicetree/bindings/power/reset/syscon-poweroff.yaml index 520e07e6f21b..3412fe7e1e80 100644 --- a/Documentation/devicetree/bindings/power/reset/syscon-poweroff.yaml +++ b/Documentation/devicetree/bindings/power/reset/syscon-poweroff.yaml @@ -41,6 +41,8 @@ required: - regmap - offset +additionalProperties: false + allOf: - if: not: diff --git a/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml b/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml index d38006b1f1f4..b80772cb9f06 100644 --- a/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml +++ b/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml @@ -41,6 +41,8 @@ required: - regmap - offset +additionalProperties: false + allOf: - if: not: diff --git a/Documentation/devicetree/bindings/power/supply/max77650-charger.yaml b/Documentation/devicetree/bindings/power/supply/max77650-charger.yaml index deef010ec535..62eeddb65aed 100644 --- a/Documentation/devicetree/bindings/power/supply/max77650-charger.yaml +++ b/Documentation/devicetree/bindings/power/supply/max77650-charger.yaml @@ -32,3 +32,6 @@ properties: required: - compatible +additionalProperties: false + +... diff --git a/Documentation/devicetree/bindings/ptp/ptp-idtcm.yaml b/Documentation/devicetree/bindings/ptp/ptp-idtcm.yaml index 9e21b83d717e..239b49fad805 100644 --- a/Documentation/devicetree/bindings/ptp/ptp-idtcm.yaml +++ b/Documentation/devicetree/bindings/ptp/ptp-idtcm.yaml @@ -55,6 +55,8 @@ required: - compatible - reg +additionalProperties: false + examples: - | i2c@1 { diff --git a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.txt b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.txt deleted file mode 100644 index 472bd46ab5a4..000000000000 --- a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.txt +++ /dev/null @@ -1,23 +0,0 @@ -* PWM controlled by ChromeOS EC - -Google's ChromeOS EC PWM is a simple PWM attached to the Embedded Controller -(EC) and controlled via a host-command interface. - -An EC PWM node should be only found as a sub-node of the EC node (see -Documentation/devicetree/bindings/mfd/cros-ec.txt). - -Required properties: -- compatible: Must contain "google,cros-ec-pwm" -- #pwm-cells: Should be 1. The cell specifies the PWM index. - -Example: - cros-ec@0 { - compatible = "google,cros-ec-spi"; - - ... - - cros_ec_pwm: ec-pwm { - compatible = "google,cros-ec-pwm"; - #pwm-cells = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml new file mode 100644 index 000000000000..41ece1d85315 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/google,cros-ec-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PWM controlled by ChromeOS EC + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - '"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>' + +description: | + Google's ChromeOS EC PWM is a simple PWM attached to the Embedded Controller + (EC) and controlled via a host-command interface. + An EC PWM node should be only found as a sub-node of the EC node (see + Documentation/devicetree/bindings/mfd/cros-ec.txt). + +properties: + compatible: + const: google,cros-ec-pwm + "#pwm-cells": + description: The cell specifies the PWM index. + const: 1 + +required: + - compatible + - '#pwm-cells' + +additionalProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + cros-ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0>; + + cros_ec_pwm: ec-pwm { + compatible = "google,cros-ec-pwm"; + #pwm-cells = <1>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pwm/iqs620a-pwm.yaml b/Documentation/devicetree/bindings/pwm/iqs620a-pwm.yaml new file mode 100644 index 000000000000..1d7c27be50da --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/iqs620a-pwm.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/iqs620a-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Azoteq IQS620A PWM Generator + +maintainers: + - Jeff LaBundy <jeff@labundy.com> + +description: | + The Azoteq IQS620A multi-function sensor generates a fixed-frequency PWM + output represented by a "pwm" child node from the parent MFD driver. See + Documentation/devicetree/bindings/mfd/iqs62x.yaml for further details as + well as an example. + +properties: + compatible: + enum: + - azoteq,iqs620a-pwm + + "#pwm-cells": + const: 2 + +required: + - compatible + - "#pwm-cells" + +additionalProperties: false + +... diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt index 0a69eadf44ce..74c41e34c3b6 100644 --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt @@ -9,6 +9,7 @@ Required properties: - "nvidia,tegra132-pwm", "nvidia,tegra20-pwm": for Tegra132 - "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210 - "nvidia,tegra186-pwm": for Tegra186 + - "nvidia,tegra194-pwm": for Tegra194 - reg: physical base address and length of the controller's registers - #pwm-cells: should be 2. See pwm.yaml in this directory for a description of the cells format. diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt index 95536d83c5f2..29adff59c479 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt @@ -19,10 +19,15 @@ Required properties: - "pwm1-8": the eight per PWM clocks for mt2712 - "pwm1-6": the six per PWM clocks for mt7622 - "pwm1-5": the five per PWM clocks for mt7623 + - "pwm1" : the PWM1 clock for mt7629 - pinctrl-names: Must contain a "default" entry. - pinctrl-0: One property must exist for each entry in pinctrl-names. See pinctrl/pinctrl-bindings.txt for details of the property values. +Optional properties: +- assigned-clocks: Reference to the PWM clock entries. +- assigned-clock-parents: The phandle of the parent clock of PWM clock. + Example: pwm0: pwm@11006000 { compatible = "mediatek,mt7623-pwm"; diff --git a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml index 4969a954993c..4bf62a3d5bba 100644 --- a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml @@ -19,6 +19,10 @@ properties: - renesas,tpu-r8a7744 # RZ/G1N - renesas,tpu-r8a7745 # RZ/G1E - renesas,tpu-r8a7790 # R-Car H2 + - renesas,tpu-r8a7791 # R-Car M2-W + - renesas,tpu-r8a7792 # R-Car V2H + - renesas,tpu-r8a7793 # R-Car M2-N + - renesas,tpu-r8a7794 # R-Car E2 - renesas,tpu-r8a7795 # R-Car H3 - renesas,tpu-r8a7796 # R-Car M3-W - renesas,tpu-r8a77965 # R-Car M3-N diff --git a/Documentation/devicetree/bindings/regulator/max77650-regulator.yaml b/Documentation/devicetree/bindings/regulator/max77650-regulator.yaml index 7d724159f890..ce0a4021ae7f 100644 --- a/Documentation/devicetree/bindings/regulator/max77650-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/max77650-regulator.yaml @@ -24,8 +24,11 @@ properties: const: maxim,max77650-regulator patternProperties: - "^regulator@[0-3]$": + "^regulator-(ldo|sbb[0-2])$": $ref: "regulator.yaml#" required: - compatible +additionalProperties: false + +... diff --git a/Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.txt b/Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.txt deleted file mode 100644 index cbce62c22b60..000000000000 --- a/Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.txt +++ /dev/null @@ -1,162 +0,0 @@ -ROHM BD71837 and BD71847 Power Management Integrated Circuit regulator bindings - -Required properties: - - regulator-name: should be "buck1", ..., "buck8" and "ldo1", ..., "ldo7" for - BD71837. For BD71847 names should be "buck1", ..., "buck6" - and "ldo1", ..., "ldo6" - -List of regulators provided by this controller. BD71837 regulators node -should be sub node of the BD71837 MFD node. See BD71837 MFD bindings at -Documentation/devicetree/bindings/mfd/rohm,bd71837-pmic.txt -Regulator nodes should be named to BUCK_<number> and LDO_<number>. The -definition for each of these nodes is defined using the standard -binding for regulators at -Documentation/devicetree/bindings/regulator/regulator.txt. -Note that if BD71837 starts at RUN state you probably want to use -regulator-boot-on at least for BUCK6 and BUCK7 so that those are not -disabled by driver at startup. LDO5 and LDO6 are supplied by those and -if they are disabled at startup the voltage monitoring for LDO5/LDO6 will -cause PMIC to reset. - -The valid names for BD71837 regulator nodes are: -BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, BUCK6, BUCK7, BUCK8 -LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7 - -The valid names for BD71847 regulator nodes are: -BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, BUCK6 -LDO1, LDO2, LDO3, LDO4, LDO5, LDO6 - -Optional properties: -- rohm,dvs-run-voltage : PMIC default "RUN" state voltage in uV. - See below table for bucks which support this. -- rohm,dvs-idle-voltage : PMIC default "IDLE" state voltage in uV. - See below table for bucks which support this. -- rohm,dvs-suspend-voltage : PMIC default "SUSPEND" state voltage in uV. - See below table for bucks which support this. -- Any optional property defined in bindings/regulator/regulator.txt - -Supported default DVS states: - -BD71837: -buck | dvs-run-voltage | dvs-idle-voltage | dvs-suspend-voltage ------------------------------------------------------------------------------ -1 | supported | supported | supported ----------------------------------------------------------------------------- -2 | supported | supported | not supported ----------------------------------------------------------------------------- -3 | supported | not supported | not supported ----------------------------------------------------------------------------- -4 | supported | not supported | not supported ----------------------------------------------------------------------------- -rest | not supported | not supported | not supported - -BD71847: -buck | dvs-run-voltage | dvs-idle-voltage | dvs-suspend-voltage ------------------------------------------------------------------------------ -1 | supported | supported | supported ----------------------------------------------------------------------------- -2 | supported | supported | not supported ----------------------------------------------------------------------------- -rest | not supported | not supported | not supported - -Example: -regulators { - buck1: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <900000>; - rohm,dvs-idle-voltage = <850000>; - rohm,dvs-suspend-voltage = <800000>; - }; - buck2: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - buck3: BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - rohm,dvs-run-voltage = <1000000>; - }; - buck4: BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - rohm,dvs-run-voltage = <1000000>; - }; - buck5: BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - }; - buck6: BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - buck7: BUCK7 { - regulator-name = "buck7"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - }; - buck8: BUCK8 { - regulator-name = "buck8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - }; - - ldo1: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - ldo2: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - }; - ldo3: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - ldo4: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - }; - ldo5: LDO5 { - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - ldo6: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - }; - ldo7_reg: LDO7 { - regulator-name = "ldo7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; -}; - - diff --git a/Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.yaml b/Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.yaml new file mode 100644 index 000000000000..a323b1696eee --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/rohm,bd71837-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ROHM BD71837 Power Management Integrated Circuit regulators + +maintainers: + - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> + +description: | + List of regulators provided by this controller. BD71837 regulators node + should be sub node of the BD71837 MFD node. See BD71837 MFD bindings at + Documentation/devicetree/bindings/mfd/rohm,bd71837-pmic.yaml + Regulator nodes should be named to BUCK_<number> and LDO_<number>. The + definition for each of these nodes is defined using the standard + binding for regulators at + Documentation/devicetree/bindings/regulator/regulator.txt. + Note that if BD71837 starts at RUN state you probably want to use + regulator-boot-on at least for BUCK6 and BUCK7 so that those are not + disabled by driver at startup. LDO5 and LDO6 are supplied by those and + if they are disabled at startup the voltage monitoring for LDO5/LDO6 will + cause PMIC to reset. + +#The valid names for BD71837 regulator nodes are: +#BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, BUCK6, BUCK7, BUCK8 +#LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7 + +patternProperties: + "^LDO[1-7]$": + type: object + allOf: + - $ref: regulator.yaml# + description: + Properties for single LDO regulator. + + properties: + regulator-name: + pattern: "^ldo[1-7]$" + description: + should be "ldo1", ..., "ldo7" + + "^BUCK[1-8]$": + type: object + allOf: + - $ref: regulator.yaml# + description: + Properties for single BUCK regulator. + + properties: + regulator-name: + pattern: "^buck[1-8]$" + description: + should be "buck1", ..., "buck8" + + rohm,dvs-run-voltage: + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + maximum: 1300000 + description: + PMIC default "RUN" state voltage in uV. See below table for + bucks which support this. 0 means disabled. + + rohm,dvs-idle-voltage: + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + maximum: 1300000 + description: + PMIC default "IDLE" state voltage in uV. See below table for + bucks which support this. 0 means disabled. + + rohm,dvs-suspend-voltage: + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + maximum: 1300000 + description: + PMIC default "SUSPEND" state voltage in uV. See below table for + bucks which support this. 0 means disabled. + + # Supported default DVS states: + # + # BD71837: + # buck | dvs-run-voltage | dvs-idle-voltage | dvs-suspend-voltage + # ---------------------------------------------------------------- + # 1 | supported | supported | supported + # ---------------------------------------------------------------- + # 2 | supported | supported | not supported + # ---------------------------------------------------------------- + # 3 | supported | not supported | not supported + # ---------------------------------------------------------------- + # 4 | supported | not supported | not supported + # ---------------------------------------------------------------- + # rest | not supported | not supported | not supported + + + required: + - regulator-name + additionalProperties: false +additionalProperties: false diff --git a/Documentation/devicetree/bindings/regulator/rohm,bd71847-regulator.yaml b/Documentation/devicetree/bindings/regulator/rohm,bd71847-regulator.yaml new file mode 100644 index 000000000000..526fd00bcb16 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/rohm,bd71847-regulator.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/rohm,bd71847-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ROHM BD71847 and BD71850 Power Management Integrated Circuit regulators + +maintainers: + - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> + +description: | + List of regulators provided by this controller. BD71847 regulators node + should be sub node of the BD71847 MFD node. See BD71847 MFD bindings at + Documentation/devicetree/bindings/mfd/rohm,bd71847-pmic.yaml + Regulator nodes should be named to BUCK_<number> and LDO_<number>. The + definition for each of these nodes is defined using the standard + binding for regulators at + Documentation/devicetree/bindings/regulator/regulator.txt. + Note that if BD71847 starts at RUN state you probably want to use + regulator-boot-on at least for BUCK5. LDO6 is supplied by it and it must + not be disabled by driver at startup. If BUCK5 is disabled at startup the + voltage monitoring for LDO5/LDO6 can cause PMIC to reset. + +#The valid names for BD71847 regulator nodes are: +#BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, BUCK6 +#LDO1, LDO2, LDO3, LDO4, LDO5, LDO6 + +patternProperties: + "^LDO[1-6]$": + type: object + allOf: + - $ref: regulator.yaml# + description: + Properties for single LDO regulator. + + properties: + regulator-name: + pattern: "^ldo[1-6]$" + description: + should be "ldo1", ..., "ldo6" + + "^BUCK[1-6]$": + type: object + allOf: + - $ref: regulator.yaml# + description: + Properties for single BUCK regulator. + + properties: + regulator-name: + pattern: "^buck[1-6]$" + description: + should be "buck1", ..., "buck6" + + rohm,dvs-run-voltage: + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + maximum: 1300000 + description: + PMIC default "RUN" state voltage in uV. See below table for + bucks which support this. 0 means disabled. + + rohm,dvs-idle-voltage: + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + maximum: 1300000 + description: + PMIC default "IDLE" state voltage in uV. See below table for + bucks which support this. 0 means disabled. + + rohm,dvs-suspend-voltage: + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + maximum: 1300000 + description: + PMIC default "SUSPEND" state voltage in uV. See below table for + bucks which support this. 0 means disabled. + + # Supported default DVS states: + # + # BD71847: + # buck | dvs-run-voltage | dvs-idle-voltage | dvs-suspend-voltage + # ---------------------------------------------------------------- + # 1 | supported | supported | supported + # ---------------------------------------------------------------- + # 2 | supported | supported | not supported + # ---------------------------------------------------------------- + # rest | not supported | not supported | not supported + + required: + - regulator-name + additionalProperties: false +additionalProperties: false diff --git a/Documentation/devicetree/bindings/regulator/st,stpmic1-regulator.txt b/Documentation/devicetree/bindings/regulator/st,stpmic1-regulator.txt deleted file mode 100644 index 6189df71ea98..000000000000 --- a/Documentation/devicetree/bindings/regulator/st,stpmic1-regulator.txt +++ /dev/null @@ -1,64 +0,0 @@ -STMicroelectronics STPMIC1 Voltage regulators - -Regulator Nodes are optional depending on needs. - -Available Regulators in STPMIC1 device are: - - buck1 for Buck BUCK1 - - buck2 for Buck BUCK2 - - buck3 for Buck BUCK3 - - buck4 for Buck BUCK4 - - ldo1 for LDO LDO1 - - ldo2 for LDO LDO2 - - ldo3 for LDO LDO3 - - ldo4 for LDO LDO4 - - ldo5 for LDO LDO5 - - ldo6 for LDO LDO6 - - vref_ddr for LDO Vref DDR - - boost for Buck BOOST - - pwr_sw1 for VBUS_OTG switch - - pwr_sw2 for SW_OUT switch - -Switches are fixed voltage regulators with only enable/disable capability. - -Optional properties: -- st,mask-reset: mask reset for this regulator: the regulator configuration - is maintained during pmic reset. -- regulator-over-current-protection: - if set, all regulators are switched off in case of over-current detection - on this regulator, - if not set, the driver only sends an over-current event. -- interrupts: index of current limit detection interrupt -- <regulator>-supply: phandle to the parent supply/regulator node - each regulator supply can be described except vref_ddr. -- regulator-active-discharge: can be used on pwr_sw1 and pwr_sw2. - -Example: -regulators { - compatible = "st,stpmic1-regulators"; - - ldo6-supply = <&v3v3>; - - vdd_core: buck1 { - regulator-name = "vdd_core"; - interrupts = <IT_CURLIM_BUCK1 0>; - st,mask-reset; - regulator-pull-down; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1200000>; - }; - - v3v3: buck4 { - regulator-name = "v3v3"; - interrupts = <IT_CURLIM_BUCK4 0>; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - v1v8: ldo6 { - regulator-name = "v1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-over-current-protection; - }; -}; diff --git a/Documentation/devicetree/bindings/remoteproc/ti,omap-remoteproc.yaml b/Documentation/devicetree/bindings/remoteproc/ti,omap-remoteproc.yaml new file mode 100644 index 000000000000..084960a8f17a --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/ti,omap-remoteproc.yaml @@ -0,0 +1,324 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OMAP4+ Remoteproc Devices + +maintainers: + - Suman Anna <s-anna@ti.com> + +description: + The OMAP family of SoCs usually have one or more slave processor sub-systems + that are used to offload some of the processor-intensive tasks, or to manage + other hardware accelerators, for achieving various system level goals. + + The processor cores in the sub-system are usually behind an IOMMU, and may + contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2 + caches, an Interrupt Controller, a Cache Controller etc. + + The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor + sub-system. The DSP processor sub-system can contain any of the TI's C64x, + C66x or C67x family of DSP cores as the main execution unit. The IPU processor + sub-system usually contains either a Dual-Core Cortex-M3 or Dual-Core + Cortex-M4 processors. + + Each remote processor sub-system is represented as a single DT node. Each node + has a number of required or optional properties that enable the OS running on + the host processor (MPU) to perform the device management of the remote + processor and to communicate with the remote processor. The various properties + can be classified as constant or variable. The constant properties are + dictated by the SoC and does not change from one board to another having the + same SoC. Examples of constant properties include 'iommus', 'reg'. The + variable properties are dictated by the system integration aspects such as + memory on the board, or configuration used within the corresponding firmware + image. Examples of variable properties include 'mboxes', 'memory-region', + 'timers', 'watchdog-timers' etc. + +properties: + compatible: + enum: + - ti,omap4-dsp + - ti,omap5-dsp + - ti,dra7-dsp + - ti,omap4-ipu + - ti,omap5-ipu + - ti,dra7-ipu + + iommus: + minItems: 1 + maxItems: 2 + description: | + phandles to OMAP IOMMU nodes, that need to be programmed + for this remote processor to access any external RAM memory or + other peripheral device address spaces. This property usually + has only a single phandle. Multiple phandles are used only in + cases where the sub-system has different ports for different + sub-modules within the processor sub-system (eg: DRA7 DSPs), + and need the same programming in both the MMUs. + + mboxes: + minItems: 1 + maxItems: 2 + description: | + OMAP Mailbox specifier denoting the sub-mailbox, to be used for + communication with the remote processor. The specifier format is + as per the bindings, + Documentation/devicetree/bindings/mailbox/omap-mailbox.txt + This property should match with the sub-mailbox node used in + the firmware image. + + clocks: + description: | + Main functional clock for the remote processor + + resets: + description: | + Reset handles for the remote processor + + firmware-name: + description: | + Default name of the firmware to load to the remote processor. + +# Optional properties: +# -------------------- +# Some of these properties are mandatory on some SoCs, and some are optional +# depending on the configuration of the firmware image to be executed on the +# remote processor. The conditions are mentioned for each property. +# +# The following are the optional properties: + + memory-region: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + phandle to the reserved memory node to be associated + with the remoteproc device. The reserved memory node + can be a CMA memory node, and should be defined as + per the bindings, + Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt + + reg: + description: | + Address space for any remoteproc memories present on + the SoC. Should contain an entry for each value in + 'reg-names'. These are mandatory for all DSP and IPU + processors that have them (OMAP4/OMAP5 DSPs do not have + any RAMs) + + reg-names: + description: | + Required names for each of the address spaces defined in + the 'reg' property. Expects the names from the following + list, in the specified order, each representing the corresponding + internal RAM memory region. + minItems: 1 + maxItems: 3 + items: + - const: l2ram + - const: l1pram + - const: l1dram + + ti,bootreg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + Should be a triple of the phandle to the System Control + Configuration region that contains the boot address + register, the register offset of the boot address + register within the System Control module, and the bit + shift within the register. This property is required for + all the DSP instances on OMAP4, OMAP5 and DRA7xx SoCs. + + ti,autosuspend-delay-ms: + description: | + Custom autosuspend delay for the remoteproc in milliseconds. + Recommended values is preferable to be in the order of couple + of seconds. A negative value can also be used to disable the + autosuspend behavior. + + ti,timers: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + One or more phandles to OMAP DMTimer nodes, that serve + as System/Tick timers for the OS running on the remote + processors. This will usually be a single timer if the + processor sub-system is running in SMP mode, or one per + core in the processor sub-system. This can also be used + to reserve specific timers to be dedicated to the + remote processors. + + This property is mandatory on remote processors requiring + external tick wakeup, and to support Power Management + features. The timers to be used should match with the + timers used in the firmware image. + + ti,watchdog-timers: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + One or more phandles to OMAP DMTimer nodes, used to + serve as Watchdog timers for the processor cores. This + will usually be one per executing processor core, even + if the processor sub-system is running a SMP OS. + + The timers to be used should match with the watchdog + timers used in the firmware image. + +if: + properties: + compatible: + enum: + - ti,dra7-dsp +then: + properties: + reg: + minItems: 3 + maxItems: 3 + required: + - reg + - reg-names + - ti,bootreg + +else: + if: + properties: + compatible: + enum: + - ti,omap4-ipu + - ti,omap5-ipu + - ti,dra7-ipu + then: + properties: + reg: + minItems: 1 + maxItems: 1 + ti,bootreg: false + required: + - reg + - reg-names + + else: + properties: + reg: false + required: + - ti,bootreg + +required: + - compatible + - iommus + - mboxes + - clocks + - resets + - firmware-name + +additionalProperties: false + +examples: + - | + + //Example 1: OMAP4 DSP + + /* DSP Reserved Memory node */ + #include <dt-bindings/clock/omap4.h> + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + + dsp_memory_region: dsp-memory@98000000 { + compatible = "shared-dma-pool"; + reg = <0x98000000 0x800000>; + reusable; + }; + }; + + /* DSP node */ + ocp { + dsp: dsp { + compatible = "ti,omap4-dsp"; + ti,bootreg = <&scm_conf 0x304 0>; + iommus = <&mmu_dsp>; + mboxes = <&mailbox &mbox_dsp>; + memory-region = <&dsp_memory_region>; + ti,timers = <&timer5>; + ti,watchdog-timers = <&timer6>; + clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>; + resets = <&prm_tesla 0>, <&prm_tesla 1>; + firmware-name = "omap4-dsp-fw.xe64T"; + }; + }; + + - |+ + + //Example 2: OMAP5 IPU + + /* IPU Reserved Memory node */ + #include <dt-bindings/clock/omap5.h> + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + ipu_memory_region: ipu-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0 0x95800000 0 0x3800000>; + reusable; + }; + }; + + /* IPU node */ + ocp { + #address-cells = <1>; + #size-cells = <1>; + + ipu: ipu@55020000 { + compatible = "ti,omap5-ipu"; + reg = <0x55020000 0x10000>; + reg-names = "l2ram"; + iommus = <&mmu_ipu>; + mboxes = <&mailbox &mbox_ipu>; + memory-region = <&ipu_memory_region>; + ti,timers = <&timer3>, <&timer4>; + ti,watchdog-timers = <&timer9>, <&timer11>; + clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>; + resets = <&prm_core 2>; + firmware-name = "omap5-ipu-fw.xem4"; + }; + }; + + - |+ + + //Example 3: DRA7xx/AM57xx DSP + + /* DSP1 Reserved Memory node */ + #include <dt-bindings/clock/dra7.h> + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + }; + }; + + /* DSP1 node */ + ocp { + #address-cells = <1>; + #size-cells = <1>; + + dsp1: dsp@40800000 { + compatible = "ti,dra7-dsp"; + reg = <0x40800000 0x48000>, + <0x40e00000 0x8000>, + <0x40f00000 0x8000>; + reg-names = "l2ram", "l1pram", "l1dram"; + ti,bootreg = <&scm_conf 0x55c 0>; + iommus = <&mmu0_dsp1>, <&mmu1_dsp1>; + mboxes = <&mailbox5 &mbox_dsp1_ipc3x>; + memory-region = <&dsp1_memory_region>; + ti,timers = <&timer5>; + ti,watchdog-timers = <&timer10>; + resets = <&prm_dsp1 0>; + clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; + firmware-name = "dra7-dsp1-fw.xe66"; + }; + }; diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml index b3f57d81f007..92922d3afd14 100644 --- a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml +++ b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml @@ -29,6 +29,8 @@ required: - reg - "#reset-cells" +additionalProperties: false + examples: - | reset-controller@c884404 { diff --git a/Documentation/devicetree/bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml b/Documentation/devicetree/bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml index 411bd76f1b64..512a33bdb208 100644 --- a/Documentation/devicetree/bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml +++ b/Documentation/devicetree/bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml @@ -28,6 +28,8 @@ required: - reg - "#reset-cells" +additionalProperties: false + examples: - | reset-controller@8b2c800 { diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt b/Documentation/devicetree/bindings/reset/renesas,rst.txt deleted file mode 100644 index de7f06ccd003..000000000000 --- a/Documentation/devicetree/bindings/reset/renesas,rst.txt +++ /dev/null @@ -1,48 +0,0 @@ -DT bindings for the Renesas R-Car and RZ/G Reset Controllers - -The R-Car and RZ/G Reset Controllers provide reset control, and implement the -following functions: - - Latching of the levels on mode pins when PRESET# is negated, - - Mode monitoring register, - - Reset control of peripheral devices (on R-Car Gen1), - - Watchdog timer (on R-Car Gen1), - - Register-based reset control and boot address registers for the various CPU - cores (on R-Car Gen2 and Gen3, and on RZ/G). - - -Required properties: - - compatible: Should be - - "renesas,<soctype>-reset-wdt" for R-Car Gen1, - - "renesas,<soctype>-rst" for R-Car Gen2 and Gen3, and RZ/G - Examples with soctypes are: - - "renesas,r8a7743-rst" (RZ/G1M) - - "renesas,r8a7744-rst" (RZ/G1N) - - "renesas,r8a7745-rst" (RZ/G1E) - - "renesas,r8a77470-rst" (RZ/G1C) - - "renesas,r8a774a1-rst" (RZ/G2M) - - "renesas,r8a774b1-rst" (RZ/G2N) - - "renesas,r8a774c0-rst" (RZ/G2E) - - "renesas,r8a7778-reset-wdt" (R-Car M1A) - - "renesas,r8a7779-reset-wdt" (R-Car H1) - - "renesas,r8a7790-rst" (R-Car H2) - - "renesas,r8a7791-rst" (R-Car M2-W) - - "renesas,r8a7792-rst" (R-Car V2H - - "renesas,r8a7793-rst" (R-Car M2-N) - - "renesas,r8a7794-rst" (R-Car E2) - - "renesas,r8a7795-rst" (R-Car H3) - - "renesas,r8a7796-rst" (R-Car M3-W) - - "renesas,r8a77961-rst" (R-Car M3-W+) - - "renesas,r8a77965-rst" (R-Car M3-N) - - "renesas,r8a77970-rst" (R-Car V3M) - - "renesas,r8a77980-rst" (R-Car V3H) - - "renesas,r8a77990-rst" (R-Car E3) - - "renesas,r8a77995-rst" (R-Car D3) - - reg: Address start and address range for the device. - - -Example: - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7795-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.yaml b/Documentation/devicetree/bindings/reset/renesas,rst.yaml new file mode 100644 index 000000000000..b5de1d196a13 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/renesas,rst.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/reset/renesas,rst.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Renesas R-Car and RZ/G Reset Controller + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + - Magnus Damm <magnus.damm@gmail.com> + +description: | + The R-Car and RZ/G Reset Controllers provide reset control, and implement the + following functions: + - Latching of the levels on mode pins when PRESET# is negated, + - Mode monitoring register, + - Reset control of peripheral devices (on R-Car Gen1), + - Watchdog timer (on R-Car Gen1), + - Register-based reset control and boot address registers for the various + CPU cores (on R-Car Gen2 and Gen3, and on RZ/G). + +properties: + compatible: + enum: + - renesas,r8a7743-rst # RZ/G1M + - renesas,r8a7744-rst # RZ/G1N + - renesas,r8a7745-rst # RZ/G1E + - renesas,r8a77470-rst # RZ/G1C + - renesas,r8a774a1-rst # RZ/G2M + - renesas,r8a774b1-rst # RZ/G2N + - renesas,r8a774c0-rst # RZ/G2E + - renesas,r8a7778-reset-wdt # R-Car M1A + - renesas,r8a7779-reset-wdt # R-Car H1 + - renesas,r8a7790-rst # R-Car H2 + - renesas,r8a7791-rst # R-Car M2-W + - renesas,r8a7792-rst # R-Car V2H + - renesas,r8a7793-rst # R-Car M2-N + - renesas,r8a7794-rst # R-Car E2 + - renesas,r8a7795-rst # R-Car H3 + - renesas,r8a7796-rst # R-Car M3-W + - renesas,r8a77961-rst # R-Car M3-W+ + - renesas,r8a77965-rst # R-Car M3-N + - renesas,r8a77970-rst # R-Car V3M + - renesas,r8a77980-rst # R-Car V3H + - renesas,r8a77990-rst # R-Car E3 + - renesas,r8a77995-rst # R-Car D3 + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7795-rst"; + reg = <0xe6160000 0x0200>; + }; diff --git a/Documentation/devicetree/bindings/rng/amlogic,meson-rng.yaml b/Documentation/devicetree/bindings/rng/amlogic,meson-rng.yaml index a9ff3cb35c5e..444be32a8a29 100644 --- a/Documentation/devicetree/bindings/rng/amlogic,meson-rng.yaml +++ b/Documentation/devicetree/bindings/rng/amlogic,meson-rng.yaml @@ -29,6 +29,8 @@ required: - compatible - reg +additionalProperties: false + examples: - | rng@c8834000 { diff --git a/Documentation/devicetree/bindings/rng/brcm,bcm2835.txt b/Documentation/devicetree/bindings/rng/brcm,bcm2835.txt deleted file mode 100644 index aaac7975f61c..000000000000 --- a/Documentation/devicetree/bindings/rng/brcm,bcm2835.txt +++ /dev/null @@ -1,40 +0,0 @@ -BCM2835/6368 Random number generator - -Required properties: - -- compatible : should be one of - "brcm,bcm2835-rng" - "brcm,bcm-nsp-rng" - "brcm,bcm5301x-rng" or - "brcm,bcm6368-rng" -- reg : Specifies base physical address and size of the registers. - -Optional properties: - -- clocks : phandle to clock-controller plus clock-specifier pair -- clock-names : "ipsec" as a clock name - -Optional properties: - -- interrupts: specify the interrupt for the RNG block - -Example: - -rng { - compatible = "brcm,bcm2835-rng"; - reg = <0x7e104000 0x10>; - interrupts = <2 29>; -}; - -rng@18033000 { - compatible = "brcm,bcm-nsp-rng"; - reg = <0x18033000 0x14>; -}; - -random: rng@10004180 { - compatible = "brcm,bcm6368-rng"; - reg = <0x10004180 0x14>; - - clocks = <&periph_clk 18>; - clock-names = "ipsec"; -}; diff --git a/Documentation/devicetree/bindings/rng/brcm,bcm2835.yaml b/Documentation/devicetree/bindings/rng/brcm,bcm2835.yaml new file mode 100644 index 000000000000..c147900f9041 --- /dev/null +++ b/Documentation/devicetree/bindings/rng/brcm,bcm2835.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rng/brcm,bcm2835.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: BCM2835/6368 Random number generator + +maintainers: + - Stefan Wahren <stefan.wahren@i2se.com> + - Florian Fainelli <f.fainelli@gmail.com> + - Herbert Xu <herbert@gondor.apana.org.au> + +properties: + compatible: + enum: + - brcm,bcm2835-rng + - brcm,bcm-nsp-rng + - brcm,bcm5301x-rng + - brcm,bcm6368-rng + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: ipsec + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + rng@7e104000 { + compatible = "brcm,bcm2835-rng"; + reg = <0x7e104000 0x10>; + interrupts = <2 29>; + }; + + - | + rng@18033000 { + compatible = "brcm,bcm-nsp-rng"; + reg = <0x18033000 0x14>; + }; + + - | + rng@10004180 { + compatible = "brcm,bcm6368-rng"; + reg = <0x10004180 0x14>; + + clocks = <&periph_clk 18>; + clock-names = "ipsec"; + }; diff --git a/Documentation/devicetree/bindings/rtc/ingenic,jz4740-rtc.txt b/Documentation/devicetree/bindings/rtc/ingenic,jz4740-rtc.txt deleted file mode 100644 index 41c7ae18fd7b..000000000000 --- a/Documentation/devicetree/bindings/rtc/ingenic,jz4740-rtc.txt +++ /dev/null @@ -1,37 +0,0 @@ -JZ4740 and similar SoCs real-time clock driver - -Required properties: - -- compatible: One of: - - "ingenic,jz4740-rtc" - for use with the JZ4740 SoC - - "ingenic,jz4780-rtc" - for use with the JZ4780 SoC -- reg: Address range of rtc register set -- interrupts: IRQ number for the alarm interrupt -- clocks: phandle to the "rtc" clock -- clock-names: must be "rtc" - -Optional properties: -- system-power-controller: To use this component as the - system power controller -- reset-pin-assert-time-ms: Reset pin low-level assertion - time after wakeup (default 60ms; range 0-125ms if RTC clock - at 32 kHz) -- min-wakeup-pin-assert-time-ms: Minimum wakeup pin assertion - time (default 100ms; range 0-2s if RTC clock at 32 kHz) - -Example: - -rtc@10003000 { - compatible = "ingenic,jz4740-rtc"; - reg = <0x10003000 0x40>; - - interrupt-parent = <&intc>; - interrupts = <32>; - - clocks = <&rtc_clock>; - clock-names = "rtc"; - - system-power-controller; - reset-pin-assert-time-ms = <60>; - min-wakeup-pin-assert-time-ms = <100>; -}; diff --git a/Documentation/devicetree/bindings/rtc/ingenic,rtc.yaml b/Documentation/devicetree/bindings/rtc/ingenic,rtc.yaml new file mode 100644 index 000000000000..4206bf8a2469 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/ingenic,rtc.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/ingenic,rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic SoCs Real-Time Clock DT bindings + +maintainers: + - Paul Cercueil <paul@crapouillou.net> + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + oneOf: + - enum: + - ingenic,jz4740-rtc + - ingenic,jz4760-rtc + - items: + - const: ingenic,jz4725b-rtc + - const: ingenic,jz4740-rtc + - items: + - enum: + - ingenic,jz4770-rtc + - ingenic,jz4780-rtc + - const: ingenic,jz4760-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: rtc + + system-power-controller: + description: | + Indicates that the RTC is responsible for powering OFF + the system. + type: boolean + + ingenic,reset-pin-assert-time-ms: + minimum: 0 + maximum: 125 + default: 60 + description: | + Reset pin low-level assertion time after wakeup + (assuming RTC clock at 32 kHz) + + ingenic,min-wakeup-pin-assert-time-ms: + minimum: 0 + maximum: 2000 + default: 100 + description: | + Minimum wakeup pin assertion time + (assuming RTC clock at 32 kHz) + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +examples: + - | + #include <dt-bindings/clock/jz4740-cgu.h> + rtc_dev: rtc@10003000 { + compatible = "ingenic,jz4740-rtc"; + reg = <0x10003000 0x40>; + + interrupt-parent = <&intc>; + interrupts = <15>; + + clocks = <&cgu JZ4740_CLK_RTC>; + clock-names = "rtc"; + }; diff --git a/Documentation/devicetree/bindings/rtc/renesas,sh-rtc.yaml b/Documentation/devicetree/bindings/rtc/renesas,sh-rtc.yaml index dcff573cbdb1..b95cb017f469 100644 --- a/Documentation/devicetree/bindings/rtc/renesas,sh-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/renesas,sh-rtc.yaml @@ -51,6 +51,8 @@ required: - clocks - clock-names +additionalProperties: false + examples: - | #include <dt-bindings/clock/r7s72100-clock.h> diff --git a/Documentation/devicetree/bindings/rtc/rtc-mt2712.txt b/Documentation/devicetree/bindings/rtc/rtc-mt2712.txt new file mode 100644 index 000000000000..c33d87e5e753 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/rtc-mt2712.txt @@ -0,0 +1,14 @@ +Device-Tree bindings for MediaTek SoC based RTC + +Required properties: +- compatible : Should be "mediatek,mt2712-rtc" : for MT2712 SoC +- reg : Specifies base physical address and size of the registers; +- interrupts : Should contain the interrupt for RTC alarm; + +Example: + +rtc: rtc@10011000 { + compatible = "mediatek,mt2712-rtc"; + reg = <0 0x10011000 0 0x1000>; + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_LOW>; +}; diff --git a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml index 0a54296d7218..48c6cafca90c 100644 --- a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml @@ -111,6 +111,8 @@ required: - clocks - interrupts +additionalProperties: false + examples: - | #include <dt-bindings/mfd/stm32f4-rcc.h> diff --git a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml index 214fe8beddc3..d4178ab0d675 100644 --- a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml +++ b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml @@ -62,6 +62,8 @@ required: - clocks - clock-names +additionalProperties: false + examples: - | serial@84c0 { diff --git a/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt b/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt index c8d677f9491f..9582fc2279ed 100644 --- a/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt +++ b/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt @@ -19,7 +19,7 @@ Optional properties: the transceiver is actually CTS_B, not RTS_B. CTS_B is always output, and RTS_B is input, regardless of dte-mode. -Please check Documentation/devicetree/bindings/serial/serial.txt +Please check Documentation/devicetree/bindings/serial/serial.yaml for the complete list of generic properties. Note: Each uart controller should have an alias correctly numbered diff --git a/Documentation/devicetree/bindings/serial/renesas,hscif.yaml b/Documentation/devicetree/bindings/serial/renesas,hscif.yaml new file mode 100644 index 000000000000..91101521ef07 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/renesas,hscif.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/serial/renesas,hscif.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Renesas High Speed Serial Communication Interface with FIFO (HSCIF) + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,hscif-r8a7778 # R-Car M1 + - renesas,hscif-r8a7779 # R-Car H1 + - const: renesas,rcar-gen1-hscif # R-Car Gen1 + - const: renesas,hscif # generic HSCIF compatible UART + + - items: + - enum: + - renesas,hscif-r8a7743 # RZ/G1M + - renesas,hscif-r8a7744 # RZ/G1N + - renesas,hscif-r8a7745 # RZ/G1E + - renesas,hscif-r8a77470 # RZ/G1C + - renesas,hscif-r8a7790 # R-Car H2 + - renesas,hscif-r8a7791 # R-Car M2-W + - renesas,hscif-r8a7792 # R-Car V2H + - renesas,hscif-r8a7793 # R-Car M2-N + - renesas,hscif-r8a7794 # R-Car E2 + - const: renesas,rcar-gen2-hscif # R-Car Gen2 and RZ/G1 + - const: renesas,hscif # generic HSCIF compatible UART + + - items: + - enum: + - renesas,hscif-r8a774a1 # RZ/G2M + - renesas,hscif-r8a774b1 # RZ/G2N + - renesas,hscif-r8a774c0 # RZ/G2E + - renesas,hscif-r8a7795 # R-Car H3 + - renesas,hscif-r8a7796 # R-Car M3-W + - renesas,hscif-r8a77961 # R-Car M3-W+ + - renesas,hscif-r8a77965 # R-Car M3-N + - renesas,hscif-r8a77970 # R-Car V3M + - renesas,hscif-r8a77980 # R-Car V3H + - renesas,hscif-r8a77990 # R-Car E3 + - renesas,hscif-r8a77995 # R-Car D3 + - const: renesas,rcar-gen3-hscif # R-Car Gen3 and RZ/G2 + - const: renesas,hscif # generic HSCIF compatible UART + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + items: + enum: + - fck # UART functional clock + - hsck # optional external clock input + - brg_int # optional internal clock source for BRG frequency divider + - scif_clk # optional external clock source for BRG frequency divider + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + dmas: + description: + Must contain a list of pairs of references to DMA specifiers, one for + transmission, and one for reception. + + dma-names: + minItems: 2 + maxItems: 4 + items: + enum: + - tx + - rx + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + +if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen2-hscif + - renesas,rcar-gen3-hscif +then: + required: + - resets + +examples: + - | + #include <dt-bindings/clock/r8a7795-cpg-mssr.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/r8a7795-sysc.h> + aliases { + serial1 = &hscif1; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a7795", "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0xe6550000 96>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 519>, <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 519>; + uart-has-rtscts; + }; diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt deleted file mode 100644 index a5edf4b70c7a..000000000000 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ /dev/null @@ -1,150 +0,0 @@ -* Renesas SH-Mobile Serial Communication Interface - -Required properties: - - - compatible: Must contain one or more of the following: - - - "renesas,scif-r7s72100" for R7S72100 (RZ/A1H) SCIF compatible UART. - - "renesas,scif-r7s9210" for R7S9210 (RZ/A2) SCIF compatible UART. - - "renesas,scifa-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFA compatible UART. - - "renesas,scifb-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFB compatible UART. - - "renesas,scifa-r8a7740" for R8A7740 (R-Mobile A1) SCIFA compatible UART. - - "renesas,scifb-r8a7740" for R8A7740 (R-Mobile A1) SCIFB compatible UART. - - "renesas,scif-r8a7743" for R8A7743 (RZ/G1M) SCIF compatible UART. - - "renesas,scifa-r8a7743" for R8A7743 (RZ/G1M) SCIFA compatible UART. - - "renesas,scifb-r8a7743" for R8A7743 (RZ/G1M) SCIFB compatible UART. - - "renesas,hscif-r8a7743" for R8A7743 (RZ/G1M) HSCIF compatible UART. - - "renesas,scif-r8a7744" for R8A7744 (RZ/G1N) SCIF compatible UART. - - "renesas,scifa-r8a7744" for R8A7744 (RZ/G1N) SCIFA compatible UART. - - "renesas,scifb-r8a7744" for R8A7744 (RZ/G1N) SCIFB compatible UART. - - "renesas,hscif-r8a7744" for R8A7744 (RZ/G1N) HSCIF compatible UART. - - "renesas,scif-r8a7745" for R8A7745 (RZ/G1E) SCIF compatible UART. - - "renesas,scifa-r8a7745" for R8A7745 (RZ/G1E) SCIFA compatible UART. - - "renesas,scifb-r8a7745" for R8A7745 (RZ/G1E) SCIFB compatible UART. - - "renesas,hscif-r8a7745" for R8A7745 (RZ/G1E) HSCIF compatible UART. - - "renesas,scif-r8a77470" for R8A77470 (RZ/G1C) SCIF compatible UART. - - "renesas,hscif-r8a77470" for R8A77470 (RZ/G1C) HSCIF compatible UART. - - "renesas,scif-r8a774a1" for R8A774A1 (RZ/G2M) SCIF compatible UART. - - "renesas,hscif-r8a774a1" for R8A774A1 (RZ/G2M) HSCIF compatible UART. - - "renesas,scif-r8a774b1" for R8A774B1 (RZ/G2N) SCIF compatible UART. - - "renesas,hscif-r8a774b1" for R8A774B1 (RZ/G2N) HSCIF compatible UART. - - "renesas,scif-r8a774c0" for R8A774C0 (RZ/G2E) SCIF compatible UART. - - "renesas,hscif-r8a774c0" for R8A774C0 (RZ/G2E) HSCIF compatible UART. - - "renesas,scif-r8a7778" for R8A7778 (R-Car M1) SCIF compatible UART. - - "renesas,hscif-r8a7778" for R8A7778 (R-Car M1) HSCIF compatible UART. - - "renesas,scif-r8a7779" for R8A7779 (R-Car H1) SCIF compatible UART. - - "renesas,hscif-r8a7779" for R8A7779 (R-Car H1) HSCIF compatible UART. - - "renesas,scif-r8a7790" for R8A7790 (R-Car H2) SCIF compatible UART. - - "renesas,scifa-r8a7790" for R8A7790 (R-Car H2) SCIFA compatible UART. - - "renesas,scifb-r8a7790" for R8A7790 (R-Car H2) SCIFB compatible UART. - - "renesas,hscif-r8a7790" for R8A7790 (R-Car H2) HSCIF compatible UART. - - "renesas,scif-r8a7791" for R8A7791 (R-Car M2-W) SCIF compatible UART. - - "renesas,scifa-r8a7791" for R8A7791 (R-Car M2-W) SCIFA compatible UART. - - "renesas,scifb-r8a7791" for R8A7791 (R-Car M2-W) SCIFB compatible UART. - - "renesas,hscif-r8a7791" for R8A7791 (R-Car M2-W) HSCIF compatible UART. - - "renesas,scif-r8a7792" for R8A7792 (R-Car V2H) SCIF compatible UART. - - "renesas,hscif-r8a7792" for R8A7792 (R-Car V2H) HSCIF compatible UART. - - "renesas,scif-r8a7793" for R8A7793 (R-Car M2-N) SCIF compatible UART. - - "renesas,scifa-r8a7793" for R8A7793 (R-Car M2-N) SCIFA compatible UART. - - "renesas,scifb-r8a7793" for R8A7793 (R-Car M2-N) SCIFB compatible UART. - - "renesas,hscif-r8a7793" for R8A7793 (R-Car M2-N) HSCIF compatible UART. - - "renesas,scif-r8a7794" for R8A7794 (R-Car E2) SCIF compatible UART. - - "renesas,scifa-r8a7794" for R8A7794 (R-Car E2) SCIFA compatible UART. - - "renesas,scifb-r8a7794" for R8A7794 (R-Car E2) SCIFB compatible UART. - - "renesas,hscif-r8a7794" for R8A7794 (R-Car E2) HSCIF compatible UART. - - "renesas,scif-r8a7795" for R8A7795 (R-Car H3) SCIF compatible UART. - - "renesas,hscif-r8a7795" for R8A7795 (R-Car H3) HSCIF compatible UART. - - "renesas,scif-r8a7796" for R8A77960 (R-Car M3-W) SCIF compatible UART. - - "renesas,hscif-r8a7796" for R8A77960 (R-Car M3-W) HSCIF compatible UART. - - "renesas,scif-r8a77961" for R8A77961 (R-Car M3-W+) SCIF compatible UART. - - "renesas,hscif-r8a77961" for R8A77961 (R-Car M3-W+) HSCIF compatible UART. - - "renesas,scif-r8a77965" for R8A77965 (R-Car M3-N) SCIF compatible UART. - - "renesas,hscif-r8a77965" for R8A77965 (R-Car M3-N) HSCIF compatible UART. - - "renesas,scif-r8a77970" for R8A77970 (R-Car V3M) SCIF compatible UART. - - "renesas,hscif-r8a77970" for R8A77970 (R-Car V3M) HSCIF compatible UART. - - "renesas,scif-r8a77980" for R8A77980 (R-Car V3H) SCIF compatible UART. - - "renesas,hscif-r8a77980" for R8A77980 (R-Car V3H) HSCIF compatible UART. - - "renesas,scif-r8a77990" for R8A77990 (R-Car E3) SCIF compatible UART. - - "renesas,hscif-r8a77990" for R8A77990 (R-Car E3) HSCIF compatible UART. - - "renesas,scif-r8a77995" for R8A77995 (R-Car D3) SCIF compatible UART. - - "renesas,hscif-r8a77995" for R8A77995 (R-Car D3) HSCIF compatible UART. - - "renesas,scifa-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFA compatible UART. - - "renesas,scifb-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFB compatible UART. - - "renesas,rcar-gen1-scif" for R-Car Gen1 SCIF compatible UART, - - "renesas,rcar-gen2-scif" for R-Car Gen2 and RZ/G1 SCIF compatible UART, - - "renesas,rcar-gen3-scif" for R-Car Gen3 and RZ/G2 SCIF compatible UART, - - "renesas,rcar-gen2-scifa" for R-Car Gen2 and RZ/G1 SCIFA compatible UART, - - "renesas,rcar-gen2-scifb" for R-Car Gen2 and RZ/G1 SCIFB compatible UART, - - "renesas,rcar-gen1-hscif" for R-Car Gen1 HSCIF compatible UART, - - "renesas,rcar-gen2-hscif" for R-Car Gen2 and RZ/G1 HSCIF compatible UART, - - "renesas,rcar-gen3-hscif" for R-Car Gen3 and RZ/G2 HSCIF compatible UART, - - "renesas,scif" for generic SCIF compatible UART. - - "renesas,scifa" for generic SCIFA compatible UART. - - "renesas,scifb" for generic SCIFB compatible UART. - - "renesas,hscif" for generic HSCIF compatible UART. - - "renesas,sci" for generic SCI compatible UART. - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first, followed by the - family-specific and/or generic versions. - - - reg: Base address and length of the I/O registers used by the UART. - - interrupts: Must contain one or more interrupt-specifiers for the SCIx. - If a single interrupt is expressed, then all events are - multiplexed into this single interrupt. - - If multiple interrupts are provided by the hardware, the order - in which the interrupts are listed must match order below. Note - that some HW interrupt events may be muxed together resulting - in duplicate entries. - The interrupt order is as follows: - 1. Error (ERI) - 2. Receive buffer full (RXI) - 3. Transmit buffer empty (TXI) - 4. Break (BRI) - 5. Data Ready (DRI) - 6. Transmit End (TEI) - - - clocks: Must contain a phandle and clock-specifier pair for each entry - in clock-names. - - clock-names: Must contain "fck" for the SCIx UART functional clock. - Apart from the divided functional clock, there may be other possible - sources for the sampling clock, depending on SCIx variant. - On (H)SCI(F) and some SCIFA, an additional clock may be specified: - - "hsck" for the optional external clock input (on HSCIF), - - "sck" for the optional external clock input (on other variants). - On UARTs equipped with a Baud Rate Generator for External Clock (BRG) - (some SCIF and HSCIF), additional clocks may be specified: - - "brg_int" for the optional internal clock source for the frequency - divider (typically the (AXI or SHwy) bus clock), - - "scif_clk" for the optional external clock source for the frequency - divider (SCIF_CLK). - -Note: Each enabled SCIx UART may have an optional "serialN" alias in the -"aliases" node. - -Optional properties: - - dmas: Must contain a list of two references to DMA specifiers, one for - transmission, and one for reception. - - dma-names: Must contain a list of two DMA names, "tx" and "rx". - - {cts,dsr,dcd,rng,rts,dtr}-gpios: Specify GPIOs for modem lines, cfr. the - generic serial DT bindings in serial.txt. - - uart-has-rtscts: Indicates dedicated lines for RTS/CTS hardware flow - control, cfr. the generic serial DT bindings in serial.txt. - -Example: - aliases { - serial0 = &scifa0; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7790", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 64>; - interrupt-parent = <&gic>; - interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>; - dma-names = "tx", "rx"; - }; diff --git a/Documentation/devicetree/bindings/serial/renesas,sci.yaml b/Documentation/devicetree/bindings/serial/renesas,sci.yaml new file mode 100644 index 000000000000..4183b7311f37 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/renesas,sci.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/serial/renesas,sci.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Renesas Serial Communication Interface + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + const: renesas,sci + + reg: + maxItems: 1 + + interrupts: + items: + - description: Error interrupt + - description: Receive buffer full interrupt + - description: Transmit buffer empty interrupt + - description: Transmit end interrupt + + interrupt-names: + items: + - const: eri + - const: rxi + - const: txi + - const: tei + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + items: + enum: + - fck # UART functional clock + - sck # optional external clock input + + uart-has-rtscts: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +examples: + - | + aliases { + serial0 = &sci0; + }; + + sci0: serial@ffff78 { + compatible = "renesas,sci"; + reg = <0xffff78 8>; + interrupts = <88 0>, <89 0>, <90 0>, <91 0>; + clocks = <&fclk>; + clock-names = "fck"; + }; diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml new file mode 100644 index 000000000000..70392b9bd977 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/serial/renesas,scif.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Renesas Serial Communication Interface with FIFO (SCIF) + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,scif-r7s72100 # RZ/A1H + - const: renesas,scif # generic SCIF compatible UART + + - items: + - enum: + - renesas,scif-r7s9210 # RZ/A2 + + - items: + - enum: + - renesas,scif-r8a7778 # R-Car M1 + - renesas,scif-r8a7779 # R-Car H1 + - const: renesas,rcar-gen1-scif # R-Car Gen1 + - const: renesas,scif # generic SCIF compatible UART + + - items: + - enum: + - renesas,scif-r8a7743 # RZ/G1M + - renesas,scif-r8a7744 # RZ/G1N + - renesas,scif-r8a7745 # RZ/G1E + - renesas,scif-r8a77470 # RZ/G1C + - renesas,scif-r8a7790 # R-Car H2 + - renesas,scif-r8a7791 # R-Car M2-W + - renesas,scif-r8a7792 # R-Car V2H + - renesas,scif-r8a7793 # R-Car M2-N + - renesas,scif-r8a7794 # R-Car E2 + - const: renesas,rcar-gen2-scif # R-Car Gen2 and RZ/G1 + - const: renesas,scif # generic SCIF compatible UART + + - items: + - enum: + - renesas,scif-r8a774a1 # RZ/G2M + - renesas,scif-r8a774b1 # RZ/G2N + - renesas,scif-r8a774c0 # RZ/G2E + - renesas,scif-r8a7795 # R-Car H3 + - renesas,scif-r8a7796 # R-Car M3-W + - renesas,scif-r8a77961 # R-Car M3-W+ + - renesas,scif-r8a77965 # R-Car M3-N + - renesas,scif-r8a77970 # R-Car V3M + - renesas,scif-r8a77980 # R-Car V3H + - renesas,scif-r8a77990 # R-Car E3 + - renesas,scif-r8a77995 # R-Car D3 + - const: renesas,rcar-gen3-scif # R-Car Gen3 and RZ/G2 + - const: renesas,scif # generic SCIF compatible UART + + reg: + maxItems: 1 + + interrupts: + oneOf: + - items: + - description: A combined interrupt + - items: + - description: Error interrupt + - description: Receive buffer full interrupt + - description: Transmit buffer empty interrupt + - description: Transmit End interrupt + - items: + - description: Error interrupt + - description: Receive buffer full interrupt + - description: Transmit buffer empty interrupt + - description: Break interrupt + - description: Data Ready interrupt + - description: Transmit End interrupt + + interrupt-names: + oneOf: + - items: + - const: eri + - const: rxi + - const: txi + - const: tei + - items: + - const: eri + - const: rxi + - const: txi + - const: bri + - const: dri + - const: tei + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + items: + enum: + - fck # UART functional clock + - sck # optional external clock input + - brg_int # optional internal clock source for BRG frequency divider + - scif_clk # optional external clock source for BRG frequency divider + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + dmas: + description: + Must contain a list of pairs of references to DMA specifiers, one for + transmission, and one for reception. + + dma-names: + minItems: 2 + maxItems: 4 + items: + enum: + - tx + - rx + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + +if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen2-scif + - renesas,rcar-gen3-scif +then: + required: + - resets + +examples: + - | + #include <dt-bindings/clock/r8a7791-cpg-mssr.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/r8a7791-sysc.h> + aliases { + serial0 = &scif0; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", + "renesas,scif"; + reg = <0xe6e60000 64>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 721>; + }; diff --git a/Documentation/devicetree/bindings/serial/renesas,scifa.yaml b/Documentation/devicetree/bindings/serial/renesas,scifa.yaml new file mode 100644 index 000000000000..b28bcb268854 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/renesas,scifa.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/serial/renesas,scifa.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Renesas Serial Communications Interface with FIFO A (SCIFA) + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,scifa-r8a73a4 # R-Mobile APE6 + - renesas,scifa-r8a7740 # R-Mobile A1 + - renesas,scifa-sh73a0 # SH-Mobile AG5 + - const: renesas,scifa # generic SCIFA compatible UART + + - items: + - enum: + - renesas,scifa-r8a7743 # R8A7743 RZ/G1M + - renesas,scifa-r8a7744 # R8A7744 RZ/G1N + - renesas,scifa-r8a7745 # R8A7745 RZ/G1E + - renesas,scifa-r8a7790 # R8A7790 R-Car H2 + - renesas,scifa-r8a7791 # R8A7791 R-Car M2-W + - renesas,scifa-r8a7793 # R8A7793 R-Car M2-N + - renesas,scifa-r8a7794 # R8A7794 R-Car E2 + - const: renesas,rcar-gen2-scifa # R-Car Gen2 and RZ/G1 + - const: renesas,scifa # generic SCIFA compatible UART + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + enum: + - fck # UART functional clock + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + dmas: + description: + Must contain a list of pairs of references to DMA specifiers, one for + transmission, and one for reception. + + dma-names: + minItems: 2 + maxItems: 4 + items: + enum: + - tx + - rx + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + +if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen2-scifa +then: + required: + - resets + +examples: + - | + #include <dt-bindings/clock/r8a7790-cpg-mssr.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/r8a7790-sysc.h> + aliases { + serial0 = &scifa0; + }; + + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7790", "renesas,rcar-gen2-scifa", + "renesas,scifa"; + reg = <0xe6c40000 64>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 204>; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + }; diff --git a/Documentation/devicetree/bindings/serial/renesas,scifb.yaml b/Documentation/devicetree/bindings/serial/renesas,scifb.yaml new file mode 100644 index 000000000000..57205cb1dcd4 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/renesas,scifb.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/serial/renesas,scifb.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Renesas Serial Communications Interface with FIFO B (SCIFB) + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,scifb-r8a73a4 # R-Mobile APE6 + - renesas,scifb-r8a7740 # R-Mobile A1 + - renesas,scifb-sh73a0 # SH-Mobile AG5 + - const: renesas,scifb # generic SCIFB compatible UART + + - items: + - enum: + - renesas,scifb-r8a7743 # RZ/G1M + - renesas,scifb-r8a7744 # RZ/G1N + - renesas,scifb-r8a7745 # RZ/G1E + - renesas,scifb-r8a7790 # R-Car H2 + - renesas,scifb-r8a7791 # R-Car M2-W + - renesas,scifb-r8a7793 # R-Car M2-N + - renesas,scifb-r8a7794 # R-Car E2 + - const: renesas,rcar-gen2-scifb # R-Car Gen2 and RZ/G1 + - const: renesas,scifb # generic SCIFB compatible UART + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + enum: + - fck # UART functional clock + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + dmas: + description: + Must contain a list of pairs of references to DMA specifiers, one for + transmission, and one for reception. + + dma-names: + minItems: 2 + maxItems: 4 + items: + enum: + - tx + - rx + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + +if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen2-scifb +then: + required: + - resets + +examples: + - | + #include <dt-bindings/clock/r8a7740-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + scifb: serial@e6c30000 { + compatible = "renesas,scifb-r8a7740", "renesas,scifb"; + reg = <0xe6c30000 0x100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; + }; diff --git a/Documentation/devicetree/bindings/serial/serial.txt b/Documentation/devicetree/bindings/serial/serial.txt deleted file mode 100644 index 863c2893759e..000000000000 --- a/Documentation/devicetree/bindings/serial/serial.txt +++ /dev/null @@ -1,56 +0,0 @@ -Generic Serial DT Bindings - -This document lists a set of generic properties for describing UARTs in a -device tree. Whether these properties apply to a particular device depends on -the DT bindings for the actual device. - -Optional properties: - - cts-gpios: Must contain a GPIO specifier, referring to the GPIO pin to be - used as the UART's CTS line. - - dcd-gpios: Must contain a GPIO specifier, referring to the GPIO pin to be - used as the UART's DCD line. - - dsr-gpios: Must contain a GPIO specifier, referring to the GPIO pin to be - used as the UART's DSR line. - - dtr-gpios: Must contain a GPIO specifier, referring to the GPIO pin to be - used as the UART's DTR line. - - rng-gpios: Must contain a GPIO specifier, referring to the GPIO pin to be - used as the UART's RNG line. - - rts-gpios: Must contain a GPIO specifier, referring to the GPIO pin to be - used as the UART's RTS line. - - - uart-has-rtscts: The presence of this property indicates that the - UART has dedicated lines for RTS/CTS hardware flow control, and that - they are available for use (wired and enabled by pinmux configuration). - This depends on both the UART hardware and the board wiring. - Note that this property is mutually-exclusive with "cts-gpios" and - "rts-gpios" above, unless support is provided to switch between modes - dynamically. - - -Examples: - - uart1: serial@48022000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart2"; - clock-frequency = <48000000>; - reg = <0x48022000 0x2000>; - interrupts = <73>; - dmas = <&edma 28 0>, <&edma 29 0>; - dma-names = "tx", "rx"; - dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; - rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; - cts-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - }; - - scifa4: serial@e6c80000 { - compatible = "renesas,scifa-sh73a0", "renesas,scifa"; - reg = <0xe6c80000 0x100>; - interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - uart-has-rtscts; - }; diff --git a/Documentation/devicetree/bindings/serial/serial.yaml b/Documentation/devicetree/bindings/serial/serial.yaml new file mode 100644 index 000000000000..53204d90d0c7 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/serial.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/serial/serial.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Serial Interface Generic DT Bindings + +maintainers: + - Rob Herring <robh@kernel.org> + - Greg Kroah-Hartman <gregkh@linuxfoundation.org> + +description: + This document lists a set of generic properties for describing UARTs in a + device tree. Whether these properties apply to a particular device depends + on the DT bindings for the actual device. + + Each enabled UART may have an optional "serialN" alias in the "aliases" node, + where N is the port number (non-negative decimal integer) as printed on the + label next to the physical port. + +properties: + $nodename: + pattern: "^serial(@.*)?$" + + cts-gpios: + maxItems: 1 + description: + Must contain a GPIO specifier, referring to the GPIO pin to be used as + the UART's CTS line. + + dcd-gpios: + maxItems: 1 + description: + Must contain a GPIO specifier, referring to the GPIO pin to be used as + the UART's DCD line. + + dsr-gpios: + maxItems: 1 + description: + Must contain a GPIO specifier, referring to the GPIO pin to be used as + the UART's DSR line. + + dtr-gpios: + maxItems: 1 + description: + Must contain a GPIO specifier, referring to the GPIO pin to be used as + the UART's DTR line. + + rng-gpios: + maxItems: 1 + description: + Must contain a GPIO specifier, referring to the GPIO pin to be used as + the UART's RNG line. + + rts-gpios: + maxItems: 1 + description: + Must contain a GPIO specifier, referring to the GPIO pin to be used as + the UART's RTS line. + + uart-has-rtscts: + $ref: /schemas/types.yaml#/definitions/flag + description: + The presence of this property indicates that the UART has dedicated lines + for RTS/CTS hardware flow control, and that they are available for use + (wired and enabled by pinmux configuration). This depends on both the + UART hardware and the board wiring. + +if: + required: + - uart-has-rtscts +then: + properties: + cts-gpios: false + rts-gpios: false + +patternProperties: + ".*": + if: + type: object + then: + description: + Serial attached devices shall be a child node of the host UART device + the slave device is attached to. It is expected that the attached + device is the only child node of the UART device. The slave device node + name shall reflect the generic type of device for the node. + + properties: + compatible: + description: + Compatible of the device connected to the serial port. + + max-speed: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The maximum baud rate the device operates at. + This should only be present if the maximum is less than the slave + device can support. For example, a particular board has some + signal quality issue or the host processor can't support higher + baud rates. + + current-speed: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + The current baud rate the device operates at. + This should only be present in case a driver has no chance to know + the baud rate of the slave device. + Examples: + * device supports auto-baud + * the rate is setup by a bootloader and there is no way to reset + the device + * device baud rate is configured by its firmware but there is no + way to request the actual settings + + required: + - compatible + +examples: + - | + serial@1234 { + compatible = "ns16550a"; + reg = <0x1234 0x20>; + interrupts = <1>; + + bluetooth { + compatible = "brcm,bcm43341-bt"; + interrupt-parent = <&gpio>; + interrupts = <10>; + }; + }; diff --git a/Documentation/devicetree/bindings/serial/slave-device.txt b/Documentation/devicetree/bindings/serial/slave-device.txt deleted file mode 100644 index 40110e019620..000000000000 --- a/Documentation/devicetree/bindings/serial/slave-device.txt +++ /dev/null @@ -1,45 +0,0 @@ -Serial Slave Device DT binding - -This documents the binding structure and common properties for serial -attached devices. Common examples include Bluetooth, WiFi, NFC and GPS -devices. - -Serial attached devices shall be a child node of the host UART device the -slave device is attached to. It is expected that the attached device is -the only child node of the UART device. The slave device node name shall -reflect the generic type of device for the node. - -Required Properties: - -- compatible : A string reflecting the vendor and specific device the node - represents. - -Optional Properties: - -- max-speed : The maximum baud rate the device operates at. This should - only be present if the maximum is less than the slave device - can support. For example, a particular board has some signal - quality issue or the host processor can't support higher - baud rates. -- current-speed : The current baud rate the device operates at. This should - only be present in case a driver has no chance to know - the baud rate of the slave device. - Examples: - * device supports auto-baud - * the rate is setup by a bootloader and there is no - way to reset the device - * device baud rate is configured by its firmware but - there is no way to request the actual settings - -Example: - -serial@1234 { - compatible = "ns16550a"; - interrupts = <1>; - - bluetooth { - compatible = "brcm,bcm43341-bt"; - interrupt-parent = <&gpio>; - interrupts = <10>; - }; -}; diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index b42002542690..b962f8db4ce9 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -27,6 +27,7 @@ properties: - rockchip,rk3066-uart - rockchip,rk3188-uart - rockchip,rk3288-uart + - rockchip,rk3308-uart - rockchip,rk3328-uart - rockchip,rk3368-uart - rockchip,rk3399-uart diff --git a/Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml b/Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml new file mode 100644 index 000000000000..09a30300850c --- /dev/null +++ b/Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/socionext,uniphier-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier UART controller + +maintainers: + - Masahiro Yamada <yamada.masahiro@socionext.com> + +properties: + compatible: + const: socionext,uniphier-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + + auto-flow-control: + description: enable automatic flow control support. + $ref: /schemas/types.yaml#/definitions/flag + +required: + - compatible + - reg + - interrupts + - clocks + +examples: + - | + aliases { + serial0 = &serial0; + }; + + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + clocks = <&uart_clk>; + }; diff --git a/Documentation/devicetree/bindings/serial/uniphier-uart.txt b/Documentation/devicetree/bindings/serial/uniphier-uart.txt deleted file mode 100644 index 7a1bf02bb869..000000000000 --- a/Documentation/devicetree/bindings/serial/uniphier-uart.txt +++ /dev/null @@ -1,22 +0,0 @@ -UniPhier UART controller - -Required properties: -- compatible: should be "socionext,uniphier-uart". -- reg: offset and length of the register set for the device. -- interrupts: a single interrupt specifier. -- clocks: phandle to the input clock. - -Optional properties: --auto-flow-control: enable automatic flow control support. - -Example: - aliases { - serial0 = &serial0; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - clocks = <&uart_clk>; - }; diff --git a/Documentation/devicetree/bindings/soc/amlogic/amlogic,canvas.yaml b/Documentation/devicetree/bindings/soc/amlogic/amlogic,canvas.yaml index f548594d020b..cb008fd188d8 100644 --- a/Documentation/devicetree/bindings/soc/amlogic/amlogic,canvas.yaml +++ b/Documentation/devicetree/bindings/soc/amlogic/amlogic,canvas.yaml @@ -40,6 +40,8 @@ required: - compatible - reg +additionalProperties: false + examples: - | canvas: video-lut@48 { diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,aips-bus.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,aips-bus.yaml new file mode 100644 index 000000000000..3cbf2d28a188 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,aips-bus.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,aips-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX AHB to IP Bridge + +maintainers: + - Peng Fan <peng.fan@nxp.com> + +description: | + This particular peripheral is designed as the bridge between + AHB bus and peripherals with the lower bandwidth IP Slave (IPS) + buses. + +select: + properties: + compatible: + contains: + const: fsl,aips-bus + required: + - compatible + +properties: + compatible: + items: + - const: fsl,aips-bus + - const: simple-bus + + reg: + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + bus@30000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x30000000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; +... diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt index 7a32404c6114..ecac2bbeae45 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt @@ -20,6 +20,7 @@ Required properties in pwrap device node. - compatible: "mediatek,mt2701-pwrap" for MT2701/7623 SoCs "mediatek,mt6765-pwrap" for MT6765 SoCs + "mediatek,mt6779-pwrap" for MT6779 SoCs "mediatek,mt6797-pwrap" for MT6797 SoCs "mediatek,mt7622-pwrap" for MT7622 SoCs "mediatek,mt8135-pwrap" for MT8135 SoCs diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.txt index db501269f47b..f8fa71f5d84b 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.txt +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.txt @@ -45,6 +45,18 @@ by the individual bindings for the specific service 12 - Ultrasound stream manager. 13 - Listen stream manager. +- qcom,protection-domain + Usage: optional + Value type: <stringlist> + Definition: Must list the protection domain service name and path + that the particular apr service has a dependency on. + Possible values are : + "avs/audio", "msm/adsp/audio_pd". + "kernel/elf_loader", "msm/modem/wlan_pd". + "tms/servreg", "msm/adsp/audio_pd". + "tms/servreg", "msm/modem/wlan_pd". + "tms/servreg", "msm/slpi/sensor_pd". + = EXAMPLE The following example represents a QDSP based sound card on a MSM8996 device which uses apr as communication between Apps and QDSP. @@ -82,3 +94,41 @@ which uses apr as communication between Apps and QDSP. ... }; }; + += EXAMPLE 2 +The following example represents a QDSP based sound card with protection domain +dependencies specified. Here some of the apr services are dependent on services +running on protection domain hosted on ADSP/SLPI remote processors while others +have no such dependency. + + apr { + compatible = "qcom,apr-v2"; + qcom,glink-channels = "apr_audio_svc"; + qcom,apr-domain = <APR_DOMAIN_ADSP>; + + q6core { + compatible = "qcom,q6core"; + reg = <APR_SVC_ADSP_CORE>; + }; + + q6afe: q6afe { + compatible = "qcom,q6afe"; + reg = <APR_SVC_AFE>; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + ... + }; + + q6asm: q6asm { + compatible = "qcom,q6asm"; + reg = <APR_SVC_ASM>; + qcom,protection-domain = "tms/servreg", "msm/slpi/sensor_pd"; + ... + }; + + q6adm: q6adm { + compatible = "qcom,q6adm"; + reg = <APR_SVC_ADM>; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + ... + }; + }; diff --git a/Documentation/devicetree/bindings/sound/adi,adau7118.yaml b/Documentation/devicetree/bindings/sound/adi,adau7118.yaml index 75e0cbe6be70..76ee695097bf 100644 --- a/Documentation/devicetree/bindings/sound/adi,adau7118.yaml +++ b/Documentation/devicetree/bindings/sound/adi,adau7118.yaml @@ -59,6 +59,8 @@ required: - iovdd-supply - dvdd-supply +additionalProperties: false + examples: - | i2c { diff --git a/Documentation/devicetree/bindings/sound/amlogic,aiu.yaml b/Documentation/devicetree/bindings/sound/amlogic,aiu.yaml new file mode 100644 index 000000000000..a61bccf915d8 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/amlogic,aiu.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/amlogic,aiu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic AIU audio output controller + +maintainers: + - Jerome Brunet <jbrunet@baylibre.com> + +properties: + $nodename: + pattern: "^audio-controller@.*" + + "#sound-dai-cells": + const: 2 + + compatible: + items: + - enum: + - amlogic,aiu-gxbb + - amlogic,aiu-gxl + - amlogic,aiu-meson8 + - amlogic,aiu-meson8b + - const: + amlogic,aiu + + clocks: + items: + - description: AIU peripheral clock + - description: I2S peripheral clock + - description: I2S output clock + - description: I2S master clock + - description: I2S mixer clock + - description: SPDIF peripheral clock + - description: SPDIF output clock + - description: SPDIF master clock + - description: SPDIF master clock multiplexer + + clock-names: + items: + - const: pclk + - const: i2s_pclk + - const: i2s_aoclk + - const: i2s_mclk + - const: i2s_mixer + - const: spdif_pclk + - const: spdif_aoclk + - const: spdif_mclk + - const: spdif_mclk_sel + + interrupts: + items: + - description: I2S interrupt line + - description: SPDIF interrupt line + + interrupt-names: + items: + - const: i2s + - const: spdif + + reg: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - "#sound-dai-cells" + - compatible + - clocks + - clock-names + - interrupts + - interrupt-names + - reg + - resets + +examples: + - | + #include <dt-bindings/clock/gxbb-clkc.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> + + aiu: audio-controller@5400 { + compatible = "amlogic,aiu-gxl", "amlogic,aiu"; + #sound-dai-cells = <2>; + reg = <0x0 0x5400 0x0 0x2ac>; + interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "i2s", "spdif"; + clocks = <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_CTS_AMCLK>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>, + <&clkc CLKID_CTS_MCLK_I958>, + <&clkc CLKID_CTS_I958>; + clock-names = "pclk", + "i2s_pclk", + "i2s_aoclk", + "i2s_mclk", + "i2s_mixer", + "spdif_pclk", + "spdif_aoclk", + "spdif_mclk", + "spdif_mclk_sel"; + resets = <&reset RESET_AIU>; + }; + diff --git a/Documentation/devicetree/bindings/sound/amlogic,g12a-toacodec.yaml b/Documentation/devicetree/bindings/sound/amlogic,g12a-toacodec.yaml new file mode 100644 index 000000000000..f778d3371fde --- /dev/null +++ b/Documentation/devicetree/bindings/sound/amlogic,g12a-toacodec.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/amlogic,g12a-toacodec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic G12a Internal DAC Control Glue + +maintainers: + - Jerome Brunet <jbrunet@baylibre.com> + +properties: + $nodename: + pattern: "^audio-controller@.*" + + "#sound-dai-cells": + const: 1 + + compatible: + oneOf: + - items: + - const: + amlogic,g12a-toacodec + - items: + - enum: + - amlogic,sm1-toacodec + - const: + amlogic,g12a-toacodec + + reg: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - "#sound-dai-cells" + - compatible + - reg + - resets + +examples: + - | + #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h> + + toacodec: audio-controller@740 { + compatible = "amlogic,g12a-toacodec"; + reg = <0x0 0x740 0x0 0x4>; + #sound-dai-cells = <1>; + resets = <&clkc_audio AUD_RESET_TOACODEC>; + }; diff --git a/Documentation/devicetree/bindings/sound/amlogic,gx-sound-card.yaml b/Documentation/devicetree/bindings/sound/amlogic,gx-sound-card.yaml new file mode 100644 index 000000000000..fb374c659be1 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/amlogic,gx-sound-card.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/amlogic,gx-sound-card.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic GX sound card + +maintainers: + - Jerome Brunet <jbrunet@baylibre.com> + +properties: + compatible: + items: + - const: amlogic,gx-sound-card + + audio-aux-devs: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: list of auxiliary devices + + audio-routing: + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + minItems: 2 + description: |- + A list of the connections between audio components. Each entry is a + pair of strings, the first being the connection's sink, the second + being the connection's source. + + audio-widgets: + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + minItems: 2 + description: |- + A list off component DAPM widget. Each entry is a pair of strings, + the first being the widget type, the second being the widget name + + model: + $ref: /schemas/types.yaml#/definitions/string + description: User specified audio sound card name + +patternProperties: + "^dai-link-[0-9]+$": + type: object + description: |- + dai-link child nodes: + Container for dai-link level properties and the CODEC sub-nodes. + There should be at least one (and probably more) subnode of this type + + properties: + dai-format: + $ref: /schemas/types.yaml#/definitions/string + enum: [ i2s, left-j, dsp_a ] + + mclk-fs: + $ref: /schemas/types.yaml#/definitions/uint32 + description: |- + Multiplication factor between the frame rate and master clock + rate + + sound-dai: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle of the CPU DAI + + patternProperties: + "^codec-[0-9]+$": + type: object + description: |- + Codecs: + dai-link representing backend links should have at least one subnode. + One subnode for each codec of the dai-link. dai-link representing + frontend links have no codec, therefore have no subnodes + + properties: + sound-dai: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle of the codec DAI + + required: + - sound-dai + + required: + - sound-dai + +required: + - model + - dai-link-0 + +examples: + - | + sound { + compatible = "amlogic,gx-sound-card"; + model = "GXL-ACME-S905X-FOO"; + audio-aux-devs = <&>; + audio-routing = "I2S ENCODER I2S IN", "I2S FIFO Playback"; + + dai-link-0 { + sound-dai = <&i2s_fifo>; + }; + + dai-link-1 { + sound-dai = <&i2s_encoder>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&codec0>; + }; + + codec-1 { + sound-dai = <&codec1>; + }; + }; + }; + diff --git a/Documentation/devicetree/bindings/sound/amlogic,t9015.yaml b/Documentation/devicetree/bindings/sound/amlogic,t9015.yaml new file mode 100644 index 000000000000..b7c38c2b5b54 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/amlogic,t9015.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/amlogic,t9015.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic T9015 Internal Audio DAC + +maintainers: + - Jerome Brunet <jbrunet@baylibre.com> + +properties: + $nodename: + pattern: "^audio-controller@.*" + + "#sound-dai-cells": + const: 0 + + compatible: + items: + - const: amlogic,t9015 + + clocks: + items: + - description: Peripheral clock + + clock-names: + items: + - const: pclk + + reg: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - "#sound-dai-cells" + - compatible + - reg + - clocks + - clock-names + - resets + +examples: + - | + #include <dt-bindings/clock/g12a-clkc.h> + #include <dt-bindings/reset/amlogic,meson-g12a-reset.h> + + acodec: audio-controller@32000 { + compatible = "amlogic,t9015"; + reg = <0x0 0x32000 0x0 0x14>; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_AUDIO_CODEC>; + clock-names = "pclk"; + resets = <&reset RESET_AUDIO_CODEC>; + }; + diff --git a/Documentation/devicetree/bindings/sound/brcm,bcm63xx-audio.txt b/Documentation/devicetree/bindings/sound/brcm,bcm63xx-audio.txt new file mode 100644 index 000000000000..007f524b4d15 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/brcm,bcm63xx-audio.txt @@ -0,0 +1,29 @@ +Broadcom DSL/PON BCM63xx Audio I2S controller + +Required properties: +- compatible: Should be "brcm,bcm63xx-i2s". +- #address-cells: 32bit valued, 1 cell. +- #size-cells: 32bit valued, 0 cell. +- reg: Should contain audio registers location and length +- interrupts: Should contain the interrupt for the controller. +- clocks: Must contain an entry for each entry in clock-names. + Please refer to clock-bindings.txt. +- clock-names: One of each entry matching the clocks phandles list: + - "i2sclk" (generated clock) Required. + - "i2sosc" (fixed 200MHz clock) Required. + +(1) : The generated clock is required only when any of TX and RX + works on Master Mode. +(2) : The fixed 200MHz clock is from internal chip and always on + +Example: + + i2s: bcm63xx-i2s { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm63xx-i2s"; + reg = <0xFF802080 0xFF>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&i2sclk>, <&osc>; + clock-names = "i2sclk","i2sosc"; + }; diff --git a/Documentation/devicetree/bindings/sound/cirrus,cs42l51.yaml b/Documentation/devicetree/bindings/sound/cirrus,cs42l51.yaml new file mode 100644 index 000000000000..83f44f07ac3f --- /dev/null +++ b/Documentation/devicetree/bindings/sound/cirrus,cs42l51.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/cirrus,cs42l51.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CS42L51 audio codec DT bindings + +maintainers: + - Olivier Moysan <olivier.moysan@st.com> + +properties: + compatible: + const: cirrus,cs42l51 + + reg: + maxItems: 1 + + "#sound-dai-cells": + const: 0 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: MCLK + + reset-gpios: + maxItems: 1 + + VL-supply: + description: phandle to voltage regulator of digital interface section + + VD-supply: + description: phandle to voltage regulator of digital internal section + + VA-supply: + description: phandle to voltage regulator of analog internal section + + VAHP-supply: + description: phandle to voltage regulator of headphone + +required: + - compatible + - reg + - "#sound-dai-cells" + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + cs42l51@4a { + compatible = "cirrus,cs42l51"; + reg = <0x4a>; + #sound-dai-cells = <0>; + clocks = <&mclk_prov>; + clock-names = "MCLK"; + VL-supply = <®_audio>; + VD-supply = <®_audio>; + VA-supply = <®_audio>; + VAHP-supply = <®_audio>; + reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/sound/cs42l51.txt b/Documentation/devicetree/bindings/sound/cs42l51.txt deleted file mode 100644 index acbd68ddd2cb..000000000000 --- a/Documentation/devicetree/bindings/sound/cs42l51.txt +++ /dev/null @@ -1,33 +0,0 @@ -CS42L51 audio CODEC - -Required properties: - - - compatible : "cirrus,cs42l51" - - - reg : the I2C address of the device for I2C. - -Optional properties: - - VL-supply, VD-supply, VA-supply, VAHP-supply: power supplies for the device, - as covered in Documentation/devicetree/bindings/regulator/regulator.txt. - - - reset-gpios : GPIO specification for the reset pin. If specified, it will be - deasserted before starting the communication with the codec. - - - clocks : a list of phandles + clock-specifiers, one for each entry in - clock-names - - - clock-names : must contain "MCLK" - -Example: - -cs42l51: cs42l51@4a { - compatible = "cirrus,cs42l51"; - reg = <0x4a>; - clocks = <&mclk_prov>; - clock-names = "MCLK"; - VL-supply = <®_audio>; - VD-supply = <®_audio>; - VA-supply = <®_audio>; - VAHP-supply = <®_audio>; - reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>; -}; diff --git a/Documentation/devicetree/bindings/sound/google,cros-ec-codec.txt b/Documentation/devicetree/bindings/sound/google,cros-ec-codec.txt deleted file mode 100644 index 8ca52dcc5572..000000000000 --- a/Documentation/devicetree/bindings/sound/google,cros-ec-codec.txt +++ /dev/null @@ -1,44 +0,0 @@ -Audio codec controlled by ChromeOS EC - -Google's ChromeOS EC codec is a digital mic codec provided by the -Embedded Controller (EC) and is controlled via a host-command interface. - -An EC codec node should only be found as a sub-node of the EC node (see -Documentation/devicetree/bindings/mfd/cros-ec.txt). - -Required properties: -- compatible: Must contain "google,cros-ec-codec" -- #sound-dai-cells: Should be 1. The cell specifies number of DAIs. - -Optional properties: -- reg: Pysical base address and length of shared memory region from EC. - It contains 3 unsigned 32-bit integer. The first 2 integers - combine to become an unsigned 64-bit physical address. The last - one integer is length of the shared memory. -- memory-region: Shared memory region to EC. A "shared-dma-pool". See - ../reserved-memory/reserved-memory.txt for details. - -Example: - -{ - ... - - reserved_mem: reserved_mem { - compatible = "shared-dma-pool"; - reg = <0 0x52800000 0 0x100000>; - no-map; - }; -} - -cros-ec@0 { - compatible = "google,cros-ec-spi"; - - ... - - cros_ec_codec: ec-codec { - compatible = "google,cros-ec-codec"; - #sound-dai-cells = <1>; - reg = <0x0 0x10500000 0x80000>; - memory-region = <&reserved_mem>; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/google,cros-ec-codec.yaml b/Documentation/devicetree/bindings/sound/google,cros-ec-codec.yaml new file mode 100644 index 000000000000..c84e656afb0a --- /dev/null +++ b/Documentation/devicetree/bindings/sound/google,cros-ec-codec.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/google,cros-ec-codec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Audio codec controlled by ChromeOS EC + +maintainers: + - Cheng-Yi Chiang <cychiang@chromium.org> + +description: | + Google's ChromeOS EC codec is a digital mic codec provided by the + Embedded Controller (EC) and is controlled via a host-command interface. + An EC codec node should only be found as a sub-node of the EC node (see + Documentation/devicetree/bindings/mfd/cros-ec.txt). + +properties: + compatible: + const: google,cros-ec-codec + + "#sound-dai-cells": + const: 1 + + reg: + items: + - description: | + Physical base address and length of shared memory region from EC. + It contains 3 unsigned 32-bit integer. The first 2 integers + combine to become an unsigned 64-bit physical address. + The last one integer is the length of the shared memory. + + memory-region: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: | + Shared memory region to EC. A "shared-dma-pool". + See ../reserved-memory/reserved-memory.txt for details. + +required: + - compatible + - '#sound-dai-cells' + +additionalProperties: false + +examples: + - | + reserved_mem: reserved-mem@52800000 { + compatible = "shared-dma-pool"; + reg = <0x52800000 0x100000>; + no-map; + }; + spi { + #address-cells = <1>; + #size-cells = <0>; + cros-ec@0 { + compatible = "google,cros-ec-spi"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0>; + cros_ec_codec: ec-codec@10500000 { + compatible = "google,cros-ec-codec"; + #sound-dai-cells = <1>; + reg = <0x0 0x10500000 0x80000>; + memory-region = <&reserved_mem>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/ingenic,aic.yaml b/Documentation/devicetree/bindings/sound/ingenic,aic.yaml new file mode 100644 index 000000000000..44f49bebb267 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ingenic,aic.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/ingenic,aic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic SoCs AC97 / I2S Controller (AIC) DT bindings + +maintainers: + - Paul Cercueil <paul@crapouillou.net> + +properties: + $nodename: + pattern: '^audio-controller@' + + compatible: + oneOf: + - enum: + - ingenic,jz4740-i2s + - ingenic,jz4760-i2s + - ingenic,jz4770-i2s + - ingenic,jz4780-i2s + - items: + - const: ingenic,jz4725b-i2s + - const: ingenic,jz4740-i2s + + '#sound-dai-cells': + const: 0 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: AIC clock + - description: I2S clock + - description: EXT clock + - description: PLL/2 clock + + clock-names: + items: + - const: aic + - const: i2s + - const: ext + - const: pll half + + dmas: + items: + - description: DMA controller phandle and request line for I2S RX + - description: DMA controller phandle and request line for I2S TX + + dma-names: + items: + - const: rx + - const: tx + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - dmas + - dma-names + - '#sound-dai-cells' + +examples: + - | + #include <dt-bindings/clock/jz4740-cgu.h> + aic: audio-controller@10020000 { + compatible = "ingenic,jz4740-i2s"; + reg = <0x10020000 0x38>; + + #sound-dai-cells = <0>; + + interrupt-parent = <&intc>; + interrupts = <18>; + + clocks = <&cgu JZ4740_CLK_AIC>, + <&cgu JZ4740_CLK_I2S>, + <&cgu JZ4740_CLK_EXT>, + <&cgu JZ4740_CLK_PLL_HALF>; + clock-names = "aic", "i2s", "ext", "pll half"; + + dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>; + dma-names = "rx", "tx"; + }; diff --git a/Documentation/devicetree/bindings/sound/ingenic,jz4740-i2s.txt b/Documentation/devicetree/bindings/sound/ingenic,jz4740-i2s.txt deleted file mode 100644 index b623d50004fb..000000000000 --- a/Documentation/devicetree/bindings/sound/ingenic,jz4740-i2s.txt +++ /dev/null @@ -1,23 +0,0 @@ -Ingenic JZ4740 I2S controller - -Required properties: -- compatible : "ingenic,jz4740-i2s" or "ingenic,jz4780-i2s" -- reg : I2S registers location and length -- clocks : AIC and I2S PLL clock specifiers. -- clock-names: "aic" and "i2s" -- dmas: DMA controller phandle and DMA request line for I2S Tx and Rx channels -- dma-names: Must be "tx" and "rx" - -Example: - -i2s: i2s@10020000 { - compatible = "ingenic,jz4740-i2s"; - reg = <0x10020000 0x94>; - - clocks = <&cgu JZ4740_CLK_AIC>, <&cgu JZ4740_CLK_I2SPLL>; - clock-names = "aic", "i2s"; - - dmas = <&dma 2>, <&dma 3>; - dma-names = "tx", "rx"; - -}; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt index b795d282818d..a8f2b0c56c79 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt @@ -18,6 +18,7 @@ Required properties: * Headphone Jack * Int Spk * Mic Jack + * Int Mic - nvidia,i2s-controller : The phandle of the Tegra I2S1 controller - nvidia,audio-codec : The phandle of the WM8903 audio codec diff --git a/Documentation/devicetree/bindings/sound/qcom,wcd934x.yaml b/Documentation/devicetree/bindings/sound/qcom,wcd934x.yaml index 38eaf0c028f9..a495d5fc0d23 100644 --- a/Documentation/devicetree/bindings/sound/qcom,wcd934x.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,wcd934x.yaml @@ -139,6 +139,8 @@ required: - "#address-cells" - "#size-cells" +additionalProperties: false + examples: - | codec@1,0{ diff --git a/Documentation/devicetree/bindings/sound/renesas,fsi.yaml b/Documentation/devicetree/bindings/sound/renesas,fsi.yaml index 140a37fc3c0b..d1b65554e681 100644 --- a/Documentation/devicetree/bindings/sound/renesas,fsi.yaml +++ b/Documentation/devicetree/bindings/sound/renesas,fsi.yaml @@ -63,6 +63,8 @@ required: - reg - interrupts +additionalProperties: false + examples: - | sh_fsi2: sound@ec230000 { diff --git a/Documentation/devicetree/bindings/sound/rockchip,rk3328-codec.txt b/Documentation/devicetree/bindings/sound/rockchip,rk3328-codec.txt index 2469588c7ccb..1ecd75d2032a 100644 --- a/Documentation/devicetree/bindings/sound/rockchip,rk3328-codec.txt +++ b/Documentation/devicetree/bindings/sound/rockchip,rk3328-codec.txt @@ -10,6 +10,11 @@ Required properties: - clock-names: should be "pclk". - spk-depop-time-ms: speak depop time msec. +Optional properties: + +- mute-gpios: GPIO specifier for external line driver control (typically the + dedicated GPIO_MUTE pin) + Example for rk3328 internal codec: codec: codec@ff410000 { @@ -18,6 +23,6 @@ codec: codec@ff410000 { rockchip,grf = <&grf>; clocks = <&cru PCLK_ACODEC>; clock-names = "pclk"; + mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; spk-depop-time-ms = 100; - status = "disabled"; }; diff --git a/Documentation/devicetree/bindings/sound/rockchip-i2s.txt b/Documentation/devicetree/bindings/sound/rockchip-i2s.txt deleted file mode 100644 index 54aefab71f2c..000000000000 --- a/Documentation/devicetree/bindings/sound/rockchip-i2s.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Rockchip I2S controller - -The I2S bus (Inter-IC sound bus) is a serial link for digital -audio data transfer between devices in the system. - -Required properties: - -- compatible: should be one of the following: - - "rockchip,rk3066-i2s": for rk3066 - - "rockchip,px30-i2s", "rockchip,rk3066-i2s": for px30 - - "rockchip,rk3036-i2s", "rockchip,rk3066-i2s": for rk3036 - - "rockchip,rk3188-i2s", "rockchip,rk3066-i2s": for rk3188 - - "rockchip,rk3228-i2s", "rockchip,rk3066-i2s": for rk3228 - - "rockchip,rk3288-i2s", "rockchip,rk3066-i2s": for rk3288 - - "rockchip,rk3328-i2s", "rockchip,rk3066-i2s": for rk3328 - - "rockchip,rk3366-i2s", "rockchip,rk3066-i2s": for rk3366 - - "rockchip,rk3368-i2s", "rockchip,rk3066-i2s": for rk3368 - - "rockchip,rk3399-i2s", "rockchip,rk3066-i2s": for rk3399 -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: should contain the I2S interrupt. -- dmas: DMA specifiers for tx and rx dma. See the DMA client binding, - Documentation/devicetree/bindings/dma/dma.txt -- dma-names: should include "tx" and "rx". -- clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names. -- clock-names: should contain the following: - - "i2s_hclk": clock for I2S BUS - - "i2s_clk" : clock for I2S controller -- rockchip,playback-channels: max playback channels, if not set, 8 channels default. -- rockchip,capture-channels: max capture channels, if not set, 2 channels default. - -Required properties for controller which support multi channels -playback/capture: - -- rockchip,grf: the phandle of the syscon node for GRF register. - -Example for rk3288 I2S controller: - -i2s@ff890000 { - compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; - reg = <0xff890000 0x10000>; - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&pdma1 0>, <&pdma1 1>; - dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; - rockchip,playback-channels = <8>; - rockchip,capture-channels = <2>; -}; diff --git a/Documentation/devicetree/bindings/sound/rockchip-i2s.yaml b/Documentation/devicetree/bindings/sound/rockchip-i2s.yaml new file mode 100644 index 000000000000..7cd0e278ed85 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/rockchip-i2s.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/rockchip-i2s.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip I2S controller + +description: + The I2S bus (Inter-IC sound bus) is a serial link for digital + audio data transfer between devices in the system. + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + oneOf: + - const: rockchip,rk3066-i2s + - items: + - enum: + - rockchip,px30-i2s + - rockchip,rk3036-i2s + - rockchip,rk3188-i2s + - rockchip,rk3228-i2s + - rockchip,rk3288-i2s + - rockchip,rk3328-i2s + - rockchip,rk3366-i2s + - rockchip,rk3368-i2s + - rockchip,rk3399-i2s + - const: rockchip,rk3066-i2s + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: clock for I2S controller + - description: clock for I2S BUS + + clock-names: + items: + - const: i2s_clk + - const: i2s_hclk + + dmas: + items: + - description: TX DMA Channel + - description: RX DMA Channel + + dma-names: + items: + - const: tx + - const: rx + + rockchip,capture-channels: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + default: 2 + description: + Max capture channels, if not set, 2 channels default. + + rockchip,playback-channels: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + default: 8 + description: + Max playback channels, if not set, 8 channels default. + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the syscon node for the GRF register. + Required property for controllers which support multi channel + playback/capture. + + "#sound-dai-cells": + const: 0 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - dmas + - dma-names + - "#sound-dai-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3288-cru.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + i2s@ff890000 { + compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; + reg = <0xff890000 0x10000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&pdma1 0>, <&pdma1 1>; + dma-names = "tx", "rx"; + rockchip,capture-channels = <2>; + rockchip,playback-channels = <8>; + #sound-dai-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/sound/rt5682.txt b/Documentation/devicetree/bindings/sound/rt5682.txt index 30e927a28369..ade1ece8b45f 100644 --- a/Documentation/devicetree/bindings/sound/rt5682.txt +++ b/Documentation/devicetree/bindings/sound/rt5682.txt @@ -32,6 +32,18 @@ Optional properties: The delay time is realtek,btndet-delay value multiple of 8.192 ms. If absent, the default is 16. +- #clock-cells : Should be set to '<1>', wclk and bclk sources provided. +- clock-output-names : Name given for DAI clocks output. + +- clocks : phandle and clock specifier for codec MCLK. +- clock-names : Clock name string for 'clocks' attribute, should be "mclk". + +- realtek,dmic-clk-rate-hz : Set the clock rate (hz) for the requirement of + the particular DMIC. + +- realtek,dmic-delay-ms : Set the delay time (ms) for the requirement of + the particular DMIC. + Pins on the device (for linking into audio routes) for RT5682: * DMIC L1 @@ -53,4 +65,10 @@ rt5682 { realtek,dmic1-clk-pin = <1>; realtek,jd-src = <1>; realtek,btndet-delay = <16>; + + #clock-cells = <1>; + clock-output-names = "rt5682-dai-wclk", "rt5682-dai-bclk"; + + clocks = <&osc>; + clock-names = "mclk"; }; diff --git a/Documentation/devicetree/bindings/sound/samsung,odroid.yaml b/Documentation/devicetree/bindings/sound/samsung,odroid.yaml index c6b244352d05..8ff2d39e7d17 100644 --- a/Documentation/devicetree/bindings/sound/samsung,odroid.yaml +++ b/Documentation/devicetree/bindings/sound/samsung,odroid.yaml @@ -69,6 +69,8 @@ required: - cpu - codec +additionalProperties: false + examples: - | sound { diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.yaml b/Documentation/devicetree/bindings/sound/samsung-i2s.yaml index 53e3bad4178c..b2ad093d94df 100644 --- a/Documentation/devicetree/bindings/sound/samsung-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/samsung-i2s.yaml @@ -115,6 +115,8 @@ required: - clocks - clock-names +additionalProperties: false + examples: - | #include <dt-bindings/clock/exynos-audss-clk.h> diff --git a/Documentation/devicetree/bindings/sound/st,stm32-i2s.txt b/Documentation/devicetree/bindings/sound/st,stm32-i2s.txt deleted file mode 100644 index cbf24bcd1b8d..000000000000 --- a/Documentation/devicetree/bindings/sound/st,stm32-i2s.txt +++ /dev/null @@ -1,62 +0,0 @@ -STMicroelectronics STM32 SPI/I2S Controller - -The SPI/I2S block supports I2S/PCM protocols when configured on I2S mode. -Only some SPI instances support I2S. - -Required properties: - - compatible: Must be "st,stm32h7-i2s" - - reg: Offset and length of the device's register set. - - interrupts: Must contain the interrupt line id. - - clocks: Must contain phandle and clock specifier pairs for each entry - in clock-names. - - clock-names: Must contain "i2sclk", "pclk", "x8k" and "x11k". - "i2sclk": clock which feeds the internal clock generator - "pclk": clock which feeds the peripheral bus interface - "x8k": I2S parent clock for sampling rates multiple of 8kHz. - "x11k": I2S parent clock for sampling rates multiple of 11.025kHz. - - dmas: DMA specifiers for tx and rx dma. - See Documentation/devicetree/bindings/dma/stm32-dma.txt. - - dma-names: Identifier for each DMA request line. Must be "tx" and "rx". - - pinctrl-names: should contain only value "default" - - pinctrl-0: see Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml - -Optional properties: - - resets: Reference to a reset controller asserting the reset controller - -The device node should contain one 'port' child node with one child 'endpoint' -node, according to the bindings defined in Documentation/devicetree/bindings/ -graph.txt. - -Example: -sound_card { - compatible = "audio-graph-card"; - dais = <&i2s2_port>; -}; - -i2s2: audio-controller@40003800 { - compatible = "st,stm32h7-i2s"; - reg = <0x40003800 0x400>; - interrupts = <36>; - clocks = <&rcc PCLK1>, <&rcc SPI2_CK>, <&rcc PLL1_Q>, <&rcc PLL2_P>; - clock-names = "pclk", "i2sclk", "x8k", "x11k"; - dmas = <&dmamux2 2 39 0x400 0x1>, - <&dmamux2 3 40 0x400 0x1>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2s2>; - - i2s2_port: port@0 { - cpu_endpoint: endpoint { - remote-endpoint = <&codec_endpoint>; - format = "i2s"; - }; - }; -}; - -audio-codec { - codec_port: port@0 { - codec_endpoint: endpoint { - remote-endpoint = <&cpu_endpoint>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml new file mode 100644 index 000000000000..f32410890589 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/st,stm32-i2s.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 SPI/I2S Controller + +maintainers: + - Olivier Moysan <olivier.moysan@st.com> + +description: + The SPI/I2S block supports I2S/PCM protocols when configured on I2S mode. + Only some SPI instances support I2S. + +properties: + compatible: + enum: + - st,stm32h7-i2s + + "#sound-dai-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + items: + - description: clock feeding the peripheral bus interface. + - description: clock feeding the internal clock generator. + - description: I2S parent clock for sampling rates multiple of 8kHz. + - description: I2S parent clock for sampling rates multiple of 11.025kHz. + + clock-names: + items: + - const: pclk + - const: i2sclk + - const: x8k + - const: x11k + + interrupts: + maxItems: 1 + + dmas: + items: + - description: audio capture DMA. + - description: audio playback DMA. + + dma-names: + items: + - const: rx + - const: tx + + resets: + maxItems: 1 + +required: + - compatible + - "#sound-dai-cells" + - reg + - clocks + - clock-names + - interrupts + - dmas + - dma-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stm32mp1-clks.h> + i2s2: audio-controller@4000b000 { + compatible = "st,stm32h7-i2s"; + #sound-dai-cells = <0>; + reg = <0x4000b000 0x400>; + clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "i2sclk", "x8k", "x11k"; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 39 0x400 0x01>, + <&dmamux1 40 0x400 0x01>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2_pins_a>; + }; + +... diff --git a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.txt b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.txt deleted file mode 100644 index ca9101777c44..000000000000 --- a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.txt +++ /dev/null @@ -1,56 +0,0 @@ -STMicroelectronics STM32 S/PDIF receiver (SPDIFRX). - -The SPDIFRX peripheral, is designed to receive an S/PDIF flow compliant with -IEC-60958 and IEC-61937. - -Required properties: - - compatible: should be "st,stm32h7-spdifrx" - - reg: cpu DAI IP base address and size - - clocks: must contain an entry for kclk (used as S/PDIF signal reference) - - clock-names: must contain "kclk" - - interrupts: cpu DAI interrupt line - - dmas: DMA specifiers for audio data DMA and iec control flow DMA - See STM32 DMA bindings, Documentation/devicetree/bindings/dma/st,stm32-dma.yaml - - dma-names: two dmas have to be defined, "rx" and "rx-ctrl" - -Optional properties: - - resets: Reference to a reset controller asserting the SPDIFRX - -The device node should contain one 'port' child node with one child 'endpoint' -node, according to the bindings defined in Documentation/devicetree/bindings/ -graph.txt. - -Example: -spdifrx: spdifrx@40004000 { - compatible = "st,stm32h7-spdifrx"; - reg = <0x40004000 0x400>; - clocks = <&rcc SPDIFRX_CK>; - clock-names = "kclk"; - interrupts = <97>; - dmas = <&dmamux1 2 93 0x400 0x0>, - <&dmamux1 3 94 0x400 0x0>; - dma-names = "rx", "rx-ctrl"; - pinctrl-0 = <&spdifrx_pins>; - pinctrl-names = "default"; - - spdifrx_port: port { - cpu_endpoint: endpoint { - remote-endpoint = <&codec_endpoint>; - }; - }; -}; - -spdif_in: spdif-in { - compatible = "linux,spdif-dir"; - - codec_port: port { - codec_endpoint: endpoint { - remote-endpoint = <&cpu_endpoint>; - }; - }; -}; - -soundcard { - compatible = "audio-graph-card"; - dais = <&spdifrx_port>; -}; diff --git a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml new file mode 100644 index 000000000000..b7f7dc452231 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/st,stm32-spdifrx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 S/PDIF receiver (SPDIFRX) + +maintainers: + - Olivier Moysan <olivier.moysan@st.com> + +description: | + The SPDIFRX peripheral, is designed to receive an S/PDIF flow compliant with + IEC-60958 and IEC-61937. + +properties: + compatible: + enum: + - st,stm32h7-spdifrx + + "#sound-dai-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: kclk + + interrupts: + maxItems: 1 + + dmas: + items: + - description: audio data capture DMA + - description: IEC status bits capture DMA + + dma-names: + items: + - const: rx + - const: rx-ctrl + + resets: + maxItems: 1 + +required: + - compatible + - "#sound-dai-cells" + - reg + - clocks + - clock-names + - interrupts + - dmas + - dma-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stm32mp1-clks.h> + spdifrx: spdifrx@40004000 { + compatible = "st,stm32h7-spdifrx"; + #sound-dai-cells = <0>; + reg = <0x40004000 0x400>; + clocks = <&rcc SPDIF_K>; + clock-names = "kclk"; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 2 93 0x400 0x0>, + <&dmamux1 3 94 0x400 0x0>; + dma-names = "rx", "rx-ctrl"; + pinctrl-0 = <&spdifrx_pins>; + pinctrl-names = "default"; + }; + +... diff --git a/Documentation/devicetree/bindings/sound/tas2562.txt b/Documentation/devicetree/bindings/sound/tas2562.txt index 658e1fb18a99..94796b547184 100644 --- a/Documentation/devicetree/bindings/sound/tas2562.txt +++ b/Documentation/devicetree/bindings/sound/tas2562.txt @@ -8,7 +8,7 @@ real time monitoring of loudspeaker behavior. Required properties: - #address-cells - Should be <1>. - #size-cells - Should be <0>. - - compatible: - Should contain "ti,tas2562". + - compatible: - Should contain "ti,tas2562", "ti,tas2563". - reg: - The i2c address. Should be 0x4c, 0x4d, 0x4e or 0x4f. - ti,imon-slot-no:- TDM TX current sense time slot. diff --git a/Documentation/devicetree/bindings/sound/tlv320adcx140.yaml b/Documentation/devicetree/bindings/sound/tlv320adcx140.yaml new file mode 100644 index 000000000000..ab2268c0ee67 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/tlv320adcx140.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) +# Copyright (C) 2019 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/tlv320adcx140.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter + +maintainers: + - Dan Murphy <dmurphy@ti.com> + +description: | + The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital + PDM microphones recording), high-performance audio, analog-to-digital + converter (ADC) with analog inputs supporting up to 2V RMS. The TLV320ADCX140 + family supports line and microphone Inputs, and offers a programmable + microphone bias or supply voltage generation. + + Specifications can be found at: + http://www.ti.com/lit/ds/symlink/tlv320adc3140.pdf + http://www.ti.com/lit/ds/symlink/tlv320adc5140.pdf + http://www.ti.com/lit/ds/symlink/tlv320adc6140.pdf + +properties: + compatible: + oneOf: + - const: ti,tlv320adc3140 + - const: ti,tlv320adc5140 + - const: ti,tlv320adc6140 + + reg: + maxItems: 1 + description: | + I2C addresss of the device can be one of these 0x4c, 0x4d, 0x4e or 0x4f + + reset-gpios: + description: | + GPIO used for hardware reset. + + areg-supply: + description: | + Regulator with AVDD at 3.3V. If not defined then the internal regulator + is enabled. + + ti,mic-bias-source: + description: | + Indicates the source for MIC Bias. + 0 - Mic bias is set to VREF + 1 - Mic bias is set to VREF × 1.096 + 6 - Mic bias is set to AVDD + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0, 1, 6] + + ti,vref-source: + description: | + Indicates the source for MIC Bias. + 0 - Set VREF to 2.75V + 1 - Set VREF to 2.5V + 2 - Set VREF to 1.375V + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0, 1, 2] + +required: + - compatible + - reg + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + codec: codec@4c { + compatible = "ti,tlv320adc5140"; + reg = <0x4c>; + ti,mic-bias-source = <6>; + reset-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml index 0565dc49e449..243a6b1e66ea 100644 --- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml +++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml @@ -18,9 +18,14 @@ properties: "#size-cells": true compatible: - enum: - - allwinner,sun6i-a31-spi - - allwinner,sun8i-h3-spi + oneOf: + - const: allwinner,sun6i-a31-spi + - const: allwinner,sun8i-h3-spi + - items: + - enum: + - allwinner,sun8i-r40-spi + - allwinner,sun50i-h6-spi + - const: allwinner,sun8i-h3-spi reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt deleted file mode 100644 index 1d64b61f5171..000000000000 --- a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt +++ /dev/null @@ -1,36 +0,0 @@ -Qualcomm Quad Serial Peripheral Interface (QSPI) - -The QSPI controller allows SPI protocol communication in single, dual, or quad -wire transmission modes for read/write access to slaves such as NOR flash. - -Required properties: -- compatible: An SoC specific identifier followed by "qcom,qspi-v1", such as - "qcom,sdm845-qspi", "qcom,qspi-v1" -- reg: Should contain the base register location and length. -- interrupts: Interrupt number used by the controller. -- clocks: Should contain the core and AHB clock. -- clock-names: Should be "core" for core clock and "iface" for AHB clock. - -SPI slave nodes must be children of the SPI master node and can contain -properties described in Documentation/devicetree/bindings/spi/spi-bus.txt - -Example: - - qspi: spi@88df000 { - compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; - reg = <0x88df000 0x600>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "iface", "core"; - clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, - <&gcc GCC_QSPI_CORE_CLK>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <25000000>; - spi-tx-bus-width = <2>; - spi-rx-bus-width = <2>; - }; - }; diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml new file mode 100644 index 000000000000..5c16cf59ca00 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Quad Serial Peripheral Interface (QSPI) + +maintainers: + - Mukesh Savaliya <msavaliy@codeaurora.org> + - Akash Asthana <akashast@codeaurora.org> + +description: + The QSPI controller allows SPI protocol communication in single, dual, or quad + wire transmission modes for read/write access to slaves such as NOR flash. + +allOf: + - $ref: /spi/spi-controller.yaml# + +properties: + compatible: + items: + - const: qcom,sdm845-qspi + - const: qcom,qspi-v1 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-names: + items: + - const: iface + - const: core + + clocks: + items: + - description: AHB clock + - description: QSPI core clock + + interconnects: + minItems: 1 + maxItems: 2 + + interconnect-names: + items: + - const: qspi-config + - const: qspi-memory + +required: + - compatible + - reg + - interrupts + - clock-names + - clocks + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc: soc { + #address-cells = <2>; + #size-cells = <2>; + + qspi: spi@88df000 { + compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; + reg = <0 0x88df000 0 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "iface", "core"; + clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, + <&gcc GCC_QSPI_CORE_CLK>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; + + }; + }; +... diff --git a/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml b/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml index 222990f9923c..930188bc5e6a 100644 --- a/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml +++ b/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml @@ -43,6 +43,9 @@ properties: '#size-cells': const: 1 + ranges: + maxItems: 1 + required: - compatible - reg @@ -51,9 +54,12 @@ required: - clock-names - '#address-cells' - '#size-cells' + - ranges + +additionalProperties: false patternProperties: - "^.+-sram$": + "-sram@[0-9a-f]+$": type: object description: A region of reserved memory. @@ -61,12 +67,8 @@ patternProperties: reg: maxItems: 1 - ranges: - maxItems: 1 - required: - reg - - ranges examples: - | @@ -88,9 +90,9 @@ examples: #address-cells = <1>; #size-cells = <1>; + ranges = <0 0xfec00000 0x100000>; gmu-sram@0 { reg = <0x0 0x100000>; - ranges = <0 0 0xfec00000 0x100000>; }; }; diff --git a/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml b/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml index f761681e4c0d..e43ec50bda37 100644 --- a/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml @@ -32,6 +32,8 @@ properties: description: phandle to the ao-secure syscon $ref: '/schemas/types.yaml#/definitions/phandle' + '#thermal-sensor-cells': + const: 0 required: - compatible @@ -40,6 +42,8 @@ required: - clocks - amlogic,ao-secure +additionalProperties: false + examples: - | cpu_temp: temperature-sensor@ff634800 { diff --git a/Documentation/devicetree/bindings/thermal/armada-thermal.txt b/Documentation/devicetree/bindings/thermal/armada-thermal.txt index f3b441100890..b0bee7e42038 100644 --- a/Documentation/devicetree/bindings/thermal/armada-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/armada-thermal.txt @@ -12,7 +12,7 @@ Required properties: Note: these bindings are deprecated for AP806/CP110 and should instead follow the rules described in: -Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt +Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt - reg: Device's register space. diff --git a/Documentation/devicetree/bindings/thermal/imx8mm-thermal.txt b/Documentation/devicetree/bindings/thermal/imx8mm-thermal.txt new file mode 100644 index 000000000000..3629d3c7e76a --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/imx8mm-thermal.txt @@ -0,0 +1,15 @@ +* Thermal Monitoring Unit (TMU) on Freescale i.MX8MM SoC + +Required properties: +- compatible : Must be "fsl,imx8mm-tmu" or "fsl,imx8mp-tmu". +- reg : Address range of TMU registers. +- clocks : TMU's clock source. +- #thermal-sensor-cells : Should be 0 or 1. See ./thermal.txt for a description. + +Example: +tmu: tmu@30260000 { + compatible = "fsl,imx8mm-tmu"; + reg = <0x30260000 0x10000>; + clocks = <&clk IMX8MM_CLK_TMU_ROOT>; + #thermal-sensor-cells = <0>; +}; diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index eef13b9446a8..2ddd39d96766 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -38,28 +38,39 @@ properties: - enum: - qcom,msm8996-tsens - qcom,msm8998-tsens + - qcom,sc7180-tsens - qcom,sdm845-tsens - const: qcom,tsens-v2 reg: - maxItems: 2 items: - description: TM registers - description: SROT registers + interrupts: + minItems: 1 + items: + - description: Combined interrupt if upper or lower threshold crossed + - description: Interrupt if critical threshold crossed + + interrupt-names: + minItems: 1 + items: + - const: uplow + - const: critical + nvmem-cells: minItems: 1 maxItems: 2 description: Reference to an nvmem node for the calibration data - nvmem-cells-names: + nvmem-cell-names: minItems: 1 maxItems: 2 items: - - enum: - - caldata - - calsel + - const: calib + - const: calib_sel "#qcom,sensors": allOf: @@ -90,22 +101,16 @@ allOf: then: properties: interrupts: - items: - - description: Combined interrupt if upper or lower threshold crossed + maxItems: 1 interrupt-names: - items: - - const: uplow + maxItems: 1 else: properties: interrupts: - items: - - description: Combined interrupt if upper or lower threshold crossed - - description: Interrupt if critical threshold crossed + minItems: 2 interrupt-names: - items: - - const: uplow - - const: critical + minItems: 2 required: - compatible @@ -115,6 +120,8 @@ required: - interrupt-names - "#thermal-sensor-cells" +additionalProperties: false + examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -125,7 +132,7 @@ examples: <0x4a8000 0x1000>; /* SROT */ nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; - nvmem-cell-names = "caldata", "calsel"; + nvmem-cell-names = "calib", "calib_sel"; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow"; diff --git a/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt b/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt index 12c740b975f7..2993fa720195 100644 --- a/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt @@ -11,6 +11,7 @@ Required properties: - "renesas,r8a774b1-thermal" (RZ/G2N) - "renesas,r8a7795-thermal" (R-Car H3) - "renesas,r8a7796-thermal" (R-Car M3-W) + - "renesas,r8a77961-thermal" (R-Car M3-W+) - "renesas,r8a77965-thermal" (R-Car M3-N) - "renesas,r8a77980-thermal" (R-Car V3H) - reg : Address ranges of the thermal registers. Each sensor diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt deleted file mode 100644 index 196112d23b1e..000000000000 --- a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt +++ /dev/null @@ -1,78 +0,0 @@ -* Renesas R-Car Thermal - -Required properties: -- compatible : "renesas,thermal-<soctype>", - "renesas,rcar-gen2-thermal" (with thermal-zone) or - "renesas,rcar-thermal" (without thermal-zone) as - fallback except R-Car V3M/E3/D3 and RZ/G2E. - Examples with soctypes are: - - "renesas,thermal-r8a73a4" (R-Mobile APE6) - - "renesas,thermal-r8a7743" (RZ/G1M) - - "renesas,thermal-r8a7744" (RZ/G1N) - - "renesas,thermal-r8a774c0" (RZ/G2E) - - "renesas,thermal-r8a7779" (R-Car H1) - - "renesas,thermal-r8a7790" (R-Car H2) - - "renesas,thermal-r8a7791" (R-Car M2-W) - - "renesas,thermal-r8a7792" (R-Car V2H) - - "renesas,thermal-r8a7793" (R-Car M2-N) - - "renesas,thermal-r8a77970" (R-Car V3M) - - "renesas,thermal-r8a77990" (R-Car E3) - - "renesas,thermal-r8a77995" (R-Car D3) -- reg : Address range of the thermal registers. - The 1st reg will be recognized as common register - if it has "interrupts". - -Option properties: - -- interrupts : If present should contain 3 interrupts for - R-Car V3M/E3/D3 and RZ/G2E or 1 interrupt otherwise. - -Example (non interrupt support): - -thermal@ffc48000 { - compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal"; - reg = <0xffc48000 0x38>; -}; - -Example (interrupt support): - -thermal@e61f0000 { - compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; - reg = <0xe61f0000 0x14 - 0xe61f0100 0x38 - 0xe61f0200 0x38 - 0xe61f0300 0x38>; - interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; -}; - -Example (with thermal-zone): - -thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <5000>; - - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - }; - }; -}; - -thermal: thermal@e61f0000 { - compatible = "renesas,thermal-r8a7790", - "renesas,rcar-gen2-thermal", - "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; - interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; - power-domains = <&cpg_clocks>; - #thermal-sensor-cells = <0>; -}; diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.yaml b/Documentation/devicetree/bindings/thermal/rcar-thermal.yaml new file mode 100644 index 000000000000..d2f4f1b063ac --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/rcar-thermal.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Copyright (C) 2020 Renesas Electronics Corp. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/rcar-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car Thermal + +maintainers: + - Niklas Söderlund <niklas.soderlund@ragnatech.se> + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,thermal-r8a73a4 # R-Mobile APE6 + - renesas,thermal-r8a7779 # R-Car H1 + - const: renesas,rcar-thermal # Generic without thermal-zone + - items: + - enum: + - renesas,thermal-r8a7743 # RZ/G1M + - renesas,thermal-r8a7744 # RZ/G1N + - const: renesas,rcar-gen2-thermal # Generic thermal-zone + - items: + - enum: + - renesas,thermal-r8a7790 # R-Car H2 + - renesas,thermal-r8a7791 # R-Car M2-W + - renesas,thermal-r8a7792 # R-Car V2H + - renesas,thermal-r8a7793 # R-Car M2-N + - const: renesas,rcar-gen2-thermal # Generic thermal-zone + - const: renesas,rcar-thermal # Generic without thermal-zone + - items: + - enum: + - renesas,thermal-r8a774c0 # RZ/G2E + - renesas,thermal-r8a77970 # R-Car V3M + - renesas,thermal-r8a77990 # R-Car E3 + - renesas,thermal-r8a77995 # R-Car D3 + reg: + description: + Address ranges of the thermal registers. If more then one range is given + the first one must be the common registers followed by each sensor + according the the datasheet. + minItems: 1 + maxItems: 4 + + interrupts: + minItems: 1 + maxItems: 3 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +if: + properties: + compatible: + contains: + enum: + - renesas,thermal-r8a73a4 # R-Mobile APE6 + - renesas,thermal-r8a7779 # R-Car H1 +then: + required: + - compatible + - reg +else: + required: + - compatible + - reg + - interrupts + - clocks + - power-domains + - resets + +examples: + # Example (non interrupt support) + - | + thermal@ffc48000 { + compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal"; + reg = <0xffc48000 0x38>; + }; + + # Example (interrupt support) + - | + #include <dt-bindings/clock/r8a73a4-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + thermal@e61f0000 { + compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; + reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, + <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>; + power-domains = <&pd_c5>; + }; + + # Example (with thermal-zone) + - | + #include <dt-bindings/clock/r8a7790-cpg-mssr.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/r8a7790-sysc.h> + + thermal: thermal@e61f0000 { + compatible = "renesas,thermal-r8a7790", + "renesas,rcar-gen2-thermal", + "renesas,rcar-thermal"; + reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <0>; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + }; + }; + }; diff --git a/Documentation/devicetree/bindings/thermal/sprd-thermal.yaml b/Documentation/devicetree/bindings/thermal/sprd-thermal.yaml new file mode 100644 index 000000000000..058c4cc06ba6 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/sprd-thermal.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/sprd-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Spreadtrum thermal sensor controller bindings + +maintainers: + - Orson Zhai <orsonzhai@gmail.com> + - Baolin Wang <baolin.wang7@gmail.com> + - Chunyan Zhang <zhang.lyra@gmail.com> + +properties: + compatible: + const: sprd,ums512-thermal + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: enable + + nvmem-cells: + maxItems: 2 + description: + Reference to nvmem nodes for the calibration data. + + nvmem-cell-names: + items: + - const: thm_sign_cal + - const: thm_ratio_cal + + "#thermal-sensor-cells": + const: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^([a-z]*-)?sensor(-section)?@[0-9]+$": + type: object + description: + Represent one thermal sensor. + + properties: + reg: + description: Specify the sensor id. + maxItems: 1 + + nvmem-cells: + maxItems: 1 + description: + Reference to an nvmem node for the calibration data. + + nvmem-cell-names: + const: sen_delta_cal + + required: + - reg + - nvmem-cells + - nvmem-cell-names + +required: + - compatible + - reg + - clocks + - clock-names + - nvmem-cells + - nvmem-cell-names + - "#thermal-sensor-cells" + - "#address-cells" + - "#size-cells" + +examples: + - | + ap_thm0: thermal@32200000 { + compatible = "sprd,ums512-thermal"; + reg = <0 0x32200000 0 0x10000>; + clock-names = "enable"; + clocks = <&aonapb_gate 32>; + #thermal-sensor-cells = <1>; + nvmem-cells = <&thm0_sign>, <&thm0_ratio>; + nvmem-cell-names = "thm_sign_cal", "thm_ratio_cal"; + #address-cells = <1>; + #size-cells = <0>; + + prometheus-sensor@0 { + reg = <0>; + nvmem-cells = <&thm0_sen0>; + nvmem-cell-names = "sen_delta_cal"; + }; + + ank-sensor@1 { + reg = <1>; + nvmem-cells = <&thm0_sen1>; + nvmem-cell-names = "sen_delta_cal"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/thermal/thermal.txt b/Documentation/devicetree/bindings/thermal/thermal.txt index ca14ba959e0d..f78bec19ca35 100644 --- a/Documentation/devicetree/bindings/thermal/thermal.txt +++ b/Documentation/devicetree/bindings/thermal/thermal.txt @@ -142,11 +142,11 @@ Required properties: - trips: A sub-node which is a container of only trip point nodes Type: sub-node required to describe the thermal zone. +Optional property: - cooling-maps: A sub-node which is a container of only cooling device Type: sub-node map nodes, used to describe the relation between trips and cooling devices. -Optional property: - coefficients: An array of integers (one signed cell) containing Type: array coefficients to compose a linear relation between Elem size: one cell the sensors listed in the thermal-sensors property. diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml index 6deead07728e..fa255672e8e5 100644 --- a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml +++ b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml @@ -82,6 +82,8 @@ properties: required: - compatible +additionalProperties: false + oneOf: - required: - interrupts diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml index 102f319833d9..582bbef62b95 100644 --- a/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml +++ b/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml @@ -32,6 +32,8 @@ properties: '#size-cells': const: 1 + ranges: true + clock-frequency: description: The frequency of the main counter, in Hz. Should be present only where necessary to work around broken firmware which does not configure @@ -93,6 +95,8 @@ required: - '#address-cells' - '#size-cells' +additionalProperties: false + examples: - | timer@f0000000 { diff --git a/Documentation/devicetree/bindings/timer/arm,global_timer.yaml b/Documentation/devicetree/bindings/timer/arm,global_timer.yaml index 21c24a8e28fd..4956c8f409d2 100644 --- a/Documentation/devicetree/bindings/timer/arm,global_timer.yaml +++ b/Documentation/devicetree/bindings/timer/arm,global_timer.yaml @@ -35,6 +35,8 @@ required: - reg - clocks +additionalProperties: false + examples: - | timer@2c000600 { diff --git a/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml b/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml index 2807225db902..1a721d8af67a 100644 --- a/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml +++ b/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml @@ -32,6 +32,8 @@ required: - reg - interrupts +additionalProperties: false + examples: - | #include <dt-bindings/interrupt-controller/irq.h> diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml index 273e359854dd..37bd01a62c52 100644 --- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml @@ -52,6 +52,8 @@ required: - interrupts - reg +additionalProperties: false + examples: - | // In this example, the IP contains two local timers, using separate diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index 330cab25cc92..4165352a590a 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -34,10 +34,6 @@ properties: - adi,adt7461 # +/-1C TDM Extended Temp Range I.C - adt7461 - # Three-Axis Digital Accelerometer - - adi,adxl345 - # Three-Axis Digital Accelerometer (backward-compatibility value "adi,adxl345" must be listed too) - - adi,adxl346 # AMS iAQ-Core VOC Sensor - ams,iaq-core # i2c serial eeprom (24cxx) @@ -367,4 +363,6 @@ required: - compatible - reg +additionalProperties: false + ... diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml index 6baf00e7d0a9..0d6d850a7f17 100644 --- a/Documentation/devicetree/bindings/usb/dwc2.yaml +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml @@ -32,20 +32,19 @@ properties: - const: lantiq,arx100-usb - const: lantiq,xrx200-usb - items: - - const: amlogic,meson8-usb - - const: snps,dwc2 - - items: - - const: amlogic,meson8b-usb - - const: snps,dwc2 - - const: amlogic,meson-gxbb-usb - - items: - - const: amlogic,meson-g12a-usb + - enum: + - amlogic,meson8-usb + - amlogic,meson8b-usb + - amlogic,meson-gxbb-usb + - amlogic,meson-g12a-usb - const: snps,dwc2 - const: amcc,dwc-otg - const: snps,dwc2 - const: st,stm32f4x9-fsotg - const: st,stm32f4x9-hsotg - const: st,stm32f7-hsotg + - const: st,stm32mp15-fsotg + - const: st,stm32mp15-hsotg - const: samsung,s3c6400-hsotg reg: @@ -91,6 +90,10 @@ properties: vusb_a-supply: description: phandle to voltage regulator of analog section. + vusb33d-supply: + description: reference to the VBUS and ID sensing comparators supply, in + order to perform OTG operation, used on STM32MP15 SoCs. + dr_mode: enum: [host, peripheral, otg] diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt index 66c394f9e11f..6aae1544f240 100644 --- a/Documentation/devicetree/bindings/usb/exynos-usb.txt +++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt @@ -78,7 +78,14 @@ Required properties: - ranges: allows valid 1:1 translation between child's address space and parent's address space - clocks: Clock IDs array as required by the controller. - - clock-names: names of clocks correseponding to IDs in the clock property + - clock-names: Names of clocks corresponding to IDs in the clock property. + Following clock names shall be provided for different + compatibles: + - samsung,exynos5250-dwusb3: "usbdrd30", + - samsung,exynos5433-dwusb3: "aclk", "susp_clk", "pipe_pclk", + "phyclk", + - samsung,exynos7-dwusb3: "usbdrd30", "usbdrd30_susp_clk", + "usbdrd30_axius_clk" - vdd10-supply: 1.0V powr supply - vdd33-supply: 3.0V/3.3V power supply diff --git a/Documentation/devicetree/bindings/usb/fcs,fusb302.txt b/Documentation/devicetree/bindings/usb/fcs,fusb302.txt index ba2e32d500c0..60e4654297af 100644 --- a/Documentation/devicetree/bindings/usb/fcs,fusb302.txt +++ b/Documentation/devicetree/bindings/usb/fcs,fusb302.txt @@ -9,7 +9,7 @@ Required sub-node: - connector : The "usb-c-connector" attached to the FUSB302 IC. The bindings of the connector node are specified in: - Documentation/devicetree/bindings/connector/usb-connector.txt + Documentation/devicetree/bindings/connector/usb-connector.yaml Example: diff --git a/Documentation/devicetree/bindings/usb/generic.txt b/Documentation/devicetree/bindings/usb/generic.txt index 67c51759a642..ba472e7aefc9 100644 --- a/Documentation/devicetree/bindings/usb/generic.txt +++ b/Documentation/devicetree/bindings/usb/generic.txt @@ -34,7 +34,7 @@ Optional properties: - usb-role-switch: boolean, indicates that the device is capable of assigning the USB data role (USB host or USB device) for a given USB connector, such as Type-C, Type-B(micro). - see connector/usb-connector.txt. + see connector/usb-connector.yaml. - role-switch-default-mode: indicating if usb-role-switch is enabled, the device default operation mode of controller while usb role is USB_ROLE_NONE. Valid arguments are "host" and diff --git a/Documentation/devicetree/bindings/usb/ingenic,musb.yaml b/Documentation/devicetree/bindings/usb/ingenic,musb.yaml index 1d6877875077..c2d2ee43ba67 100644 --- a/Documentation/devicetree/bindings/usb/ingenic,musb.yaml +++ b/Documentation/devicetree/bindings/usb/ingenic,musb.yaml @@ -56,7 +56,7 @@ additionalProperties: false examples: - | #include <dt-bindings/clock/jz4740-cgu.h> - usb_phy: usb-phy@0 { + usb_phy: usb-phy { compatible = "usb-nop-xceiv"; #phy-cells = <0>; }; diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt index e0ae6096f7ac..a82ca438aec1 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt +++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt @@ -34,7 +34,7 @@ Optional properties: dual-role mode. it's considered valid for compatibility reasons, not allowed for new bindings, and put into a usb-connector node. - see connector/usb-connector.txt. + see connector/usb-connector.yaml. - pinctrl-names : a pinctrl state named "default" is optional, and need be defined if auto drd switch is enabled, that means the property dr_mode is set as "otg", and meanwhile the property "mediatek,enable-manual-drd" diff --git a/Documentation/devicetree/bindings/usb/mediatek,musb.txt b/Documentation/devicetree/bindings/usb/mediatek,musb.txt index 2b8a87c90d9e..5eedb0296562 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,musb.txt +++ b/Documentation/devicetree/bindings/usb/mediatek,musb.txt @@ -23,7 +23,7 @@ Optional properties: MTCMOS Required child nodes: - usb connector node as defined in bindings/connector/usb-connector.txt + usb connector node as defined in bindings/connector/usb-connector.yaml Optional properties: - id-gpios : input GPIO for USB ID pin. - vbus-gpios : input GPIO for USB VBUS pin. diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml new file mode 100644 index 000000000000..b84ed8ee8cfc --- /dev/null +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml @@ -0,0 +1,190 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/usb/nvidia,tegra-xudc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Device tree binding for NVIDIA Tegra XUSB device mode controller (XUDC) + +description: + The Tegra XUDC controller supports both USB 2.0 HighSpeed/FullSpeed and + USB 3.0 SuperSpeed protocols. + +maintainers: + - Nagarjuna Kristam <nkristam@nvidia.com> + - JC Kuo <jckuo@nvidia.com> + - Thierry Reding <treding@nvidia.com> + +properties: + compatible: + items: + - enum: + - nvidia,tegra210-xudc # For Tegra210 + - nvidia,tegra186-xudc # For Tegra186 + + reg: + minItems: 2 + maxItems: 3 + items: + - description: XUSB device controller registers + - description: XUSB device PCI Config registers + - description: XUSB device registers. + + reg-names: + minItems: 2 + maxItems: 3 + items: + - const: base + - const: fpci + - const: ipfs + + interrupts: + maxItems: 1 + description: Must contain the XUSB device interrupt. + + clocks: + minItems: 4 + maxItems: 5 + items: + - description: Clock to enable core XUSB dev clock. + - description: Clock to enable XUSB super speed clock. + - description: Clock to enable XUSB super speed dev clock. + - description: Clock to enable XUSB high speed dev clock. + - description: Clock to enable XUSB full speed dev clock. + + clock-names: + minItems: 4 + maxItems: 5 + items: + - const: dev + - const: ss + - const: ss_src + - const: fs_src + - const: hs_src + + power-domains: + maxItems: 2 + items: + - description: XUSBB(device) power-domain + - description: XUSBA(superspeed) power-domain + + power-domain-names: + maxItems: 2 + items: + - const: dev + - const: ss + + nvidia,xusb-padctl: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + phandle to the XUSB pad controller that is used to configure the USB pads + used by the XUDC controller. + + phys: + minItems: 1 + description: + Must contain an entry for each entry in phy-names. + See ../phy/phy-bindings.txt for details. + + phy-names: + minItems: 1 + items: + - const: usb2-0 + - const: usb2-1 + - const: usb2-2 + - const: usb2-3 + - const: usb3-0 + - const: usb3-1 + - const: usb3-2 + - const: usb3-3 + + avddio-usb-supply: + description: PCIe/USB3 analog logic power supply. Must supply 1.05 V. + + hvdd-usb-supply: + description: USB controller power supply. Must supply 3.3 V. + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + - clock-names + - power-domains + - power-domain-names + - nvidia,xusb-padctl + - phys + - phy-names + +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra210-xudc + then: + properties: + reg: + minItems: 3 + reg-names: + minItems: 3 + clocks: + minItems: 5 + clock-names: + minItems: 5 + required: + - avddio-usb-supply + - hvdd-usb-supply + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-xudc + then: + properties: + reg: + maxItems: 2 + reg-names: + maxItems: 2 + clocks: + maxItems: 4 + clock-names: + maxItems: 4 + +examples: + - | + #include <dt-bindings/clock/tegra210-car.h> + #include <dt-bindings/gpio/tegra-gpio.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + usb@700d0000 { + compatible = "nvidia,tegra210-xudc"; + reg = <0x0 0x700d0000 0x0 0x8000>, + <0x0 0x700d8000 0x0 0x1000>, + <0x0 0x700d9000 0x0 0x1000>; + reg-names = "base", "fpci", "ipfs"; + + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, + <&tegra_car TEGRA210_CLK_XUSB_SS>, + <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, + <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, + <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; + clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; + + power-domains = <&pd_xusbdev>, <&pd_xusbss>; + power-domain-names = "dev", "ss"; + + nvidia,xusb-padctl = <&padctl>; + + phys = <µ_b>; + phy-names = "usb2-0"; + + avddio-usb-supply = <&vdd_pex_1v05>; + hvdd-usb-supply = <&vdd_3v3_sys>; + }; diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt index cb695aa3fba4..fbdd01756752 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt @@ -52,8 +52,8 @@ A child node must exist to represent the core DWC3 IP block. The name of the node is not important. The content of the node is defined in dwc3.txt. Phy documentation is provided in the following places: -Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt - USB3 QMP PHY -Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt - USB2 QUSB2 PHY +Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt - USB3 QMP PHY +Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml - USB2 QUSB2 PHY Example device nodes: diff --git a/Documentation/devicetree/bindings/usb/richtek,rt1711h.txt b/Documentation/devicetree/bindings/usb/richtek,rt1711h.txt index e3fc57e605ed..6f8115db2ea9 100644 --- a/Documentation/devicetree/bindings/usb/richtek,rt1711h.txt +++ b/Documentation/devicetree/bindings/usb/richtek,rt1711h.txt @@ -9,7 +9,7 @@ Required properties: Required sub-node: - connector: The "usb-c-connector" attached to the tcpci chip, the bindings of connector node are specified in - Documentation/devicetree/bindings/connector/usb-connector.txt + Documentation/devicetree/bindings/connector/usb-connector.yaml Example : rt1711h@4e { diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt index c8c4b00ecb94..94520493233b 100644 --- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt @@ -16,7 +16,7 @@ A child node must exist to represent the core DWC3 IP block. The name of the node is not important. The content of the node is defined in dwc3.txt. Phy documentation is provided in the following places: -Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt - USB2.0 PHY +Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml - USB2.0 PHY Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt - Type-C PHY Example device nodes: diff --git a/Documentation/devicetree/bindings/usb/ti,hd3ss3220.txt b/Documentation/devicetree/bindings/usb/ti,hd3ss3220.txt index 25780e945b15..2bd21b22ce95 100644 --- a/Documentation/devicetree/bindings/usb/ti,hd3ss3220.txt +++ b/Documentation/devicetree/bindings/usb/ti,hd3ss3220.txt @@ -9,7 +9,7 @@ Required sub-node: - connector: The "usb-c-connector" attached to the hd3ss3220 chip. The bindings of the connector node are specified in: - Documentation/devicetree/bindings/connector/usb-connector.txt + Documentation/devicetree/bindings/connector/usb-connector.yaml Example: hd3ss3220@47 { diff --git a/Documentation/devicetree/bindings/usb/typec-tcpci.txt b/Documentation/devicetree/bindings/usb/typec-tcpci.txt index 0dd1469e7318..2082522b1c32 100644 --- a/Documentation/devicetree/bindings/usb/typec-tcpci.txt +++ b/Documentation/devicetree/bindings/usb/typec-tcpci.txt @@ -13,7 +13,7 @@ Required properties: Required sub-node: - connector: The "usb-c-connector" attached to the tcpci chip, the bindings of connector node are specified in - Documentation/devicetree/bindings/connector/usb-connector.txt + Documentation/devicetree/bindings/connector/usb-connector.yaml Example: diff --git a/Documentation/devicetree/bindings/usb/usb-conn-gpio.txt b/Documentation/devicetree/bindings/usb/usb-conn-gpio.txt index 3d05ae56cb0d..ec80641208a5 100644 --- a/Documentation/devicetree/bindings/usb/usb-conn-gpio.txt +++ b/Documentation/devicetree/bindings/usb/usb-conn-gpio.txt @@ -8,11 +8,11 @@ Required properties: - compatible : should include "gpio-usb-b-connector" and "usb-b-connector". - id-gpios, vbus-gpios : input gpios, either one of them must be present, and both can be present as well. - see connector/usb-connector.txt + see connector/usb-connector.yaml Optional properties: - vbus-supply : can be present if needed when supports dual role mode. - see connector/usb-connector.txt + see connector/usb-connector.yaml - Sub-nodes: - port : can be present. diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 49467b58913f..d3891386d671 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -141,6 +141,8 @@ patternProperties: description: Shenzhen AZW Technology Co., Ltd. "^bananapi,.*": description: BIPAI KEJI LIMITED + "^beacon,.*": + description: Compass Electronics Group, LLC "^bhf,.*": description: Beckhoff Automation GmbH & Co. KG "^bitmain,.*": @@ -235,6 +237,8 @@ patternProperties: description: DataImage, Inc. "^davicom,.*": description: DAVICOM Semiconductor, Inc. + "^dell,.*": + description: Dell Inc. "^delta,.*": description: Delta Electronics, Inc. "^denx,.*": @@ -289,6 +293,8 @@ patternProperties: description: Elan Microelectronic Corp. "^elgin,.*": description: Elgin S/A. + "^elida,.*": + description: Shenzhen Elida Technology Co., Ltd. "^embest,.*": description: Shenzhen Embest Technology Co., Ltd. "^emlid,.*": @@ -301,6 +307,8 @@ patternProperties: description: emtrion GmbH "^endless,.*": description: Endless Mobile, Inc. + "^ene,.*": + description: ENE Technology, Inc. "^energymicro,.*": description: Silicon Laboratories (formerly Energy Micro AS) "^engicam,.*": @@ -479,6 +487,8 @@ patternProperties: description: Intersil "^issi,.*": description: Integrated Silicon Solutions Inc. + "^ite,.*": + description: ITE Tech, Inc. "^itead,.*": description: ITEAD Intelligent Systems Co.Ltd "^iwave,.*": @@ -555,6 +565,8 @@ patternProperties: description: LinkSprite Technologies, Inc. "^linksys,.*": description: Belkin International, Inc. (Linksys) + "^linutronix,.*": + description: Linutronix GmbH "^linux,.*": description: Linux-specific binding "^linx,.*": @@ -641,6 +653,9 @@ patternProperties: description: Monolithic Power Systems Inc. "^mqmaker,.*": description: mqmaker Inc. + "^mrvl,.*": + description: Marvell Technology Group Ltd. + deprecated: true "^mscc,.*": description: Microsemi Corporation "^msi,.*": @@ -741,6 +756,8 @@ patternProperties: description: OmniVision Technologies "^oxsemi,.*": description: Oxford Semiconductor, Ltd. + "^ozzmaker,.*": + description: OzzMaker "^panasonic,.*": description: Panasonic Corporation "^parade,.*": @@ -775,6 +792,8 @@ patternProperties: description: Broadcom Corporation (formerly PLX Technology) "^pni,.*": description: PNI Sensor Corporation + "^pocketbook,.*": + description: PocketBook International SA "^polaroid,.*": description: Polaroid Corporation "^portwell,.*": @@ -873,6 +892,8 @@ patternProperties: description: Small Form Factor Committee "^sgd,.*": description: Solomon Goldentek Display Corporation + "^sgmicro,.*": + description: SG Micro Corp "^sgx,.*": description: SGX Sensortech "^sharp,.*": @@ -996,6 +1017,8 @@ patternProperties: "^toppoly,.*": description: TPO (deprecated, use tpo) deprecated: true + "^topwise,.*": + description: Topwise Communication Co., Ltd. "^toradex,.*": description: Toradex AG "^toshiba,.*": @@ -1066,6 +1089,8 @@ patternProperties: description: Vision Optical Technology Co., Ltd. "^vxt,.*": description: VXT Ltd + "^waveshare,.*": + description: Waveshare Electronics "^wd,.*": description: Western Digital Corp. "^wetek,.*": @@ -1092,6 +1117,8 @@ patternProperties: description: X-Powers "^xes,.*": description: Extreme Engineering Solutions (X-ES) + "^xiaomi,.*": + description: Xiaomi Technology Co., Ltd. "^xillybus,.*": description: Xillybus Ltd. "^xinpeng,.*": diff --git a/Documentation/devicetree/bindings/watchdog/st,stpmic1-wdt.txt b/Documentation/devicetree/bindings/watchdog/st,stpmic1-wdt.txt deleted file mode 100644 index 7cc1407f15cb..000000000000 --- a/Documentation/devicetree/bindings/watchdog/st,stpmic1-wdt.txt +++ /dev/null @@ -1,11 +0,0 @@ -STMicroelectronics STPMIC1 Watchdog - -Required properties: - -- compatible : should be "st,stpmic1-wdt" - -Example: - -watchdog { - compatible = "st,stpmic1-wdt"; -}; diff --git a/Documentation/devicetree/bindings/watchdog/ti,rti-wdt.yaml b/Documentation/devicetree/bindings/watchdog/ti,rti-wdt.yaml new file mode 100644 index 000000000000..e83026fef2e9 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/ti,rti-wdt.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/ti,rti-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments K3 SoC Watchdog Timer + +maintainers: + - Tero Kristo <t-kristo@ti.com> + +description: + The TI K3 SoC watchdog timer is implemented via the RTI (Real Time + Interrupt) IP module. This timer adds a support for windowed watchdog + mode, which will signal an error if it is pinged outside the watchdog + time window, meaning either too early or too late. The error signal + generated can be routed to either interrupt a safety controller or + to directly reset the SoC. + +allOf: + - $ref: "watchdog.yaml#" + +properties: + compatible: + enum: + - ti,j7-rti-wdt + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + assigned-clocks: + maxItems: 1 + + assigned-clocks-parents: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - power-domains + +examples: + - | + /* + * RTI WDT in main domain on J721e SoC. Assigned clocks are used to + * select the source clock for the watchdog, forcing it to tick with + * a 32kHz clock in this case. + */ + #include <dt-bindings/soc/ti,sci_pm_domain.h> + + watchdog0: rti@2200000 { + compatible = "ti,rti-wdt"; + reg = <0x0 0x2200000 0x0 0x100>; + clocks = <&k3_clks 252 1>; + power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 252 1>; + assigned-clock-parents = <&k3_clks 252 5>; + }; diff --git a/Documentation/driver-api/gpio/driver.rst b/Documentation/driver-api/gpio/driver.rst index 871922529332..9809f593c0ab 100644 --- a/Documentation/driver-api/gpio/driver.rst +++ b/Documentation/driver-api/gpio/driver.rst @@ -416,7 +416,7 @@ The preferred way to set up the helpers is to fill in the struct gpio_irq_chip inside struct gpio_chip before adding the gpio_chip. If you do this, the additional irq_chip will be set up by gpiolib at the same time as setting up the rest of the GPIO functionality. The following -is a typical example of a cascaded interrupt handler using gpio_irq_chip:: +is a typical example of a cascaded interrupt handler using gpio_irq_chip: .. code-block:: c @@ -453,7 +453,7 @@ is a typical example of a cascaded interrupt handler using gpio_irq_chip:: return devm_gpiochip_add_data(dev, &g->gc, g); The helper support using hierarchical interrupt controllers as well. -In this case the typical set-up will look like this:: +In this case the typical set-up will look like this: .. code-block:: c diff --git a/Documentation/driver-api/libata.rst b/Documentation/driver-api/libata.rst index 207f0d24de69..e2f87b82b074 100644 --- a/Documentation/driver-api/libata.rst +++ b/Documentation/driver-api/libata.rst @@ -401,7 +401,7 @@ Error handling ============== This chapter describes how errors are handled under libata. Readers are -advised to read SCSI EH (Documentation/scsi/scsi_eh.txt) and ATA +advised to read SCSI EH (Documentation/scsi/scsi_eh.rst) and ATA exceptions doc first. Origins of commands diff --git a/Documentation/driver-api/soundwire/stream.rst b/Documentation/driver-api/soundwire/stream.rst index 5351bd2f34a8..8bceece51554 100644 --- a/Documentation/driver-api/soundwire/stream.rst +++ b/Documentation/driver-api/soundwire/stream.rst @@ -156,22 +156,27 @@ Below shows the SoundWire stream states and state transition diagram. :: +-----------+ +------------+ +----------+ +----------+ | ALLOCATED +---->| CONFIGURED +---->| PREPARED +---->| ENABLED | | STATE | | STATE | | STATE | | STATE | - +-----------+ +------------+ +----------+ +----+-----+ - ^ - | - | - v - +----------+ +------------+ +----+-----+ + +-----------+ +------------+ +---+--+---+ +----+-----+ + ^ ^ ^ + | | | + __| |___________ | + | | | + v | v + +----------+ +-----+------+ +-+--+-----+ | RELEASED |<----------+ DEPREPARED |<-------+ DISABLED | | STATE | | STATE | | STATE | +----------+ +------------+ +----------+ -NOTE: State transition between prepare and deprepare is supported in Spec -but not in the software (subsystem) +NOTE: State transitions between ``SDW_STREAM_ENABLED`` and +``SDW_STREAM_DISABLED`` are only relevant when then INFO_PAUSE flag is +supported at the ALSA/ASoC level. Likewise the transition between +``SDW_DISABLED_STATE`` and ``SDW_PREPARED_STATE`` depends on the +INFO_RESUME flag. -NOTE2: Stream state transition checks need to be handled by caller -framework, for example ALSA/ASoC. No checks for stream transition exist in -SoundWire subsystem. +NOTE2: The framework implements basic state transition checks, but +does not e.g. check if a transition from DISABLED to ENABLED is valid +on a specific platform. Such tests need to be added at the ALSA/ASoC +level. Stream State Operations ----------------------- @@ -246,6 +251,9 @@ SDW_STREAM_PREPARED Prepare state of stream. Operations performed before entering in this state: + (0) Steps 1 and 2 are omitted in the case of a resume operation, + where the bus bandwidth is known. + (1) Bus parameters such as bandwidth, frame shape, clock frequency, are computed based on current stream as well as already active stream(s) on Bus. Re-computation is required to accommodate current @@ -270,9 +278,11 @@ Prepare state of stream. Operations performed before entering in this state: After all above operations are successful, stream state is set to ``SDW_STREAM_PREPARED``. -Bus implements below API for PREPARE state which needs to be called once per -stream. From ASoC DPCM framework, this stream state is linked to -.prepare() operation. +Bus implements below API for PREPARE state which needs to be called +once per stream. From ASoC DPCM framework, this stream state is linked +to .prepare() operation. Since the .trigger() operations may not +follow the .prepare(), a direct transition from +``SDW_STREAM_PREPARED`` to ``SDW_STREAM_DEPREPARED`` is allowed. .. code-block:: c @@ -332,6 +342,14 @@ Bus implements below API for DISABLED state which needs to be called once per stream. From ASoC DPCM framework, this stream state is linked to .trigger() stop operation. +When the INFO_PAUSE flag is supported, a direct transition to +``SDW_STREAM_ENABLED`` is allowed. + +For resume operations where ASoC will use the .prepare() callback, the +stream can transition from ``SDW_STREAM_DISABLED`` to +``SDW_STREAM_PREPARED``, with all required settings restored but +without updating the bandwidth and bit allocation. + .. code-block:: c int sdw_disable_stream(struct sdw_stream_runtime * stream); @@ -353,9 +371,18 @@ state: After all above operations are successful, stream state is set to ``SDW_STREAM_DEPREPARED``. -Bus implements below API for DEPREPARED state which needs to be called once -per stream. From ASoC DPCM framework, this stream state is linked to -.trigger() stop operation. +Bus implements below API for DEPREPARED state which needs to be called +once per stream. ALSA/ASoC do not have a concept of 'deprepare', and +the mapping from this stream state to ALSA/ASoC operation may be +implementation specific. + +When the INFO_PAUSE flag is supported, the stream state is linked to +the .hw_free() operation - the stream is not deprepared on a +TRIGGER_STOP. + +Other implementations may transition to the ``SDW_STREAM_DEPREPARED`` +state on TRIGGER_STOP, should they require a transition through the +``SDW_STREAM_PREPARED`` state. .. code-block:: c diff --git a/Documentation/driver-api/thermal/cpu-idle-cooling.rst b/Documentation/driver-api/thermal/cpu-idle-cooling.rst index 9f0016ee4cfb..a1c3edecae00 100644 --- a/Documentation/driver-api/thermal/cpu-idle-cooling.rst +++ b/Documentation/driver-api/thermal/cpu-idle-cooling.rst @@ -105,8 +105,8 @@ and this variation will modulate the cooling effect. idle <--------------> running - <-----------------------------> - duty cycle 33% + <---------------------> + duty cycle 33% ^ diff --git a/Documentation/driver-api/usb/writing_usb_driver.rst b/Documentation/driver-api/usb/writing_usb_driver.rst index 4fe1c06b6a13..0b3d9ff221bb 100644 --- a/Documentation/driver-api/usb/writing_usb_driver.rst +++ b/Documentation/driver-api/usb/writing_usb_driver.rst @@ -314,11 +314,8 @@ http://www.linux-usb.org/ Linux Hotplug Project: http://linux-hotplug.sourceforge.net/ -Linux USB Working Devices List: -http://www.qbik.ch/usb/devices/ - -linux-usb-devel Mailing List Archives: -http://marc.theaimsgroup.com/?l=linux-usb-devel +linux-usb Mailing List Archives: +https://lore.kernel.org/linux-usb/ Programming Guide for Linux USB Device Drivers: http://lmu.web.psi.ch/docu/manuals/software_manuals/linux_sl/usb_linux_programming_guide.pdf diff --git a/Documentation/driver-api/w1.rst b/Documentation/driver-api/w1.rst index 9963cca788a1..bda3ad60f655 100644 --- a/Documentation/driver-api/w1.rst +++ b/Documentation/driver-api/w1.rst @@ -7,9 +7,6 @@ W1: Dallas' 1-wire bus W1 API internal to the kernel ============================= -W1 API internal to the kernel ------------------------------ - include/linux/w1.h ~~~~~~~~~~~~~~~~~~ diff --git a/Documentation/filesystems/9p.rst b/Documentation/filesystems/9p.rst index f054d1c45e86..671fef39a802 100644 --- a/Documentation/filesystems/9p.rst +++ b/Documentation/filesystems/9p.rst @@ -158,6 +158,16 @@ Options /sys/fs/9p/caches. (applies only to cache=fscache) ============= =============================================================== +Behavior +======== + +This section aims at describing 9p 'quirks' that can be different +from a local filesystem behaviors. + + - Setting O_NONBLOCK on a file will make client reads return as early + as the server returns some data instead of trying to fill the read + buffer with the requested amount of bytes or end of file is reached. + Resources ========= diff --git a/Documentation/filesystems/ceph.rst b/Documentation/filesystems/ceph.rst index b46a7218248f..0aa70750df0f 100644 --- a/Documentation/filesystems/ceph.rst +++ b/Documentation/filesystems/ceph.rst @@ -107,17 +107,17 @@ Mount Options address its connection to the monitor originates from. wsize=X - Specify the maximum write size in bytes. Default: 16 MB. + Specify the maximum write size in bytes. Default: 64 MB. rsize=X - Specify the maximum read size in bytes. Default: 16 MB. + Specify the maximum read size in bytes. Default: 64 MB. rasize=X Specify the maximum readahead size in bytes. Default: 8 MB. mount_timeout=X Specify the timeout value for mount (in seconds), in the case - of a non-responsive Ceph file system. The default is 30 + of a non-responsive Ceph file system. The default is 60 seconds. caps_max=X diff --git a/Documentation/filesystems/f2fs.rst b/Documentation/filesystems/f2fs.rst index d681203728d7..87d794bc75a4 100644 --- a/Documentation/filesystems/f2fs.rst +++ b/Documentation/filesystems/f2fs.rst @@ -243,8 +243,8 @@ checkpoint=%s[:%u[%]] Set to "disable" to turn off checkpointing. Set to "enabl hide up to all remaining free space. The actual space that would be unusable can be viewed at /sys/fs/f2fs/<disk>/unusable This space is reclaimed once checkpoint=enable. -compress_algorithm=%s Control compress algorithm, currently f2fs supports "lzo" - and "lz4" algorithm. +compress_algorithm=%s Control compress algorithm, currently f2fs supports "lzo", + "lz4" and "zstd" algorithm. compress_log_size=%u Support configuring compress cluster size, the size will be 4KB * (1 << %u), 16KB is minimum size, also it's default size. diff --git a/Documentation/filesystems/fiemap.txt b/Documentation/filesystems/fiemap.txt index f6d9c99103a4..ac87e6fda842 100644 --- a/Documentation/filesystems/fiemap.txt +++ b/Documentation/filesystems/fiemap.txt @@ -115,8 +115,10 @@ data. Note that the opposite is not true - it would be valid for FIEMAP_EXTENT_NOT_ALIGNED to appear alone. * FIEMAP_EXTENT_LAST -This is the last extent in the file. A mapping attempt past this -extent will return nothing. +This is generally the last extent in the file. A mapping attempt past +this extent may return nothing. Some implementations set this flag to +indicate this extent is the last one in the range queried by the user +(via fiemap->fm_length). * FIEMAP_EXTENT_UNKNOWN The location of this extent is currently unknown. This may indicate diff --git a/Documentation/filesystems/orangefs.rst b/Documentation/filesystems/orangefs.rst index 7d6d4cad73c4..e41369709c5b 100644 --- a/Documentation/filesystems/orangefs.rst +++ b/Documentation/filesystems/orangefs.rst @@ -41,16 +41,6 @@ Documentation http://www.orangefs.org/documentation/ - -Userspace Filesystem Source -=========================== - -http://www.orangefs.org/download - -Orangefs versions prior to 2.9.3 would not be compatible with the -upstream version of the kernel client. - - Running ORANGEFS On a Single Server =================================== @@ -94,6 +84,14 @@ Mount the filesystem:: mount -t pvfs2 tcp://localhost:3334/orangefs /pvfsmnt +Userspace Filesystem Source +=========================== + +http://www.orangefs.org/download + +Orangefs versions prior to 2.9.3 would not be compatible with the +upstream version of the kernel client. + Building ORANGEFS on a Single Server ==================================== @@ -107,18 +105,24 @@ default, we will probably be changing the default to LMDB soon. :: - ./configure --prefix=/opt/ofs --with-db-backend=lmdb + ./configure --prefix=/opt/ofs --with-db-backend=lmdb --disable-usrint make make install -Create an orangefs config file:: +Create an orangefs config file by running pvfs2-genconfig and +specifying a target config file. Pvfs2-genconfig will prompt you +through. Generally it works fine to take the defaults, but you +should use your server's hostname, rather than "localhost" when +it comes to that question:: /opt/ofs/bin/pvfs2-genconfig /etc/pvfs2.conf Create an /etc/pvfs2tab file:: +Localhost is fine for your pvfs2tab file: + echo tcp://localhost:3334/orangefs /pvfsmnt pvfs2 defaults,noauto 0 0 > \ /etc/pvfs2tab @@ -132,7 +136,7 @@ Bootstrap the server:: Start the server:: - /opt/osf/sbin/pvfs2-server /etc/pvfs2.conf + /opt/ofs/sbin/pvfs2-server /etc/pvfs2.conf Now the server should be running. Pvfs2-ls is a simple test to verify that the server is running:: @@ -142,11 +146,11 @@ test to verify that the server is running:: If stuff seems to be working, load the kernel module and turn on the client core:: - /opt/ofs/sbin/pvfs2-client -p /opt/osf/sbin/pvfs2-client-core + /opt/ofs/sbin/pvfs2-client -p /opt/ofs/sbin/pvfs2-client-core Mount your filesystem:: - mount -t pvfs2 tcp://localhost:3334/orangefs /pvfsmnt + mount -t pvfs2 tcp://`hostname`:3334/orangefs /pvfsmnt Running xfstests diff --git a/Documentation/filesystems/overlayfs.rst b/Documentation/filesystems/overlayfs.rst index e443be7928db..c9d2bf96b02d 100644 --- a/Documentation/filesystems/overlayfs.rst +++ b/Documentation/filesystems/overlayfs.rst @@ -40,13 +40,46 @@ On 64bit systems, even if all overlay layers are not on the same underlying filesystem, the same compliant behavior could be achieved with the "xino" feature. The "xino" feature composes a unique object identifier from the real object st_ino and an underlying fsid index. + If all underlying filesystems support NFS file handles and export file handles with 32bit inode number encoding (e.g. ext4), overlay filesystem will use the high inode number bits for fsid. Even when the underlying filesystem uses 64bit inode numbers, users can still enable the "xino" feature with the "-o xino=on" overlay mount option. That is useful for the case of underlying filesystems like xfs and tmpfs, which use 64bit inode -numbers, but are very unlikely to use the high inode number bit. +numbers, but are very unlikely to use the high inode number bits. In case +the underlying inode number does overflow into the high xino bits, overlay +filesystem will fall back to the non xino behavior for that inode. + +The following table summarizes what can be expected in different overlay +configurations. + +Inode properties +```````````````` + ++--------------+------------+------------+-----------------+----------------+ +|Configuration | Persistent | Uniform | st_ino == d_ino | d_ino == i_ino | +| | st_ino | st_dev | | [*] | ++==============+=====+======+=====+======+========+========+========+=======+ +| | dir | !dir | dir | !dir | dir + !dir | dir | !dir | ++--------------+-----+------+-----+------+--------+--------+--------+-------+ +| All layers | Y | Y | Y | Y | Y | Y | Y | Y | +| on same fs | | | | | | | | | ++--------------+-----+------+-----+------+--------+--------+--------+-------+ +| Layers not | N | Y | Y | N | N | Y | N | Y | +| on same fs, | | | | | | | | | +| xino=off | | | | | | | | | ++--------------+-----+------+-----+------+--------+--------+--------+-------+ +| xino=on/auto | Y | Y | Y | Y | Y | Y | Y | Y | +| | | | | | | | | | ++--------------+-----+------+-----+------+--------+--------+--------+-------+ +| xino=on/auto,| N | Y | Y | N | N | Y | N | Y | +| ino overflow | | | | | | | | | ++--------------+-----+------+-----+------+--------+--------+--------+-------+ + +[*] nfsd v3 readdirplus verifies d_ino == i_ino. i_ino is exposed via several +/proc files, such as /proc/locks and /proc/self/fdinfo/<fd> of an inotify +file descriptor. Upper and Lower @@ -248,6 +281,50 @@ overlay filesystem (though an operation on the name of the file such as rename or unlink will of course be noticed and handled). +Permission model +---------------- + +Permission checking in the overlay filesystem follows these principles: + + 1) permission check SHOULD return the same result before and after copy up + + 2) task creating the overlay mount MUST NOT gain additional privileges + + 3) non-mounting task MAY gain additional privileges through the overlay, + compared to direct access on underlying lower or upper filesystems + +This is achieved by performing two permission checks on each access + + a) check if current task is allowed access based on local DAC (owner, + group, mode and posix acl), as well as MAC checks + + b) check if mounting task would be allowed real operation on lower or + upper layer based on underlying filesystem permissions, again including + MAC checks + +Check (a) ensures consistency (1) since owner, group, mode and posix acls +are copied up. On the other hand it can result in server enforced +permissions (used by NFS, for example) being ignored (3). + +Check (b) ensures that no task gains permissions to underlying layers that +the mounting task does not have (2). This also means that it is possible +to create setups where the consistency rule (1) does not hold; normally, +however, the mounting task will have sufficient privileges to perform all +operations. + +Another way to demonstrate this model is drawing parallels between + + mount -t overlay overlay -olowerdir=/lower,upperdir=/upper,... /merged + +and + + cp -a /lower /upper + mount --bind /upper /merged + +The resulting access permissions should be the same. The difference is in +the time of copy (on-demand vs. up-front). + + Multiple lower layers --------------------- @@ -383,7 +460,8 @@ guarantee that the values of st_ino and st_dev returned by stat(2) and the value of d_ino returned by readdir(3) will act like on a normal filesystem. E.g. the value of st_dev may be different for two objects in the same overlay filesystem and the value of st_ino for directory objects may not be -persistent and could change even while the overlay filesystem is mounted. +persistent and could change even while the overlay filesystem is mounted, as +summarized in the `Inode properties`_ table above. Changes to underlying filesystems diff --git a/Documentation/filesystems/qnx6.rst b/Documentation/filesystems/qnx6.rst index b71308314070..fd13433d362c 100644 --- a/Documentation/filesystems/qnx6.rst +++ b/Documentation/filesystems/qnx6.rst @@ -185,7 +185,7 @@ tree structures are treated as system blocks. The rational behind that is that a write request can work on a new snapshot (system area of the inactive - resp. lower serial numbered superblock) while -at the same time there is still a complete stable filesystem structer in the +at the same time there is still a complete stable filesystem structure in the other half of the system area. When finished with writing (a sync write is completed, the maximum sync leap diff --git a/Documentation/firmware-guide/acpi/namespace.rst b/Documentation/firmware-guide/acpi/namespace.rst index 3eb763d6656d..6193582a2204 100644 --- a/Documentation/firmware-guide/acpi/namespace.rst +++ b/Documentation/firmware-guide/acpi/namespace.rst @@ -56,13 +56,13 @@ are illustrated in the following diagram:: +- - - -+ | +-------------------| | | Entry | - - - - - - - -+ | | Definition Blocks | | +- - - -+ | | +-------------------+ | - | | +- - - - - - - - - -+ | - +-|->| SSDT | | + | | +- - - - - - - - - -+ | + +-|->| SSDT | | | +-------------------+ | | | Definition Blocks | | | +- - - - - - - - - -+ | +------------------------+ - | + | OSPM Loading | \|/ +----------------+ diff --git a/Documentation/hwmon/isl68137.rst b/Documentation/hwmon/isl68137.rst index cc4b61447b63..0e71b22047f8 100644 --- a/Documentation/hwmon/isl68137.rst +++ b/Documentation/hwmon/isl68137.rst @@ -16,7 +16,7 @@ Supported chips: * Renesas ISL68220 - Prefix: 'raa_dmpvr2_2rail' + Prefix: 'isl68220' Addresses scanned: - @@ -26,7 +26,7 @@ Supported chips: * Renesas ISL68221 - Prefix: 'raa_dmpvr2_3rail' + Prefix: 'isl68221' Addresses scanned: - @@ -36,7 +36,7 @@ Supported chips: * Renesas ISL68222 - Prefix: 'raa_dmpvr2_2rail' + Prefix: 'isl68222' Addresses scanned: - @@ -46,7 +46,7 @@ Supported chips: * Renesas ISL68223 - Prefix: 'raa_dmpvr2_2rail' + Prefix: 'isl68223' Addresses scanned: - @@ -56,7 +56,7 @@ Supported chips: * Renesas ISL68224 - Prefix: 'raa_dmpvr2_3rail' + Prefix: 'isl68224' Addresses scanned: - @@ -66,7 +66,7 @@ Supported chips: * Renesas ISL68225 - Prefix: 'raa_dmpvr2_2rail' + Prefix: 'isl68225' Addresses scanned: - @@ -76,7 +76,7 @@ Supported chips: * Renesas ISL68226 - Prefix: 'raa_dmpvr2_3rail' + Prefix: 'isl68226' Addresses scanned: - @@ -86,7 +86,7 @@ Supported chips: * Renesas ISL68227 - Prefix: 'raa_dmpvr2_1rail' + Prefix: 'isl68227' Addresses scanned: - @@ -96,7 +96,7 @@ Supported chips: * Renesas ISL68229 - Prefix: 'raa_dmpvr2_3rail' + Prefix: 'isl68229' Addresses scanned: - @@ -106,7 +106,7 @@ Supported chips: * Renesas ISL68233 - Prefix: 'raa_dmpvr2_2rail' + Prefix: 'isl68233' Addresses scanned: - @@ -116,7 +116,7 @@ Supported chips: * Renesas ISL68239 - Prefix: 'raa_dmpvr2_3rail' + Prefix: 'isl68239' Addresses scanned: - @@ -126,7 +126,7 @@ Supported chips: * Renesas ISL69222 - Prefix: 'raa_dmpvr2_2rail' + Prefix: 'isl69222' Addresses scanned: - @@ -136,7 +136,7 @@ Supported chips: * Renesas ISL69223 - Prefix: 'raa_dmpvr2_3rail' + Prefix: 'isl69223' Addresses scanned: - @@ -146,7 +146,7 @@ Supported chips: * Renesas ISL69224 - Prefix: 'raa_dmpvr2_2rail' + Prefix: 'isl69224' Addresses scanned: - @@ -156,7 +156,7 @@ Supported chips: * Renesas ISL69225 - Prefix: 'raa_dmpvr2_2rail' + Prefix: 'isl69225' Addresses scanned: - @@ -166,7 +166,7 @@ Supported chips: * Renesas ISL69227 - Prefix: 'raa_dmpvr2_3rail' + Prefix: 'isl69227' Addresses scanned: - @@ -176,7 +176,7 @@ Supported chips: * Renesas ISL69228 - Prefix: 'raa_dmpvr2_3rail' + Prefix: 'isl69228' Addresses scanned: - @@ -186,7 +186,7 @@ Supported chips: * Renesas ISL69234 - Prefix: 'raa_dmpvr2_2rail' + Prefix: 'isl69234' Addresses scanned: - @@ -196,7 +196,7 @@ Supported chips: * Renesas ISL69236 - Prefix: 'raa_dmpvr2_2rail' + Prefix: 'isl69236' Addresses scanned: - @@ -206,7 +206,7 @@ Supported chips: * Renesas ISL69239 - Prefix: 'raa_dmpvr2_3rail' + Prefix: 'isl69239' Addresses scanned: - @@ -216,7 +216,7 @@ Supported chips: * Renesas ISL69242 - Prefix: 'raa_dmpvr2_2rail' + Prefix: 'isl69242' Addresses scanned: - @@ -226,7 +226,7 @@ Supported chips: * Renesas ISL69243 - Prefix: 'raa_dmpvr2_1rail' + Prefix: 'isl69243' Addresses scanned: - @@ -236,7 +236,7 @@ Supported chips: * Renesas ISL69247 - Prefix: 'raa_dmpvr2_2rail' + Prefix: 'isl69247' Addresses scanned: - @@ -246,7 +246,7 @@ Supported chips: * Renesas ISL69248 - Prefix: 'raa_dmpvr2_2rail' + Prefix: 'isl69248' Addresses scanned: - @@ -256,7 +256,7 @@ Supported chips: * Renesas ISL69254 - Prefix: 'raa_dmpvr2_2rail' + Prefix: 'isl69254' Addresses scanned: - @@ -266,7 +266,7 @@ Supported chips: * Renesas ISL69255 - Prefix: 'raa_dmpvr2_2rail' + Prefix: 'isl69255' Addresses scanned: - @@ -276,7 +276,7 @@ Supported chips: * Renesas ISL69256 - Prefix: 'raa_dmpvr2_2rail' + Prefix: 'isl69256' Addresses scanned: - @@ -286,7 +286,7 @@ Supported chips: * Renesas ISL69259 - Prefix: 'raa_dmpvr2_2rail' + Prefix: 'isl69259' Addresses scanned: - @@ -296,7 +296,7 @@ Supported chips: * Renesas ISL69260 - Prefix: 'raa_dmpvr2_2rail' + Prefix: 'isl69260' Addresses scanned: - @@ -306,7 +306,7 @@ Supported chips: * Renesas ISL69268 - Prefix: 'raa_dmpvr2_2rail' + Prefix: 'isl69268' Addresses scanned: - @@ -316,7 +316,7 @@ Supported chips: * Renesas ISL69269 - Prefix: 'raa_dmpvr2_3rail' + Prefix: 'isl69269' Addresses scanned: - @@ -326,7 +326,7 @@ Supported chips: * Renesas ISL69298 - Prefix: 'raa_dmpvr2_2rail' + Prefix: 'isl69298' Addresses scanned: - @@ -336,7 +336,7 @@ Supported chips: * Renesas RAA228000 - Prefix: 'raa_dmpvr2_hv' + Prefix: 'raa228000' Addresses scanned: - @@ -346,7 +346,7 @@ Supported chips: * Renesas RAA228004 - Prefix: 'raa_dmpvr2_hv' + Prefix: 'raa228004' Addresses scanned: - @@ -356,7 +356,7 @@ Supported chips: * Renesas RAA228006 - Prefix: 'raa_dmpvr2_hv' + Prefix: 'raa228006' Addresses scanned: - @@ -366,7 +366,7 @@ Supported chips: * Renesas RAA228228 - Prefix: 'raa_dmpvr2_2rail' + Prefix: 'raa228228' Addresses scanned: - @@ -376,7 +376,7 @@ Supported chips: * Renesas RAA229001 - Prefix: 'raa_dmpvr2_2rail' + Prefix: 'raa229001' Addresses scanned: - @@ -386,7 +386,7 @@ Supported chips: * Renesas RAA229004 - Prefix: 'raa_dmpvr2_2rail' + Prefix: 'raa229004' Addresses scanned: - diff --git a/Documentation/i2c/smbus-protocol.rst b/Documentation/i2c/smbus-protocol.rst index c122ed239f7f..c2e29633071e 100644 --- a/Documentation/i2c/smbus-protocol.rst +++ b/Documentation/i2c/smbus-protocol.rst @@ -274,7 +274,7 @@ to know which slave triggered the interrupt. This is implemented the following way in the Linux kernel: * I2C bus drivers which support SMBus alert should call - i2c_setup_smbus_alert() to setup SMBus alert support. + i2c_new_smbus_alert_device() to install SMBus alert support. * I2C drivers for devices which can trigger SMBus alerts should implement the optional alert() callback. diff --git a/Documentation/index.rst b/Documentation/index.rst index 9df95bab4de8..9599c0f3eea8 100644 --- a/Documentation/index.rst +++ b/Documentation/index.rst @@ -131,8 +131,10 @@ needed). bpf/index usb/index PCI/index + scsi/index misc-devices/index scheduler/index + mhi/index Architecture-agnostic documentation ----------------------------------- diff --git a/Documentation/kbuild/kbuild.rst b/Documentation/kbuild/kbuild.rst index 510f38d7e78a..2d1fc03d346e 100644 --- a/Documentation/kbuild/kbuild.rst +++ b/Documentation/kbuild/kbuild.rst @@ -262,3 +262,8 @@ KBUILD_BUILD_USER, KBUILD_BUILD_HOST These two variables allow to override the user@host string displayed during boot and in /proc/version. The default value is the output of the commands whoami and host, respectively. + +LLVM +---- +If this variable is set to 1, Kbuild will use Clang and LLVM utilities instead +of GCC and GNU binutils to build the kernel. diff --git a/Documentation/kbuild/llvm.rst b/Documentation/kbuild/llvm.rst index d6c79eb4e23e..c776b6eee969 100644 --- a/Documentation/kbuild/llvm.rst +++ b/Documentation/kbuild/llvm.rst @@ -47,14 +47,21 @@ example: LLVM Utilities -------------- -LLVM has substitutes for GNU binutils utilities. These can be invoked as -additional parameters to `make`. +LLVM has substitutes for GNU binutils utilities. Kbuild supports `LLVM=1` +to enable them. - make CC=clang AS=clang LD=ld.lld AR=llvm-ar NM=llvm-nm STRIP=llvm-strip \\ - OBJCOPY=llvm-objcopy OBJDUMP=llvm-objdump OBJSIZE=llvm-objsize \\ + make LLVM=1 + +They can be enabled individually. The full list of the parameters: + + make CC=clang LD=ld.lld AR=llvm-ar NM=llvm-nm STRIP=llvm-strip \\ + OBJCOPY=llvm-objcopy OBJDUMP=llvm-objdump OBJSIZE=llvm-size \\ READELF=llvm-readelf HOSTCC=clang HOSTCXX=clang++ HOSTAR=llvm-ar \\ HOSTLD=ld.lld +Currently, the integrated assembler is disabled by default. You can pass +`LLVM_IAS=1` to enable it. + Getting Help ------------ diff --git a/Documentation/mhi/index.rst b/Documentation/mhi/index.rst new file mode 100644 index 000000000000..1d8dec302780 --- /dev/null +++ b/Documentation/mhi/index.rst @@ -0,0 +1,18 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=== +MHI +=== + +.. toctree:: + :maxdepth: 1 + + mhi + topology + +.. only:: subproject and html + + Indices + ======= + + * :ref:`genindex` diff --git a/Documentation/mhi/mhi.rst b/Documentation/mhi/mhi.rst new file mode 100644 index 000000000000..803ff84f7d7b --- /dev/null +++ b/Documentation/mhi/mhi.rst @@ -0,0 +1,218 @@ +.. SPDX-License-Identifier: GPL-2.0 + +========================== +MHI (Modem Host Interface) +========================== + +This document provides information about the MHI protocol. + +Overview +======== + +MHI is a protocol developed by Qualcomm Innovation Center, Inc. It is used +by the host processors to control and communicate with modem devices over high +speed peripheral buses or shared memory. Even though MHI can be easily adapted +to any peripheral buses, it is primarily used with PCIe based devices. MHI +provides logical channels over the physical buses and allows transporting the +modem protocols, such as IP data packets, modem control messages, and +diagnostics over at least one of those logical channels. Also, the MHI +protocol provides data acknowledgment feature and manages the power state of the +modems via one or more logical channels. + +MHI Internals +============= + +MMIO +---- + +MMIO (Memory mapped IO) consists of a set of registers in the device hardware, +which are mapped to the host memory space by the peripheral buses like PCIe. +Following are the major components of MMIO register space: + +MHI control registers: Access to MHI configurations registers + +MHI BHI registers: BHI (Boot Host Interface) registers are used by the host +for downloading the firmware to the device before MHI initialization. + +Channel Doorbell array: Channel Doorbell (DB) registers used by the host to +notify the device when there is new work to do. + +Event Doorbell array: Associated with event context array, the Event Doorbell +(DB) registers are used by the host to notify the device when new events are +available. + +Debug registers: A set of registers and counters used by the device to expose +debugging information like performance, functional, and stability to the host. + +Data structures +--------------- + +All data structures used by MHI are in the host system memory. Using the +physical interface, the device accesses those data structures. MHI data +structures and data buffers in the host system memory regions are mapped for +the device. + +Channel context array: All channel configurations are organized in channel +context data array. + +Transfer rings: Used by the host to schedule work items for a channel. The +transfer rings are organized as a circular queue of Transfer Descriptors (TD). + +Event context array: All event configurations are organized in the event context +data array. + +Event rings: Used by the device to send completion and state transition messages +to the host + +Command context array: All command configurations are organized in command +context data array. + +Command rings: Used by the host to send MHI commands to the device. The command +rings are organized as a circular queue of Command Descriptors (CD). + +Channels +-------- + +MHI channels are logical, unidirectional data pipes between a host and a device. +The concept of channels in MHI is similar to endpoints in USB. MHI supports up +to 256 channels. However, specific device implementations may support less than +the maximum number of channels allowed. + +Two unidirectional channels with their associated transfer rings form a +bidirectional data pipe, which can be used by the upper-layer protocols to +transport application data packets (such as IP packets, modem control messages, +diagnostics messages, and so on). Each channel is associated with a single +transfer ring. + +Transfer rings +-------------- + +Transfers between the host and device are organized by channels and defined by +Transfer Descriptors (TD). TDs are managed through transfer rings, which are +defined for each channel between the device and host and reside in the host +memory. TDs consist of one or more ring elements (or transfer blocks):: + + [Read Pointer (RP)] ----------->[Ring Element] } TD + [Write Pointer (WP)]- [Ring Element] + - [Ring Element] + --------->[Ring Element] + [Ring Element] + +Below is the basic usage of transfer rings: + +* Host allocates memory for transfer ring. +* Host sets the base pointer, read pointer, and write pointer in corresponding + channel context. +* Ring is considered empty when RP == WP. +* Ring is considered full when WP + 1 == RP. +* RP indicates the next element to be serviced by the device. +* When the host has a new buffer to send, it updates the ring element with + buffer information, increments the WP to the next element and rings the + associated channel DB. + +Event rings +----------- + +Events from the device to host are organized in event rings and defined by Event +Descriptors (ED). Event rings are used by the device to report events such as +data transfer completion status, command completion status, and state changes +to the host. Event rings are the array of EDs that resides in the host +memory. EDs consist of one or more ring elements (or transfer blocks):: + + [Read Pointer (RP)] ----------->[Ring Element] } ED + [Write Pointer (WP)]- [Ring Element] + - [Ring Element] + --------->[Ring Element] + [Ring Element] + +Below is the basic usage of event rings: + +* Host allocates memory for event ring. +* Host sets the base pointer, read pointer, and write pointer in corresponding + channel context. +* Both host and device has a local copy of RP, WP. +* Ring is considered empty (no events to service) when WP + 1 == RP. +* Ring is considered full of events when RP == WP. +* When there is a new event the device needs to send, the device updates ED + pointed by RP, increments the RP to the next element and triggers the + interrupt. + +Ring Element +------------ + +A Ring Element is a data structure used to transfer a single block +of data between the host and the device. Transfer ring element types contain a +single buffer pointer, the size of the buffer, and additional control +information. Other ring element types may only contain control and status +information. For single buffer operations, a ring descriptor is composed of a +single element. For large multi-buffer operations (such as scatter and gather), +elements can be chained to form a longer descriptor. + +MHI Operations +============== + +MHI States +---------- + +MHI_STATE_RESET +~~~~~~~~~~~~~~~ +MHI is in reset state after power-up or hardware reset. The host is not allowed +to access device MMIO register space. + +MHI_STATE_READY +~~~~~~~~~~~~~~~ +MHI is ready for initialization. The host can start MHI initialization by +programming MMIO registers. + +MHI_STATE_M0 +~~~~~~~~~~~~ +MHI is running and operational in the device. The host can start channels by +issuing channel start command. + +MHI_STATE_M1 +~~~~~~~~~~~~ +MHI operation is suspended by the device. This state is entered when the +device detects inactivity at the physical interface within a preset time. + +MHI_STATE_M2 +~~~~~~~~~~~~ +MHI is in low power state. MHI operation is suspended and the device may +enter lower power mode. + +MHI_STATE_M3 +~~~~~~~~~~~~ +MHI operation stopped by the host. This state is entered when the host suspends +MHI operation. + +MHI Initialization +------------------ + +After system boots, the device is enumerated over the physical interface. +In the case of PCIe, the device is enumerated and assigned BAR-0 for +the device's MMIO register space. To initialize the MHI in a device, +the host performs the following operations: + +* Allocates the MHI context for event, channel and command arrays. +* Initializes the context array, and prepares interrupts. +* Waits until the device enters READY state. +* Programs MHI MMIO registers and sets device into MHI_M0 state. +* Waits for the device to enter M0 state. + +MHI Data Transfer +----------------- + +MHI data transfer is initiated by the host to transfer data to the device. +Following are the sequence of operations performed by the host to transfer +data to device: + +* Host prepares TD with buffer information. +* Host increments the WP of the corresponding channel transfer ring. +* Host rings the channel DB register. +* Device wakes up to process the TD. +* Device generates a completion event for the processed TD by updating ED. +* Device increments the RP of the corresponding event ring. +* Device triggers IRQ to wake up the host. +* Host wakes up and checks the event ring for completion event. +* Host updates the WP of the corresponding event ring to indicate that the + data transfer has been completed successfully. + diff --git a/Documentation/mhi/topology.rst b/Documentation/mhi/topology.rst new file mode 100644 index 000000000000..dc7799d03294 --- /dev/null +++ b/Documentation/mhi/topology.rst @@ -0,0 +1,60 @@ +.. SPDX-License-Identifier: GPL-2.0 + +============ +MHI Topology +============ + +This document provides information about the MHI topology modeling and +representation in the kernel. + +MHI Controller +-------------- + +MHI controller driver manages the interaction with the MHI client devices +such as the external modems and WiFi chipsets. It is also the MHI bus master +which is in charge of managing the physical link between the host and device. +It is however not involved in the actual data transfer as the data transfer +is taken care by the physical bus such as PCIe. Each controller driver exposes +channels and events based on the client device type. + +Below are the roles of the MHI controller driver: + +* Turns on the physical bus and establishes the link to the device +* Configures IRQs, IOMMU, and IOMEM +* Allocates struct mhi_controller and registers with the MHI bus framework + with channel and event configurations using mhi_register_controller. +* Initiates power on and shutdown sequence +* Initiates suspend and resume power management operations of the device. + +MHI Device +---------- + +MHI device is the logical device which binds to a maximum of two MHI channels +for bi-directional communication. Once MHI is in powered on state, the MHI +core will create MHI devices based on the channel configuration exposed +by the controller. There can be a single MHI device for each channel or for a +couple of channels. + +Each supported device is enumerated in:: + + /sys/bus/mhi/devices/ + +MHI Driver +---------- + +MHI driver is the client driver which binds to one or more MHI devices. The MHI +driver sends and receives the upper-layer protocol packets like IP packets, +modem control messages, and diagnostics messages over MHI. The MHI core will +bind the MHI devices to the MHI driver. + +Each supported driver is enumerated in:: + + /sys/bus/mhi/drivers/ + +Below are the roles of the MHI driver: + +* Registers the driver with the MHI bus framework using mhi_driver_register. +* Prepares the device for transfer by calling mhi_prepare_for_transfer. +* Initiates data transfer by calling mhi_queue_transfer. +* Once the data transfer is finished, calls mhi_unprepare_from_transfer to + end data transfer. diff --git a/Documentation/networking/devlink/devlink-trap.rst b/Documentation/networking/devlink/devlink-trap.rst index a09971c2115c..fe089acb7783 100644 --- a/Documentation/networking/devlink/devlink-trap.rst +++ b/Documentation/networking/devlink/devlink-trap.rst @@ -257,6 +257,8 @@ drivers: * :doc:`netdevsim` * :doc:`mlxsw` +.. _Generic-Packet-Trap-Groups: + Generic Packet Trap Groups ========================== diff --git a/Documentation/networking/index.rst b/Documentation/networking/index.rst index 50133d9761c9..6538ede29661 100644 --- a/Documentation/networking/index.rst +++ b/Documentation/networking/index.rst @@ -22,6 +22,7 @@ Contents: z8530book msg_zerocopy failover + net_dim net_failover phy sfp-phylink diff --git a/Documentation/networking/ip-sysctl.txt b/Documentation/networking/ip-sysctl.txt index ee961d322d93..6fcfd313dbe4 100644 --- a/Documentation/networking/ip-sysctl.txt +++ b/Documentation/networking/ip-sysctl.txt @@ -812,7 +812,7 @@ tcp_limit_output_bytes - INTEGER tcp_challenge_ack_limit - INTEGER Limits number of Challenge ACK sent per second, as recommended in RFC 5961 (Improving TCP's Robustness to Blind In-Window Attacks) - Default: 100 + Default: 1000 tcp_rx_skb_cache - BOOLEAN Controls a per TCP socket cache of one skb, that might help diff --git a/Documentation/networking/net_dim.txt b/Documentation/networking/net_dim.rst index 9bdb7d5a3ba3..3bed9fd95336 100644 --- a/Documentation/networking/net_dim.txt +++ b/Documentation/networking/net_dim.rst @@ -1,28 +1,20 @@ +====================================================== Net DIM - Generic Network Dynamic Interrupt Moderation ====================================================== -Author: - Tal Gilboa <talgi@mellanox.com> - - -Contents -========= +:Author: Tal Gilboa <talgi@mellanox.com> -- Assumptions -- Introduction -- The Net DIM Algorithm -- Registering a Network Device to DIM -- Example +.. contents:: :depth: 2 -Part 0: Assumptions -====================== +Assumptions +=========== This document assumes the reader has basic knowledge in network drivers and in general interrupt moderation. -Part I: Introduction -====================== +Introduction +============ Dynamic Interrupt Moderation (DIM) (in networking) refers to changing the interrupt moderation configuration of a channel in order to optimize packet @@ -41,14 +33,15 @@ number of wanted packets per event. The Net DIM algorithm ascribes importance to increase bandwidth over reducing interrupt rate. -Part II: The Net DIM Algorithm -=============================== +Net DIM Algorithm +================= Each iteration of the Net DIM algorithm follows these steps: -1. Calculates new data sample. -2. Compares it to previous sample. -3. Makes a decision - suggests interrupt moderation configuration fields. -4. Applies a schedule work function, which applies suggested configuration. + +#. Calculates new data sample. +#. Compares it to previous sample. +#. Makes a decision - suggests interrupt moderation configuration fields. +#. Applies a schedule work function, which applies suggested configuration. The first two steps are straightforward, both the new and the previous data are supplied by the driver registered to Net DIM. The previous data is the new data @@ -89,19 +82,21 @@ manoeuvre as it may provide partial data or ignore the algorithm suggestion under some conditions. -Part III: Registering a Network Device to DIM -============================================== +Registering a Network Device to DIM +=================================== -Net DIM API exposes the main function net_dim(struct dim *dim, -struct dim_sample end_sample). This function is the entry point to the Net +Net DIM API exposes the main function net_dim(). +This function is the entry point to the Net DIM algorithm and has to be called every time the driver would like to check if it should change interrupt moderation parameters. The driver should provide two -data structures: struct dim and struct dim_sample. Struct dim +data structures: :c:type:`struct dim <dim>` and +:c:type:`struct dim_sample <dim_sample>`. :c:type:`struct dim <dim>` describes the state of DIM for a specific object (RX queue, TX queue, other queues, etc.). This includes the current selected profile, previous data samples, the callback function provided by the driver and more. -Struct dim_sample describes a data sample, which will be compared to the -data sample stored in struct dim in order to decide on the algorithm's next +:c:type:`struct dim_sample <dim_sample>` describes a data sample, +which will be compared to the data sample stored in :c:type:`struct dim <dim>` +in order to decide on the algorithm's next step. The sample should include bytes, packets and interrupts, measured by the driver. @@ -110,9 +105,10 @@ main net_dim() function. The recommended method is to call net_dim() on each interrupt. Since Net DIM has a built-in moderation and it might decide to skip iterations under certain conditions, there is no need to moderate the net_dim() calls as well. As mentioned above, the driver needs to provide an object of type -struct dim to the net_dim() function call. It is advised for each entity -using Net DIM to hold a struct dim as part of its data structure and use it -as the main Net DIM API object. The struct dim_sample should hold the latest +:c:type:`struct dim <dim>` to the net_dim() function call. It is advised for +each entity using Net DIM to hold a :c:type:`struct dim <dim>` as part of its +data structure and use it as the main Net DIM API object. +The :c:type:`struct dim_sample <dim_sample>` should hold the latest bytes, packets and interrupts count. No need to perform any calculations, just include the raw data. @@ -124,19 +120,19 @@ the data flow. After the work is done, Net DIM algorithm needs to be set to the proper state in order to move to the next iteration. -Part IV: Example -================= +Example +======= The following code demonstrates how to register a driver to Net DIM. The actual usage is not complete but it should make the outline of the usage clear. -my_driver.c: +.. code-block:: c -#include <linux/dim.h> + #include <linux/dim.h> -/* Callback for net DIM to schedule on a decision to change moderation */ -void my_driver_do_dim_work(struct work_struct *work) -{ + /* Callback for net DIM to schedule on a decision to change moderation */ + void my_driver_do_dim_work(struct work_struct *work) + { /* Get struct dim from struct work_struct */ struct dim *dim = container_of(work, struct dim, work); @@ -145,11 +141,11 @@ void my_driver_do_dim_work(struct work_struct *work) /* Signal net DIM work is done and it should move to next iteration */ dim->state = DIM_START_MEASURE; -} + } -/* My driver's interrupt handler */ -int my_driver_handle_interrupt(struct my_driver_entity *my_entity, ...) -{ + /* My driver's interrupt handler */ + int my_driver_handle_interrupt(struct my_driver_entity *my_entity, ...) + { ... /* A struct to hold current measured data */ struct dim_sample dim_sample; @@ -162,13 +158,19 @@ int my_driver_handle_interrupt(struct my_driver_entity *my_entity, ...) /* Call net DIM */ net_dim(&my_entity->dim, dim_sample); ... -} + } -/* My entity's initialization function (my_entity was already allocated) */ -int my_driver_init_my_entity(struct my_driver_entity *my_entity, ...) -{ + /* My entity's initialization function (my_entity was already allocated) */ + int my_driver_init_my_entity(struct my_driver_entity *my_entity, ...) + { ... /* Initiate struct work_struct with my driver's callback function */ INIT_WORK(&my_entity->dim.work, my_driver_do_dim_work); ... -} + } + +Dynamic Interrupt Moderation (DIM) library API +============================================== + +.. kernel-doc:: include/linux/dim.h + :internal: diff --git a/Documentation/openrisc/openrisc_port.rst b/Documentation/openrisc/openrisc_port.rst index a18747a8d191..4b2c437942a0 100644 --- a/Documentation/openrisc/openrisc_port.rst +++ b/Documentation/openrisc/openrisc_port.rst @@ -37,8 +37,8 @@ or Stafford's toolchain build and release scripts. Build the Linux kernel as usual:: - make ARCH=openrisc defconfig - make ARCH=openrisc + make ARCH=openrisc CROSS_COMPILE="or1k-linux-" defconfig + make ARCH=openrisc CROSS_COMPILE="or1k-linux-" 3) Running on FPGA (optional) diff --git a/Documentation/powerpc/firmware-assisted-dump.rst b/Documentation/powerpc/firmware-assisted-dump.rst index 0455a78486d5..b3f3ee135dbe 100644 --- a/Documentation/powerpc/firmware-assisted-dump.rst +++ b/Documentation/powerpc/firmware-assisted-dump.rst @@ -112,13 +112,13 @@ to ensure that crash data is preserved to process later. -- On OPAL based machines (PowerNV), if the kernel is build with CONFIG_OPAL_CORE=y, OPAL memory at the time of crash is also - exported as /sys/firmware/opal/core file. This procfs file is + exported as /sys/firmware/opal/mpipl/core file. This procfs file is helpful in debugging OPAL crashes with GDB. The kernel memory used for exporting this procfs file can be released by echo'ing - '1' to /sys/kernel/fadump_release_opalcore node. + '1' to /sys/firmware/opal/mpipl/release_core node. e.g. - # echo 1 > /sys/kernel/fadump_release_opalcore + # echo 1 > /sys/firmware/opal/mpipl/release_core Implementation details: ----------------------- @@ -268,6 +268,11 @@ Here is the list of files under kernel sysfs: be handled and vmcore will not be captured. This interface can be easily integrated with kdump service start/stop. + /sys/kernel/fadump/mem_reserved + + This is used to display the memory reserved by FADump for saving the + crash dump. + /sys/kernel/fadump_release_mem This file is available only when FADump is active during second kernel. This is used to release the reserved memory @@ -283,14 +288,29 @@ Here is the list of files under kernel sysfs: enhanced to use this interface to release the memory reserved for dump and continue without 2nd reboot. - /sys/kernel/fadump_release_opalcore +Note: /sys/kernel/fadump_release_opalcore sysfs has moved to + /sys/firmware/opal/mpipl/release_core + + /sys/firmware/opal/mpipl/release_core This file is available only on OPAL based machines when FADump is active during capture kernel. This is used to release the memory - used by the kernel to export /sys/firmware/opal/core file. To + used by the kernel to export /sys/firmware/opal/mpipl/core file. To release this memory, echo '1' to it: - echo 1 > /sys/kernel/fadump_release_opalcore + echo 1 > /sys/firmware/opal/mpipl/release_core + +Note: The following FADump sysfs files are deprecated. + ++----------------------------------+--------------------------------+ +| Deprecated | Alternative | ++----------------------------------+--------------------------------+ +| /sys/kernel/fadump_enabled | /sys/kernel/fadump/enabled | ++----------------------------------+--------------------------------+ +| /sys/kernel/fadump_registered | /sys/kernel/fadump/registered | ++----------------------------------+--------------------------------+ +| /sys/kernel/fadump_release_mem | /sys/kernel/fadump/release_mem | ++----------------------------------+--------------------------------+ Here is the list of files under powerpc debugfs: (Assuming debugfs is mounted on /sys/kernel/debug directory.) diff --git a/Documentation/process/changes.rst b/Documentation/process/changes.rst index e47863575917..91c5ff8e161e 100644 --- a/Documentation/process/changes.rst +++ b/Documentation/process/changes.rst @@ -31,7 +31,7 @@ you probably needn't concern yourself with pcmciautils. ====================== =============== ======================================== GNU C 4.6 gcc --version GNU make 3.81 make --version -binutils 2.21 ld -v +binutils 2.23 ld -v flex 2.5.35 flex --version bison 2.0 bison --version util-linux 2.10o fdformat --version @@ -76,7 +76,7 @@ You will need GNU make 3.81 or later to build the kernel. Binutils -------- -Binutils 2.21 or newer is needed to build the kernel. +Binutils 2.23 or newer is needed to build the kernel. pkg-config ---------- diff --git a/Documentation/process/embargoed-hardware-issues.rst b/Documentation/process/embargoed-hardware-issues.rst index a19d084f9b2c..43cdc67e4f8e 100644 --- a/Documentation/process/embargoed-hardware-issues.rst +++ b/Documentation/process/embargoed-hardware-issues.rst @@ -246,7 +246,8 @@ an involved disclosed party. The current ambassadors list: ============= ======================================================== ARM Grant Likely <grant.likely@arm.com> AMD Tom Lendacky <tom.lendacky@amd.com> - IBM + IBM Z Christian Borntraeger <borntraeger@de.ibm.com> + IBM Power Anton Blanchard <anton@linux.ibm.com> Intel Tony Luck <tony.luck@intel.com> Qualcomm Trilok Soni <tsoni@codeaurora.org> diff --git a/Documentation/remoteproc.txt b/Documentation/remoteproc.txt index 03c3d2e568b0..2be1147256e0 100644 --- a/Documentation/remoteproc.txt +++ b/Documentation/remoteproc.txt @@ -230,7 +230,7 @@ in the used rings. Binary Firmware Structure ========================= -At this point remoteproc only supports ELF32 firmware binaries. However, +At this point remoteproc supports ELF32 and ELF64 firmware binaries. However, it is quite expected that other platforms/devices which we'd want to support with this framework will be based on different binary formats. diff --git a/Documentation/scsi/53c700.txt b/Documentation/scsi/53c700.rst index e31aceb6df15..53a0e9f9c198 100644 --- a/Documentation/scsi/53c700.txt +++ b/Documentation/scsi/53c700.rst @@ -1,3 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0 + +======================= +The 53c700 Driver Notes +======================= + General Description =================== @@ -16,9 +22,9 @@ fill in to get the driver working. Compile Time Flags ================== -A compile time flag is: +A compile time flag is:: -CONFIG_53C700_LE_ON_BE + CONFIG_53C700_LE_ON_BE define if the chipset must be supported in little endian mode on a big endian architecture (used for the 700 on parisc). @@ -51,9 +57,11 @@ consistent with the best operation of the chip (although some choose to drive it off the CPU or bus clock rather than going to the expense of an extra clock chip). The best operation clock speeds are: -53c700 - 25MHz -53c700-66 - 50MHz -53c710 - 40Mhz +========= ===== +53c700 25MHz +53c700-66 50MHz +53c710 40Mhz +========= ===== Writing Your Glue Driver ======================== @@ -69,7 +77,7 @@ parameters that matter to you (see below), plumb the NCR_700_intr routine into the interrupt line and call NCR_700_detect with the host template and the new parameters as arguments. You should also call the relevant request_*_region function and place the register base -address into the `base' pointer of the host parameters. +address into the 'base' pointer of the host parameters. In the release routine, you must free the NCR_700_Host_Parameters that you allocated, call the corresponding release_*_region and free the @@ -78,7 +86,7 @@ interrupt. Handling Interrupts ------------------- -In general, you should just plumb the card's interrupt line in with +In general, you should just plumb the card's interrupt line in with request_irq(irq, NCR_700_intr, <irq flags>, <driver name>, host); @@ -95,41 +103,32 @@ Settable NCR_700_Host_Parameters The following are a list of the user settable parameters: clock: (MANDATORY) - -Set to the clock speed of the chip in MHz. + Set to the clock speed of the chip in MHz. base: (MANDATORY) - -set to the base of the io or mem region for the register set. On 64 -bit architectures this is only 32 bits wide, so the registers must be -mapped into the low 32 bits of memory. + Set to the base of the io or mem region for the register set. On 64 + bit architectures this is only 32 bits wide, so the registers must be + mapped into the low 32 bits of memory. pci_dev: (OPTIONAL) - -set to the PCI board device. Leave NULL for a non-pci board. This is -used for the pci_alloc_consistent() and pci_map_*() functions. + Set to the PCI board device. Leave NULL for a non-pci board. This is + used for the pci_alloc_consistent() and pci_map_*() functions. dmode_extra: (OPTIONAL, 53c710 only) - -extra flags for the DMODE register. These are used to control bus -output pins on the 710. The settings should be a combination of -DMODE_FC1 and DMODE_FC2. What these pins actually do is entirely up -to the board designer. Usually it is safe to ignore this setting. + Extra flags for the DMODE register. These are used to control bus + output pins on the 710. The settings should be a combination of + DMODE_FC1 and DMODE_FC2. What these pins actually do is entirely up + to the board designer. Usually it is safe to ignore this setting. differential: (OPTIONAL) - -set to 1 if the chip drives a differential bus. + Set to 1 if the chip drives a differential bus. force_le_on_be: (OPTIONAL, only if CONFIG_53C700_LE_ON_BE is set) - -set to 1 if the chip is operating in little endian mode on a big -endian architecture. + Set to 1 if the chip is operating in little endian mode on a big + endian architecture. chip710: (OPTIONAL) - -set to 1 if the chip is a 53c710. + Set to 1 if the chip is a 53c710. burst_disable: (OPTIONAL, 53c710 only) - -disable 8 byte bursting for DMA transfers. - + Disable 8 byte bursting for DMA transfers. diff --git a/Documentation/scsi/BusLogic.txt b/Documentation/scsi/BusLogic.rst index 48e982cd6fe7..b60169812358 100644 --- a/Documentation/scsi/BusLogic.txt +++ b/Documentation/scsi/BusLogic.rst @@ -1,6 +1,11 @@ - BusLogic MultiMaster and FlashPoint SCSI Driver for Linux +.. SPDX-License-Identifier: GPL-2.0 + +========================================================= +BusLogic MultiMaster and FlashPoint SCSI Driver for Linux +========================================================= Version 2.0.15 for Linux 2.0 + Version 2.1.15 for Linux 2.1 PRODUCTION RELEASE @@ -8,13 +13,16 @@ 17 August 1998 Leonard N. Zubkoff + Dandelion Digital + lnz@dandelion.com Copyright 1995-1998 by Leonard N. Zubkoff <lnz@dandelion.com> - INTRODUCTION +Introduction +============ BusLogic, Inc. designed and manufactured a variety of high performance SCSI host adapters which share a common programming interface across a diverse @@ -86,9 +94,11 @@ Contact information for offices in Europe and Japan is available on the Web site. - DRIVER FEATURES +Driver Features +=============== -o Configuration Reporting and Testing +Configuration Reporting and Testing +----------------------------------- During system initialization, the driver reports extensively on the host adapter hardware configuration, including the synchronous transfer parameters @@ -130,7 +140,8 @@ o Configuration Reporting and Testing The status of Wide Negotiation, Disconnect/Reconnect, and Tagged Queuing are reported as "Enabled", Disabled", or a sequence of "Y" and "N" letters. -o Performance Features +Performance Features +-------------------- BusLogic SCSI Host Adapters directly implement SCSI-2 Tagged Queuing, and so support has been included in the driver to utilize tagged queuing with any @@ -150,7 +161,8 @@ o Performance Features queue depth of 1 is selected. Tagged queuing is also disabled for individual target devices if disconnect/reconnect is disabled for that device. -o Robustness Features +Robustness Features +------------------- The driver implements extensive error recovery procedures. When the higher level parts of the SCSI subsystem request that a timed out command be reset, @@ -174,7 +186,8 @@ o Robustness Features lock up or crash, and thereby allowing a clean shutdown and restart after the offending component is removed. -o PCI Configuration Support +PCI Configuration Support +------------------------- On PCI systems running kernels compiled with PCI BIOS support enabled, this driver will interrogate the PCI configuration space and use the I/O port @@ -184,19 +197,22 @@ o PCI Configuration Support used to disable the ISA compatible I/O port entirely as it is not necessary. The ISA compatible I/O port is disabled by default on the BT-948/958/958D. -o /proc File System Support +/proc File System Support +------------------------- Copies of the host adapter configuration information together with updated data transfer and error recovery statistics are available through the /proc/scsi/BusLogic/<N> interface. -o Shared Interrupts Support +Shared Interrupts Support +------------------------- On systems that support shared interrupts, any number of BusLogic Host Adapters may share the same interrupt request channel. - SUPPORTED HOST ADAPTERS +Supported Host Adapters +======================= The following list comprises the supported BusLogic SCSI Host Adapters as of the date of this document. It is recommended that anyone purchasing a BusLogic @@ -205,6 +221,7 @@ that it is or will be supported. FlashPoint Series PCI Host Adapters: +======================= ============================================= FlashPoint LT (BT-930) Ultra SCSI-3 FlashPoint LT (BT-930R) Ultra SCSI-3 with RAIDPlus FlashPoint LT (BT-920) Ultra SCSI-3 (BT-930 without BIOS) @@ -214,15 +231,19 @@ FlashPoint LW (BT-950) Wide Ultra SCSI-3 FlashPoint LW (BT-950R) Wide Ultra SCSI-3 with RAIDPlus FlashPoint DW (BT-952) Dual Channel Wide Ultra SCSI-3 FlashPoint DW (BT-952R) Dual Channel Wide Ultra SCSI-3 with RAIDPlus +======================= ============================================= MultiMaster "W" Series Host Adapters: +======= === ============================== BT-948 PCI Ultra SCSI-3 BT-958 PCI Wide Ultra SCSI-3 BT-958D PCI Wide Differential Ultra SCSI-3 +======= === ============================== MultiMaster "C" Series Host Adapters: +======== ==== ============================== BT-946C PCI Fast SCSI-2 BT-956C PCI Wide Fast SCSI-2 BT-956CD PCI Wide Differential Fast SCSI-2 @@ -232,9 +253,11 @@ BT-757C EISA Wide Fast SCSI-2 BT-757CD EISA Wide Differential Fast SCSI-2 BT-545C ISA Fast SCSI-2 BT-540CF ISA Fast SCSI-2 +======== ==== ============================== MultiMaster "S" Series Host Adapters: +======= ==== ============================== BT-445S VLB Fast SCSI-2 BT-747S EISA Fast SCSI-2 BT-747D EISA Differential Fast SCSI-2 @@ -244,11 +267,14 @@ BT-545S ISA Fast SCSI-2 BT-542D ISA Differential Fast SCSI-2 BT-742A EISA SCSI-2 (742A revision H) BT-542B ISA SCSI-2 (542B revision H) +======= ==== ============================== MultiMaster "A" Series Host Adapters: +======= ==== ============================== BT-742A EISA SCSI-2 (742A revisions A - G) BT-542B ISA SCSI-2 (542B revisions A - G) +======= ==== ============================== AMI FastDisk Host Adapters that are true BusLogic MultiMaster clones are also supported by this driver. @@ -260,9 +286,11 @@ list. The retail kit includes the bare board and manual as well as cabling and driver media and documentation that are not provided with bare boards. - FLASHPOINT INSTALLATION NOTES +FlashPoint Installation Notes +============================= -o RAIDPlus Support +RAIDPlus Support +---------------- FlashPoint Host Adapters now include RAIDPlus, Mylex's bootable software RAID. RAIDPlus is not supported on Linux, and there are no plans to support @@ -273,7 +301,8 @@ o RAIDPlus Support than RAIDPlus, so there is little impetus to include RAIDPlus support in the BusLogic driver. -o Enabling UltraSCSI Transfers +Enabling UltraSCSI Transfers +---------------------------- FlashPoint Host Adapters ship with their configuration set to "Factory Default" settings that are conservative and do not allow for UltraSCSI speed @@ -287,12 +316,14 @@ o Enabling UltraSCSI Transfers the "Optimum Performance" settings are loaded. - BT-948/958/958D INSTALLATION NOTES +BT-948/958/958D Installation Notes +================================== The BT-948/958/958D PCI Ultra SCSI Host Adapters have some features which may require attention in some circumstances when installing Linux. -o PCI I/O Port Assignments +PCI I/O Port Assignments +------------------------ When configured to factory default settings, the BT-948/958/958D will only recognize the PCI I/O port assignments made by the motherboard's PCI BIOS. @@ -312,7 +343,8 @@ o PCI I/O Port Assignments possible future I/O port conflicts. The older BT-946C/956C/956CD also have this configuration option, but the factory default setting is "Primary". -o PCI Slot Scanning Order +PCI Slot Scanning Order +----------------------- In systems with multiple BusLogic PCI Host Adapters, the order in which the PCI slots are scanned may appear reversed with the BT-948/958/958D as @@ -339,7 +371,8 @@ o PCI Slot Scanning Order so as to recognize the host adapters in the same order as they are enumerated by the host adapter's BIOS. -o Enabling UltraSCSI Transfers +Enabling UltraSCSI Transfers +---------------------------- The BT-948/958/958D ship with their configuration set to "Factory Default" settings that are conservative and do not allow for UltraSCSI speed to be @@ -353,7 +386,8 @@ o Enabling UltraSCSI Transfers "Optimum Performance" settings are loaded. - DRIVER OPTIONS +Driver Options +============== BusLogic Driver Options may be specified either via the Linux Kernel Command Line or via the Loadable Kernel Module Installation Facility. Driver Options @@ -520,30 +554,34 @@ The following examples demonstrate setting the Queue Depth for Target Devices Devices on the second host adapter to 31, and the Bus Settle Time on the second host adapter to 30 seconds. -Linux Kernel Command Line: +Linux Kernel Command Line:: linux BusLogic=QueueDepth:[,7,15];QueueDepth:31,BusSettleTime:30 -LILO Linux Boot Loader (in /etc/lilo.conf): +LILO Linux Boot Loader (in /etc/lilo.conf):: append = "BusLogic=QueueDepth:[,7,15];QueueDepth:31,BusSettleTime:30" -INSMOD Loadable Kernel Module Installation Facility: +INSMOD Loadable Kernel Module Installation Facility:: insmod BusLogic.o \ 'BusLogic="QueueDepth:[,7,15];QueueDepth:31,BusSettleTime:30"' -NOTE: Module Utilities 2.1.71 or later is required for correct parsing + +.. Note:: + + Module Utilities 2.1.71 or later is required for correct parsing of driver options containing commas. - DRIVER INSTALLATION +Driver Installation +=================== This distribution was prepared for Linux kernel version 2.0.35, but should be compatible with 2.0.4 or any later 2.0 series kernel. To install the new BusLogic SCSI driver, you may use the following commands, -replacing "/usr/src" with wherever you keep your Linux kernel source tree: +replacing "/usr/src" with wherever you keep your Linux kernel source tree:: cd /usr/src tar -xvzf BusLogic-2.0.15.tar.gz @@ -557,7 +595,8 @@ Then install "arch/x86/boot/zImage" as your standard kernel, run lilo if appropriate, and reboot. - BUSLOGIC ANNOUNCEMENTS MAILING LIST +BusLogic Announcements Mailing List +=================================== The BusLogic Announcements Mailing List provides a forum for informing Linux users of new driver releases and other announcements regarding Linux support diff --git a/Documentation/scsi/FlashPoint.rst b/Documentation/scsi/FlashPoint.rst new file mode 100644 index 000000000000..ef3c07e94ad6 --- /dev/null +++ b/Documentation/scsi/FlashPoint.rst @@ -0,0 +1,176 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=================================== +The BusLogic FlashPoint SCSI Driver +=================================== + +The BusLogic FlashPoint SCSI Host Adapters are now fully supported on Linux. +The upgrade program described below has been officially terminated effective +31 March 1997 since it is no longer needed. + +:: + + MYLEX INTRODUCES LINUX OPERATING SYSTEM SUPPORT FOR ITS + BUSLOGIC FLASHPOINT LINE OF SCSI HOST ADAPTERS + + + FREMONT, CA, -- October 8, 1996 -- Mylex Corporation has expanded Linux + operating system support to its BusLogic brand of FlashPoint Ultra SCSI + host adapters. All of BusLogic's other SCSI host adapters, including the + MultiMaster line, currently support the Linux operating system. Linux + drivers and information will be available on October 15th at + http://sourceforge.net/projects/dandelion/. + + "Mylex is committed to supporting the Linux community," says Peter Shambora, + vice president of marketing for Mylex. "We have supported Linux driver + development and provided technical support for our host adapters for several + years, and are pleased to now make our FlashPoint products available to this + user base." + +The Linux Operating System +========================== + +Linux is a freely-distributed implementation of UNIX for Intel x86, Sun +SPARC, SGI MIPS, Motorola 68k, Digital Alpha AXP and Motorola PowerPC +machines. It supports a wide range of software, including the X Window +System, Emacs, and TCP/IP networking. Further information is available at +http://www.linux.org and http://www.ssc.com/. + +FlashPoint Host Adapters +======================== + +The FlashPoint family of Ultra SCSI host adapters, designed for workstation +and file server environments, are available in narrow, wide, dual channel, +and dual channel wide versions. These adapters feature SeqEngine +automation technology, which minimizes SCSI command overhead and reduces +the number of interrupts generated to the CPU. + +About Mylex +=========== + +Mylex Corporation (NASDAQ/NM SYMBOL: MYLX), founded in 1983, is a leading +producer of RAID technology and network management products. The company +produces high performance disk array (RAID) controllers, and complementary +computer products for network servers, mass storage systems, workstations +and system boards. Through its wide range of RAID controllers and its +BusLogic line of Ultra SCSI host adapter products, Mylex provides enabling +intelligent I/O technologies that increase network management control, +enhance CPU utilization, optimize I/O performance, and ensure data security +and availability. Products are sold globally through a network of OEMs, +major distributors, VARs, and system integrators. Mylex Corporation is +headquartered at 34551 Ardenwood Blvd., Fremont, CA. + +Contact: +======== + +:: + + Peter Shambora + Vice President of Marketing + Mylex Corp. + 510/796-6100 + peters@mylex.com + + +:: + + ANNOUNCEMENT + BusLogic FlashPoint LT/BT-948 Upgrade Program + 1 February 1996 + + ADDITIONAL ANNOUNCEMENT + BusLogic FlashPoint LW/BT-958 Upgrade Program + 14 June 1996 + + Ever since its introduction last October, the BusLogic FlashPoint LT has + been problematic for members of the Linux community, in that no Linux + drivers have been available for this new Ultra SCSI product. Despite its + officially being positioned as a desktop workstation product, and not being + particularly well suited for a high performance multitasking operating + system like Linux, the FlashPoint LT has been touted by computer system + vendors as the latest thing, and has been sold even on many of their high + end systems, to the exclusion of the older MultiMaster products. This has + caused grief for many people who inadvertently purchased a system expecting + that all BusLogic SCSI Host Adapters were supported by Linux, only to + discover that the FlashPoint was not supported and would not be for quite + some time, if ever. + + After this problem was identified, BusLogic contacted its major OEM + customers to make sure the BT-946C/956C MultiMaster cards would still be + made available, and that Linux users who mistakenly ordered systems with + the FlashPoint would be able to upgrade to the BT-946C. While this helped + many purchasers of new systems, it was only a partial solution to the + overall problem of FlashPoint support for Linux users. It did nothing to + assist the people who initially purchased a FlashPoint for a supported + operating system and then later decided to run Linux, or those who had + ended up with a FlashPoint LT, believing it was supported, and were unable + to return it. + + In the middle of December, I asked to meet with BusLogic's senior + management to discuss the issues related to Linux and free software support + for the FlashPoint. Rumors of varying accuracy had been circulating + publicly about BusLogic's attitude toward the Linux community, and I felt + it was best that these issues be addressed directly. I sent an email + message after 11pm one evening, and the meeting took place the next + afternoon. Unfortunately, corporate wheels sometimes grind slowly, + especially when a company is being acquired, and so it's taken until now + before the details were completely determined and a public statement could + be made. + + BusLogic is not prepared at this time to release the information necessary + for third parties to write drivers for the FlashPoint. The only existing + FlashPoint drivers have been written directly by BusLogic Engineering, and + there is no FlashPoint documentation sufficiently detailed to allow outside + developers to write a driver without substantial assistance. While there + are people at BusLogic who would rather not release the details of the + FlashPoint architecture at all, that debate has not yet been settled either + way. In any event, even if documentation were available today it would + take quite a while for a usable driver to be written, especially since I'm + not convinced that the effort required would be worthwhile. + + However, BusLogic does remain committed to providing a high performance + SCSI solution for the Linux community, and does not want to see anyone left + unable to run Linux because they have a Flashpoint LT. Therefore, BusLogic + has put in place a direct upgrade program to allow any Linux user worldwide + to trade in their FlashPoint LT for the new BT-948 MultiMaster PCI Ultra + SCSI Host Adapter. The BT-948 is the Ultra SCSI successor to the BT-946C + and has all the best features of both the BT-946C and FlashPoint LT, + including smart termination and a flash PROM for easy firmware updates, and + is of course compatible with the present Linux driver. The price for this + upgrade has been set at US $45 plus shipping and handling, and the upgrade + program will be administered through BusLogic Technical Support, which can + be reached by electronic mail at techsup@buslogic.com, by Voice at +1 408 + 654-0760, or by FAX at +1 408 492-1542. + + As of 14 June 1996, the original BusLogic FlashPoint LT to BT-948 upgrade + program has now been extended to encompass the FlashPoint LW Wide Ultra + SCSI Host Adapter. Any Linux user worldwide may trade in their FlashPoint + LW (BT-950) for a BT-958 MultiMaster PCI Ultra SCSI Host Adapter. The + price for this upgrade has been set at US $65 plus shipping and handling. + + I was a beta test site for the BT-948/958, and versions 1.2.1 and 1.3.1 of + my BusLogic driver already included latent support for the BT-948/958. + Additional cosmetic support for the Ultra SCSI MultiMaster cards was added + subsequent releases. As a result of this cooperative testing process, + several firmware bugs were found and corrected. My heavily loaded Linux + test system provided an ideal environment for testing error recovery + processes that are much more rarely exercised in production systems, but + are crucial to overall system stability. It was especially convenient + being able to work directly with their firmware engineer in demonstrating + the problems under control of the firmware debugging environment; things + sure have come a long way since the last time I worked on firmware for an + embedded system. I am presently working on some performance testing and + expect to have some data to report in the not too distant future. + + BusLogic asked me to send this announcement since a large percentage of the + questions regarding support for the FlashPoint have either been sent to me + directly via email, or have appeared in the Linux newsgroups in which I + participate. To summarize, BusLogic is offering Linux users an upgrade + from the unsupported FlashPoint LT (BT-930) to the supported BT-948 for US + $45 plus shipping and handling, or from the unsupported FlashPoint LW + (BT-950) to the supported BT-958 for $65 plus shipping and handling. + Contact BusLogic Technical Support at techsup@buslogic.com or +1 408 + 654-0760 to take advantage of their offer. + + Leonard N. Zubkoff + lnz@dandelion.com diff --git a/Documentation/scsi/FlashPoint.txt b/Documentation/scsi/FlashPoint.txt deleted file mode 100644 index 5b5f29cb9f8b..000000000000 --- a/Documentation/scsi/FlashPoint.txt +++ /dev/null @@ -1,163 +0,0 @@ -The BusLogic FlashPoint SCSI Host Adapters are now fully supported on Linux. -The upgrade program described below has been officially terminated effective -31 March 1997 since it is no longer needed. - - - - MYLEX INTRODUCES LINUX OPERATING SYSTEM SUPPORT FOR ITS - BUSLOGIC FLASHPOINT LINE OF SCSI HOST ADAPTERS - - -FREMONT, CA, -- October 8, 1996 -- Mylex Corporation has expanded Linux -operating system support to its BusLogic brand of FlashPoint Ultra SCSI -host adapters. All of BusLogic's other SCSI host adapters, including the -MultiMaster line, currently support the Linux operating system. Linux -drivers and information will be available on October 15th at -http://sourceforge.net/projects/dandelion/. - -"Mylex is committed to supporting the Linux community," says Peter Shambora, -vice president of marketing for Mylex. "We have supported Linux driver -development and provided technical support for our host adapters for several -years, and are pleased to now make our FlashPoint products available to this -user base." - -The Linux Operating System - -Linux is a freely-distributed implementation of UNIX for Intel x86, Sun -SPARC, SGI MIPS, Motorola 68k, Digital Alpha AXP and Motorola PowerPC -machines. It supports a wide range of software, including the X Window -System, Emacs, and TCP/IP networking. Further information is available at -http://www.linux.org and http://www.ssc.com/. - -FlashPoint Host Adapters - -The FlashPoint family of Ultra SCSI host adapters, designed for workstation -and file server environments, are available in narrow, wide, dual channel, -and dual channel wide versions. These adapters feature SeqEngine -automation technology, which minimizes SCSI command overhead and reduces -the number of interrupts generated to the CPU. - -About Mylex - -Mylex Corporation (NASDAQ/NM SYMBOL: MYLX), founded in 1983, is a leading -producer of RAID technology and network management products. The company -produces high performance disk array (RAID) controllers, and complementary -computer products for network servers, mass storage systems, workstations -and system boards. Through its wide range of RAID controllers and its -BusLogic line of Ultra SCSI host adapter products, Mylex provides enabling -intelligent I/O technologies that increase network management control, -enhance CPU utilization, optimize I/O performance, and ensure data security -and availability. Products are sold globally through a network of OEMs, -major distributors, VARs, and system integrators. Mylex Corporation is -headquartered at 34551 Ardenwood Blvd., Fremont, CA. - - #### - -Contact: - -Peter Shambora -Vice President of Marketing -Mylex Corp. -510/796-6100 -peters@mylex.com - - ANNOUNCEMENT - BusLogic FlashPoint LT/BT-948 Upgrade Program - 1 February 1996 - - ADDITIONAL ANNOUNCEMENT - BusLogic FlashPoint LW/BT-958 Upgrade Program - 14 June 1996 - -Ever since its introduction last October, the BusLogic FlashPoint LT has -been problematic for members of the Linux community, in that no Linux -drivers have been available for this new Ultra SCSI product. Despite its -officially being positioned as a desktop workstation product, and not being -particularly well suited for a high performance multitasking operating -system like Linux, the FlashPoint LT has been touted by computer system -vendors as the latest thing, and has been sold even on many of their high -end systems, to the exclusion of the older MultiMaster products. This has -caused grief for many people who inadvertently purchased a system expecting -that all BusLogic SCSI Host Adapters were supported by Linux, only to -discover that the FlashPoint was not supported and would not be for quite -some time, if ever. - -After this problem was identified, BusLogic contacted its major OEM -customers to make sure the BT-946C/956C MultiMaster cards would still be -made available, and that Linux users who mistakenly ordered systems with -the FlashPoint would be able to upgrade to the BT-946C. While this helped -many purchasers of new systems, it was only a partial solution to the -overall problem of FlashPoint support for Linux users. It did nothing to -assist the people who initially purchased a FlashPoint for a supported -operating system and then later decided to run Linux, or those who had -ended up with a FlashPoint LT, believing it was supported, and were unable -to return it. - -In the middle of December, I asked to meet with BusLogic's senior -management to discuss the issues related to Linux and free software support -for the FlashPoint. Rumors of varying accuracy had been circulating -publicly about BusLogic's attitude toward the Linux community, and I felt -it was best that these issues be addressed directly. I sent an email -message after 11pm one evening, and the meeting took place the next -afternoon. Unfortunately, corporate wheels sometimes grind slowly, -especially when a company is being acquired, and so it's taken until now -before the details were completely determined and a public statement could -be made. - -BusLogic is not prepared at this time to release the information necessary -for third parties to write drivers for the FlashPoint. The only existing -FlashPoint drivers have been written directly by BusLogic Engineering, and -there is no FlashPoint documentation sufficiently detailed to allow outside -developers to write a driver without substantial assistance. While there -are people at BusLogic who would rather not release the details of the -FlashPoint architecture at all, that debate has not yet been settled either -way. In any event, even if documentation were available today it would -take quite a while for a usable driver to be written, especially since I'm -not convinced that the effort required would be worthwhile. - -However, BusLogic does remain committed to providing a high performance -SCSI solution for the Linux community, and does not want to see anyone left -unable to run Linux because they have a Flashpoint LT. Therefore, BusLogic -has put in place a direct upgrade program to allow any Linux user worldwide -to trade in their FlashPoint LT for the new BT-948 MultiMaster PCI Ultra -SCSI Host Adapter. The BT-948 is the Ultra SCSI successor to the BT-946C -and has all the best features of both the BT-946C and FlashPoint LT, -including smart termination and a flash PROM for easy firmware updates, and -is of course compatible with the present Linux driver. The price for this -upgrade has been set at US $45 plus shipping and handling, and the upgrade -program will be administered through BusLogic Technical Support, which can -be reached by electronic mail at techsup@buslogic.com, by Voice at +1 408 -654-0760, or by FAX at +1 408 492-1542. - -As of 14 June 1996, the original BusLogic FlashPoint LT to BT-948 upgrade -program has now been extended to encompass the FlashPoint LW Wide Ultra -SCSI Host Adapter. Any Linux user worldwide may trade in their FlashPoint -LW (BT-950) for a BT-958 MultiMaster PCI Ultra SCSI Host Adapter. The -price for this upgrade has been set at US $65 plus shipping and handling. - -I was a beta test site for the BT-948/958, and versions 1.2.1 and 1.3.1 of -my BusLogic driver already included latent support for the BT-948/958. -Additional cosmetic support for the Ultra SCSI MultiMaster cards was added -subsequent releases. As a result of this cooperative testing process, -several firmware bugs were found and corrected. My heavily loaded Linux -test system provided an ideal environment for testing error recovery -processes that are much more rarely exercised in production systems, but -are crucial to overall system stability. It was especially convenient -being able to work directly with their firmware engineer in demonstrating -the problems under control of the firmware debugging environment; things -sure have come a long way since the last time I worked on firmware for an -embedded system. I am presently working on some performance testing and -expect to have some data to report in the not too distant future. - -BusLogic asked me to send this announcement since a large percentage of the -questions regarding support for the FlashPoint have either been sent to me -directly via email, or have appeared in the Linux newsgroups in which I -participate. To summarize, BusLogic is offering Linux users an upgrade -from the unsupported FlashPoint LT (BT-930) to the supported BT-948 for US -$45 plus shipping and handling, or from the unsupported FlashPoint LW -(BT-950) to the supported BT-958 for $65 plus shipping and handling. -Contact BusLogic Technical Support at techsup@buslogic.com or +1 408 -654-0760 to take advantage of their offer. - - Leonard N. Zubkoff - lnz@dandelion.com diff --git a/Documentation/scsi/NinjaSCSI.rst b/Documentation/scsi/NinjaSCSI.rst new file mode 100644 index 000000000000..999a6ed5bf7e --- /dev/null +++ b/Documentation/scsi/NinjaSCSI.rst @@ -0,0 +1,164 @@ +.. SPDX-License-Identifier: GPL-2.0 + +========================================= +WorkBiT NinjaSCSI-3/32Bi driver for Linux +========================================= + +1. Comment +========== + +This is Workbit corp.'s(http://www.workbit.co.jp/) NinjaSCSI-3 +for Linux. + +2. My Linux environment +======================= + +:Linux kernel: 2.4.7 / 2.2.19 +:pcmcia-cs: 3.1.27 +:gcc: gcc-2.95.4 +:PC card: I-O data PCSC-F (NinjaSCSI-3), + I-O data CBSC-II in 16 bit mode (NinjaSCSI-32Bi) +:SCSI device: I-O data CDPS-PX24 (CD-ROM drive), + Media Intelligent MMO-640GT (Optical disk drive) + +3. Install +========== + +(a) Check your PC card is true "NinjaSCSI-3" card. + + If you installed pcmcia-cs already, pcmcia reports your card as UNKNOWN + card, and write ["WBT", "NinjaSCSI-3", "R1.0"] or some other string to + your console or log file. + + You can also use "cardctl" program (this program is in pcmcia-cs source + code) to get more info. + + :: + + # cat /var/log/messages + ... + Jan 2 03:45:06 lindberg cardmgr[78]: unsupported card in socket 1 + Jan 2 03:45:06 lindberg cardmgr[78]: product info: "WBT", "NinjaSCSI-3", "R1.0" + ... + # cardctl ident + Socket 0: + no product info available + Socket 1: + product info: "IO DATA", "CBSC16 ", "1" + + +(b) Get the Linux kernel source, and extract it to /usr/src. + Because the NinjaSCSI driver requires some SCSI header files in Linux + kernel source, I recommend rebuilding your kernel; this eliminates + some versioning problems. + + :: + + $ cd /usr/src + $ tar -zxvf linux-x.x.x.tar.gz + $ cd linux + $ make config + ... + +(c) If you use this driver with Kernel 2.2, unpack pcmcia-cs in some directory + and make & install. This driver requires the pcmcia-cs header file. + + :: + + $ cd /usr/src + $ tar zxvf cs-pcmcia-cs-3.x.x.tar.gz + ... + +(d) Extract this driver's archive somewhere, and edit Makefile, then do make:: + + $ tar -zxvf nsp_cs-x.x.tar.gz + $ cd nsp_cs-x.x + $ emacs Makefile + ... + $ make + +(e) Copy nsp_cs.ko to suitable place, like /lib/modules/<Kernel version>/pcmcia/ . + +(f) Add these lines to /etc/pcmcia/config . + + If you use pcmcia-cs-3.1.8 or later, we can use "nsp_cs.conf" file. + So, you don't need to edit file. Just copy to /etc/pcmcia/ . + + :: + + device "nsp_cs" + class "scsi" module "nsp_cs" + + card "WorkBit NinjaSCSI-3" + version "WBT", "NinjaSCSI-3", "R1.0" + bind "nsp_cs" + + card "WorkBit NinjaSCSI-32Bi (16bit)" + version "WORKBIT", "UltraNinja-16", "1" + bind "nsp_cs" + + # OEM + card "WorkBit NinjaSCSI-32Bi (16bit) / IO-DATA" + version "IO DATA", "CBSC16 ", "1" + bind "nsp_cs" + + # OEM + card "WorkBit NinjaSCSI-32Bi (16bit) / KME-1" + version "KME ", "SCSI-CARD-001", "1" + bind "nsp_cs" + card "WorkBit NinjaSCSI-32Bi (16bit) / KME-2" + version "KME ", "SCSI-CARD-002", "1" + bind "nsp_cs" + card "WorkBit NinjaSCSI-32Bi (16bit) / KME-3" + version "KME ", "SCSI-CARD-003", "1" + bind "nsp_cs" + card "WorkBit NinjaSCSI-32Bi (16bit) / KME-4" + version "KME ", "SCSI-CARD-004", "1" + bind "nsp_cs" + +(f) Start (or restart) pcmcia-cs:: + + # /etc/rc.d/rc.pcmcia start (BSD style) + + or:: + + # /etc/init.d/pcmcia start (SYSV style) + + +4. History +========== + +See README.nin_cs . + +5. Caution +========== + +If you eject card when doing some operation for your SCSI device or suspend +your computer, you encount some *BAD* error like disk crash. + +It works good when I using this driver right way. But I'm not guarantee +your data. Please backup your data when you use this driver. + +6. Known Bugs +============= + +In 2.4 kernel, you can't use 640MB Optical disk. This error comes from +high level SCSI driver. + +7. Testing +========== + +Please send me some reports(bug reports etc..) of this software. +When you send report, please tell me these or more. + + - card name + - kernel version + - your SCSI device name(hard drive, CD-ROM, etc...) + +8. Copyright +============ + + See GPL. + + +2001/08/08 yokota@netlab.is.tsukuba.ac.jp <YOKOTA Hiroshi> diff --git a/Documentation/scsi/NinjaSCSI.txt b/Documentation/scsi/NinjaSCSI.txt deleted file mode 100644 index ac8db8ceec77..000000000000 --- a/Documentation/scsi/NinjaSCSI.txt +++ /dev/null @@ -1,128 +0,0 @@ - - WorkBiT NinjaSCSI-3/32Bi driver for Linux - -1. Comment - This is Workbit corp.'s(http://www.workbit.co.jp/) NinjaSCSI-3 -for Linux. - -2. My Linux environment -Linux kernel: 2.4.7 / 2.2.19 -pcmcia-cs: 3.1.27 -gcc: gcc-2.95.4 -PC card: I-O data PCSC-F (NinjaSCSI-3) - I-O data CBSC-II in 16 bit mode (NinjaSCSI-32Bi) -SCSI device: I-O data CDPS-PX24 (CD-ROM drive) - Media Intelligent MMO-640GT (Optical disk drive) - -3. Install -[1] Check your PC card is true "NinjaSCSI-3" card. - If you installed pcmcia-cs already, pcmcia reports your card as UNKNOWN - card, and write ["WBT", "NinjaSCSI-3", "R1.0"] or some other string to - your console or log file. - You can also use "cardctl" program (this program is in pcmcia-cs source - code) to get more info. - -# cat /var/log/messages -... -Jan 2 03:45:06 lindberg cardmgr[78]: unsupported card in socket 1 -Jan 2 03:45:06 lindberg cardmgr[78]: product info: "WBT", "NinjaSCSI-3", "R1.0" -... -# cardctl ident -Socket 0: - no product info available -Socket 1: - product info: "IO DATA", "CBSC16 ", "1" - - -[2] Get the Linux kernel source, and extract it to /usr/src. - Because the NinjaSCSI driver requires some SCSI header files in Linux - kernel source, I recommend rebuilding your kernel; this eliminates - some versioning problems. -$ cd /usr/src -$ tar -zxvf linux-x.x.x.tar.gz -$ cd linux -$ make config -... - -[3] If you use this driver with Kernel 2.2, unpack pcmcia-cs in some directory - and make & install. This driver requires the pcmcia-cs header file. -$ cd /usr/src -$ tar zxvf cs-pcmcia-cs-3.x.x.tar.gz -... - -[4] Extract this driver's archive somewhere, and edit Makefile, then do make. -$ tar -zxvf nsp_cs-x.x.tar.gz -$ cd nsp_cs-x.x -$ emacs Makefile -... -$ make - -[5] Copy nsp_cs.ko to suitable place, like /lib/modules/<Kernel version>/pcmcia/ . - -[6] Add these lines to /etc/pcmcia/config . - If you use pcmcia-cs-3.1.8 or later, we can use "nsp_cs.conf" file. - So, you don't need to edit file. Just copy to /etc/pcmcia/ . - -------------------------------------- -device "nsp_cs" - class "scsi" module "nsp_cs" - -card "WorkBit NinjaSCSI-3" - version "WBT", "NinjaSCSI-3", "R1.0" - bind "nsp_cs" - -card "WorkBit NinjaSCSI-32Bi (16bit)" - version "WORKBIT", "UltraNinja-16", "1" - bind "nsp_cs" - -# OEM -card "WorkBit NinjaSCSI-32Bi (16bit) / IO-DATA" - version "IO DATA", "CBSC16 ", "1" - bind "nsp_cs" - -# OEM -card "WorkBit NinjaSCSI-32Bi (16bit) / KME-1" - version "KME ", "SCSI-CARD-001", "1" - bind "nsp_cs" -card "WorkBit NinjaSCSI-32Bi (16bit) / KME-2" - version "KME ", "SCSI-CARD-002", "1" - bind "nsp_cs" -card "WorkBit NinjaSCSI-32Bi (16bit) / KME-3" - version "KME ", "SCSI-CARD-003", "1" - bind "nsp_cs" -card "WorkBit NinjaSCSI-32Bi (16bit) / KME-4" - version "KME ", "SCSI-CARD-004", "1" - bind "nsp_cs" -------------------------------------- - -[7] Start (or restart) pcmcia-cs. -# /etc/rc.d/rc.pcmcia start (BSD style) -or -# /etc/init.d/pcmcia start (SYSV style) - - -4. History -See README.nin_cs . - -5. Caution - If you eject card when doing some operation for your SCSI device or suspend -your computer, you encount some *BAD* error like disk crash. - It works good when I using this driver right way. But I'm not guarantee -your data. Please backup your data when you use this driver. - -6. Known Bugs - In 2.4 kernel, you can't use 640MB Optical disk. This error comes from -high level SCSI driver. - -7. Testing - Please send me some reports(bug reports etc..) of this software. -When you send report, please tell me these or more. - card name - kernel version - your SCSI device name(hard drive, CD-ROM, etc...) - -8. Copyright - See GPL. - - -2001/08/08 yokota@netlab.is.tsukuba.ac.jp <YOKOTA Hiroshi> diff --git a/Documentation/scsi/aacraid.txt b/Documentation/scsi/aacraid.rst index 30f643f611b2..1904674b94f3 100644 --- a/Documentation/scsi/aacraid.txt +++ b/Documentation/scsi/aacraid.rst @@ -1,7 +1,11 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=================================== AACRAID Driver for Linux (take two) +=================================== Introduction -------------------------- +============ The aacraid driver adds support for Adaptec (http://www.adaptec.com) RAID controllers. This is a major rewrite from the original Adaptec supplied driver. It has significantly cleaned up both the code @@ -9,8 +13,11 @@ and the running binary size (the module is less than half the size of the original). Supported Cards/Chipsets -------------------------- +======================== + + =================== ======= ======================================= PCI ID (pci.ids) OEM Product + =================== ======= ======================================= 9005:0285:9005:0285 Adaptec 2200S (Vulcan) 9005:0285:9005:0286 Adaptec 2120S (Crusader) 9005:0285:9005:0287 Adaptec 2200S (Vulcan-2m) @@ -117,34 +124,54 @@ Supported Cards/Chipsets 9005:0285:108e:0286 SUN STK RAID INT (Cougar) 9005:0285:108e:0287 SUN STK RAID EXT (Prometheus) 9005:0285:108e:7aae SUN STK RAID EM (Narvi) + =================== ======= ======================================= People -------------------------- +====== + Alan Cox <alan@lxorguk.ukuu.org.uk> -Christoph Hellwig <hch@infradead.org> (updates for new-style PCI probing and SCSI host registration, - small cleanups/fixes) -Matt Domsch <matt_domsch@dell.com> (revision ioctl, adapter messages) -Deanna Bonds (non-DASD support, PAE fibs and 64 bit, added new adaptec controllers - added new ioctls, changed scsi interface to use new error handler, - increased the number of fibs and outstanding commands to a container) - - (fixed 64bit and 64G memory model, changed confusing naming convention - where fibs that go to the hardware are consistently called hw_fibs and - not just fibs like the name of the driver tracking structure) -Mark Salyzyn <Mark_Salyzyn@adaptec.com> Fixed panic issues and added some new product ids for upcoming hbas. Performance tuning, card failover and bug mitigations. + +Christoph Hellwig <hch@infradead.org> + +- updates for new-style PCI probing and SCSI host registration, + small cleanups/fixes + +Matt Domsch <matt_domsch@dell.com> + +- revision ioctl, adapter messages + +Deanna Bonds + +- non-DASD support, PAE fibs and 64 bit, added new adaptec controllers + added new ioctls, changed scsi interface to use new error handler, + increased the number of fibs and outstanding commands to a container +- fixed 64bit and 64G memory model, changed confusing naming convention + where fibs that go to the hardware are consistently called hw_fibs and + not just fibs like the name of the driver tracking structure + +Mark Salyzyn <Mark_Salyzyn@adaptec.com> + +- Fixed panic issues and added some new product ids for upcoming hbas. +- Performance tuning, card failover and bug mitigations. + Achim Leubner <Achim_Leubner@adaptec.com> -Original Driver +- Original Driver + ------------------------- + Adaptec Unix OEM Product Group Mailing List -------------------------- +============ + linux-scsi@vger.kernel.org (Interested parties troll here) Also note this is very different to Brian's original driver so don't expect him to support it. + Adaptec does support this driver. Contact Adaptec tech support or aacraid@adaptec.com Original by Brian Boerner February 2001 + Rewritten by Alan Cox, November 2001 diff --git a/Documentation/scsi/advansys.txt b/Documentation/scsi/advansys.rst index 4a3db62b7424..e0367e179696 100644 --- a/Documentation/scsi/advansys.txt +++ b/Documentation/scsi/advansys.rst @@ -1,3 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0 + +===================== +AdvanSys Driver Notes +===================== + AdvanSys (Advanced System Products, Inc.) manufactures the following RISC-based, Bus-Mastering, Fast (10 Mhz) and Ultra (20 Mhz) Narrow (8-bit transfer) SCSI Host Adapters for the ISA, EISA, VL, and PCI @@ -12,50 +18,51 @@ adapter detected. The number of CDBs used by the driver can be lowered in the BIOS by changing the 'Host Queue Size' adapter setting. Laptop Products: - ABP-480 - Bus-Master CardBus (16 CDB) + - ABP-480 - Bus-Master CardBus (16 CDB) Connectivity Products: - ABP510/5150 - Bus-Master ISA (240 CDB) - ABP5140 - Bus-Master ISA PnP (16 CDB) - ABP5142 - Bus-Master ISA PnP with floppy (16 CDB) - ABP902/3902 - Bus-Master PCI (16 CDB) - ABP3905 - Bus-Master PCI (16 CDB) - ABP915 - Bus-Master PCI (16 CDB) - ABP920 - Bus-Master PCI (16 CDB) - ABP3922 - Bus-Master PCI (16 CDB) - ABP3925 - Bus-Master PCI (16 CDB) - ABP930 - Bus-Master PCI (16 CDB) - ABP930U - Bus-Master PCI Ultra (16 CDB) - ABP930UA - Bus-Master PCI Ultra (16 CDB) - ABP960 - Bus-Master PCI MAC/PC (16 CDB) - ABP960U - Bus-Master PCI MAC/PC Ultra (16 CDB) + - ABP510/5150 - Bus-Master ISA (240 CDB) + - ABP5140 - Bus-Master ISA PnP (16 CDB) + - ABP5142 - Bus-Master ISA PnP with floppy (16 CDB) + - ABP902/3902 - Bus-Master PCI (16 CDB) + - ABP3905 - Bus-Master PCI (16 CDB) + - ABP915 - Bus-Master PCI (16 CDB) + - ABP920 - Bus-Master PCI (16 CDB) + - ABP3922 - Bus-Master PCI (16 CDB) + - ABP3925 - Bus-Master PCI (16 CDB) + - ABP930 - Bus-Master PCI (16 CDB) + - ABP930U - Bus-Master PCI Ultra (16 CDB) + - ABP930UA - Bus-Master PCI Ultra (16 CDB) + - ABP960 - Bus-Master PCI MAC/PC (16 CDB) + - ABP960U - Bus-Master PCI MAC/PC Ultra (16 CDB) Single Channel Products: - ABP542 - Bus-Master ISA with floppy (240 CDB) - ABP742 - Bus-Master EISA (240 CDB) - ABP842 - Bus-Master VL (240 CDB) - ABP940 - Bus-Master PCI (240 CDB) - ABP940U - Bus-Master PCI Ultra (240 CDB) - ABP940UA/3940UA - Bus-Master PCI Ultra (240 CDB) - ABP970 - Bus-Master PCI MAC/PC (240 CDB) - ABP970U - Bus-Master PCI MAC/PC Ultra (240 CDB) - ABP3960UA - Bus-Master PCI MAC/PC Ultra (240 CDB) - ABP940UW/3940UW - Bus-Master PCI Ultra-Wide (253 CDB) - ABP970UW - Bus-Master PCI MAC/PC Ultra-Wide (253 CDB) - ABP3940U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB) + - ABP542 - Bus-Master ISA with floppy (240 CDB) + - ABP742 - Bus-Master EISA (240 CDB) + - ABP842 - Bus-Master VL (240 CDB) + - ABP940 - Bus-Master PCI (240 CDB) + - ABP940U - Bus-Master PCI Ultra (240 CDB) + - ABP940UA/3940UA - Bus-Master PCI Ultra (240 CDB) + - ABP970 - Bus-Master PCI MAC/PC (240 CDB) + - ABP970U - Bus-Master PCI MAC/PC Ultra (240 CDB) + - ABP3960UA - Bus-Master PCI MAC/PC Ultra (240 CDB) + - ABP940UW/3940UW - Bus-Master PCI Ultra-Wide (253 CDB) + - ABP970UW - Bus-Master PCI MAC/PC Ultra-Wide (253 CDB) + - ABP3940U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB) Multi-Channel Products: - ABP752 - Dual Channel Bus-Master EISA (240 CDB Per Channel) - ABP852 - Dual Channel Bus-Master VL (240 CDB Per Channel) - ABP950 - Dual Channel Bus-Master PCI (240 CDB Per Channel) - ABP950UW - Dual Channel Bus-Master PCI Ultra-Wide (253 CDB Per Channel) - ABP980 - Four Channel Bus-Master PCI (240 CDB Per Channel) - ABP980U - Four Channel Bus-Master PCI Ultra (240 CDB Per Channel) - ABP980UA/3980UA - Four Channel Bus-Master PCI Ultra (16 CDB Per Chan.) - ABP3950U2W - Bus-Master PCI LVD/Ultra2-Wide and Ultra-Wide (253 CDB) - ABP3950U3W - Bus-Master PCI Dual LVD2/Ultra3-Wide (253 CDB) + - ABP752 - Dual Channel Bus-Master EISA (240 CDB Per Channel) + - ABP852 - Dual Channel Bus-Master VL (240 CDB Per Channel) + - ABP950 - Dual Channel Bus-Master PCI (240 CDB Per Channel) + - ABP950UW - Dual Channel Bus-Master PCI Ultra-Wide (253 CDB Per Channel) + - ABP980 - Four Channel Bus-Master PCI (240 CDB Per Channel) + - ABP980U - Four Channel Bus-Master PCI Ultra (240 CDB Per Channel) + - ABP980UA/3980UA - Four Channel Bus-Master PCI Ultra (16 CDB Per Chan.) + - ABP3950U2W - Bus-Master PCI LVD/Ultra2-Wide and Ultra-Wide (253 CDB) + - ABP3950U3W - Bus-Master PCI Dual LVD2/Ultra3-Wide (253 CDB) Driver Compile Time Options and Debugging +========================================= The following constants can be defined in the source file. @@ -88,26 +95,30 @@ The following constants can be defined in the source file. first three hex digits of the pseudo I/O Port must be set to 'deb' and the fourth hex digit specifies the debug level: 0 - F. The following command line will look for an adapter at 0x330 - and set the debug level to 2. + and set the debug level to 2:: linux advansys=0x330,0,0,0,0xdeb2 If the driver is built as a loadable module this variable can be defined when the driver is loaded. The following insmod command - will set the debug level to one. + will set the debug level to one:: insmod advansys.o asc_dbglvl=1 Debugging Message Levels: - 0: Errors Only - 1: High-Level Tracing - 2-N: Verbose Tracing + + + ==== ================== + 0 Errors Only + 1 High-Level Tracing + 2-N Verbose Tracing + ==== ================== To enable debug output to console, please make sure that: a. System and kernel logging is enabled (syslogd, klogd running). b. Kernel messages are routed to console output. Check - /etc/syslog.conf for an entry similar to this: + /etc/syslog.conf for an entry similar to this:: kern.* /dev/console @@ -120,8 +131,11 @@ The following constants can be defined in the source file. Alternatively you can enable printk() to console with this program. However, this is not the 'official' way to do this. + Debug output is logged in /var/log/messages. + :: + main() { syscall(103, 7, 0, 0); @@ -144,11 +158,11 @@ The following constants can be defined in the source file. Statistics are only available for kernels greater than or equal to v1.3.0 with the CONFIG_PROC_FS (/proc) file system configured. - AdvanSys SCSI adapter files have the following path name format: + AdvanSys SCSI adapter files have the following path name format:: /proc/scsi/advansys/{0,1,2,3,...} - This information can be displayed with cat. For example: + This information can be displayed with cat. For example:: cat /proc/scsi/advansys/0 @@ -156,6 +170,7 @@ The following constants can be defined in the source file. contain adapter and device configuration information. Driver LILO Option +================== If init/main.c is modified as described in the 'Directions for Adding the AdvanSys Driver to Linux' section (B.4.) above, the driver will @@ -167,17 +182,30 @@ affects searching for ISA and VL boards. Examples: 1. Eliminate I/O port scanning: - boot: linux advansys= - or - boot: linux advansys=0x0 + + boot:: + + linux advansys= + + or:: + + boot: linux advansys=0x0 + 2. Limit I/O port scanning to one I/O port: - boot: linux advansys=0x110 + + boot:: + + linux advansys=0x110 + 3. Limit I/O port scanning to four I/O ports: - boot: linux advansys=0x110,0x210,0x230,0x330 + + boot:: + + linux advansys=0x110,0x210,0x230,0x330 For a loadable module the same effect can be achieved by setting the 'asc_iopflag' variable and 'asc_ioport' array when loading -the driver, e.g. +the driver, e.g.:: insmod advansys.o asc_iopflag=1 asc_ioport=0x110,0x330 @@ -187,6 +215,7 @@ the 'Driver Compile Time Options and Debugging' section above for more information. Credits (Chronological Order) +============================= Bob Frey <bfrey@turbolinux.com.cn> wrote the AdvanSys SCSI driver and maintained it up to 3.3F. He continues to answer questions diff --git a/Documentation/scsi/aha152x.txt b/Documentation/scsi/aha152x.rst index 94848734ac66..7012b5c46d5d 100644 --- a/Documentation/scsi/aha152x.txt +++ b/Documentation/scsi/aha152x.rst @@ -1,7 +1,12 @@ -$Id: README.aha152x,v 1.2 1999/12/25 15:32:30 fischer Exp fischer $ +.. SPDX-License-Identifier: GPL-2.0 +.. include:: <isonum.txt> + +===================================================== Adaptec AHA-1520/1522 SCSI driver for Linux (aha152x) +===================================================== + +Copyright |copy| 1993-1999 Jürgen Fischer <fischer@norbit.de> -Copyright 1993-1999 Jürgen Fischer <fischer@norbit.de> TC1550 patches by Luuk van Dijk (ldz@xs4all.nl) @@ -14,8 +19,10 @@ less polling loops), has slightly higher throughput (at least on my ancient test box; a i486/33Mhz/20MB). -CONFIGURATION ARGUMENTS: +Configuration Arguments +======================= +============ ======================================== ====================== IOPORT base io address (0x340/0x140) IRQ interrupt level (9-12; default 11) SCSI_ID scsi id of controller (0-7; default 7) @@ -25,31 +32,38 @@ SYNCHRONOUS enable synchronous transfers (0/1; default 1 [on]) DELAY: bus reset delay (default 100) EXT_TRANS: enable extended translation (0/1: default 0 [off]) (see NOTES) +============ ======================================== ====================== + +Compile Time Configuration +========================== + +(go into AHA152X in drivers/scsi/Makefile): -COMPILE TIME CONFIGURATION (go into AHA152X in drivers/scsi/Makefile): +- DAUTOCONF + use configuration the controller reports (AHA-152x only) --DAUTOCONF - use configuration the controller reports (AHA-152x only) +- DSKIP_BIOSTEST + Don't test for BIOS signature (AHA-1510 or disabled BIOS) --DSKIP_BIOSTEST - Don't test for BIOS signature (AHA-1510 or disabled BIOS) +- DSETUP0="{ IOPORT, IRQ, SCSI_ID, RECONNECT, PARITY, SYNCHRONOUS, DELAY, EXT_TRANS }" + override for the first controller --DSETUP0="{ IOPORT, IRQ, SCSI_ID, RECONNECT, PARITY, SYNCHRONOUS, DELAY, EXT_TRANS }" - override for the first controller +- DSETUP1="{ IOPORT, IRQ, SCSI_ID, RECONNECT, PARITY, SYNCHRONOUS, DELAY, EXT_TRANS }" + override for the second controller --DSETUP1="{ IOPORT, IRQ, SCSI_ID, RECONNECT, PARITY, SYNCHRONOUS, DELAY, EXT_TRANS }" - override for the second controller +- DAHA152X_DEBUG + enable debugging output --DAHA152X_DEBUG - enable debugging output +- DAHA152X_STAT + enable some statistics --DAHA152X_STAT - enable some statistics +LILO Command Line Options +========================= -LILO COMMAND LINE OPTIONS: + :: -aha152x=<IOPORT>[,<IRQ>[,<SCSI-ID>[,<RECONNECT>[,<PARITY>[,<SYNCHRONOUS>[,<DELAY> [,<EXT_TRANS]]]]]]] + aha152x=<IOPORT>[,<IRQ>[,<SCSI-ID>[,<RECONNECT>[,<PARITY>[,<SYNCHRONOUS>[,<DELAY> [,<EXT_TRANS]]]]]]] The normal configuration can be overridden by specifying a command line. When you do this, the BIOS test is skipped. Entered values have to be @@ -58,17 +72,21 @@ aha152x=<IOPORT>[,<IRQ>[,<SCSI-ID>[,<RECONNECT>[,<PARITY>[,<SYNCHRONOUS>[,<DELAY For two controllers use the aha152x statement twice. -SYMBOLS FOR MODULE CONFIGURATION: +Symbols for Module Configuration +================================ Choose from 2 alternatives: -1. specify everything (old) +1. specify everything (old):: + + aha152x=IOPORT,IRQ,SCSI_ID,RECONNECT,PARITY,SYNCHRONOUS,DELAY,EXT_TRANS -aha152x=IOPORT,IRQ,SCSI_ID,RECONNECT,PARITY,SYNCHRONOUS,DELAY,EXT_TRANS configuration override for first controller + :: + + aha152x1=IOPORT,IRQ,SCSI_ID,RECONNECT,PARITY,SYNCHRONOUS,DELAY,EXT_TRANS -aha152x1=IOPORT,IRQ,SCSI_ID,RECONNECT,PARITY,SYNCHRONOUS,DELAY,EXT_TRANS configuration override for second controller 2. specify only what you need to (irq or io is required; new) @@ -101,7 +119,8 @@ exttrans=EXTTRANS0[,EXTTRANS1] If you use both alternatives the first will be taken. -NOTES ON EXT_TRANS: +Notes on EXT_TRANS +================== SCSI uses block numbers to address blocks/sectors on a device. The BIOS uses a cylinder/head/sector addressing scheme (C/H/S) @@ -150,8 +169,9 @@ geometry right in most cases: - for disks<1GB: use default translation (C/32/64) - for disks>1GB: + - take current geometry from the partition table - (using scsicam_bios_param and accept only `valid' geometries, + (using scsicam_bios_param and accept only 'valid' geometries, ie. either (C/32/64) or (C/63/255)). This can be extended translation even if it's not enabled in the driver. @@ -161,7 +181,8 @@ geometry right in most cases: disks. -REFERENCES USED: +References Used +=============== "AIC-6260 SCSI Chip Specification", Adaptec Corporation. @@ -177,7 +198,7 @@ REFERENCES USED: Drew Eckhardt (drew@cs.colorado.edu) - Eric Youngdale (eric@andante.org) + Eric Youngdale (eric@andante.org) special thanks to Eric Youngdale for the free(!) supplying the documentation on the chip. diff --git a/Documentation/scsi/aic79xx.rst b/Documentation/scsi/aic79xx.rst new file mode 100644 index 000000000000..071ff5111a4f --- /dev/null +++ b/Documentation/scsi/aic79xx.rst @@ -0,0 +1,593 @@ +.. SPDX-License-Identifier: GPL-2.0 +.. include:: <isonum.txt> + +=================================== +Adaptec Ultra320 Family Manager Set +=================================== + +README for The Linux Operating System + +.. The following information is available in this file: + + 1. Supported Hardware + 2. Version History + 3. Command Line Options + 4. Additional Notes + 5. Contacting Adaptec + + +1. Supported Hardware +===================== + + The following Adaptec SCSI Host Adapters are supported by this + driver set. + + ============= ========================================= + Ultra320 ASIC Description + ============= ========================================= + AIC-7901A Single Channel 64-bit PCI-X 133MHz to + Ultra320 SCSI ASIC + AIC-7901B Single Channel 64-bit PCI-X 133MHz to + Ultra320 SCSI ASIC with Retained Training + AIC-7902A4 Dual Channel 64-bit PCI-X 133MHz to + Ultra320 SCSI ASIC + AIC-7902B Dual Channel 64-bit PCI-X 133MHz to + Ultra320 SCSI ASIC with Retained Training + ============= ========================================= + + ========================== ===================================== ============ + Ultra320 Adapters Description ASIC + ========================== ===================================== ============ + Adaptec SCSI Card 39320 Dual Channel 64-bit PCI-X 133MHz to 7902A4/7902B + Ultra320 SCSI Card (one external + 68-pin, two internal 68-pin) + Adaptec SCSI Card 39320A Dual Channel 64-bit PCI-X 133MHz to 7902B + Ultra320 SCSI Card (one external + 68-pin, two internal 68-pin) + Adaptec SCSI Card 39320D Dual Channel 64-bit PCI-X 133MHz to 7902A4 + Ultra320 SCSI Card (two external VHDC + and one internal 68-pin) + Adaptec SCSI Card 39320D Dual Channel 64-bit PCI-X 133MHz to 7902A4 + Ultra320 SCSI Card (two external VHDC + and one internal 68-pin) based on the + AIC-7902B ASIC + Adaptec SCSI Card 29320 Single Channel 64-bit PCI-X 133MHz to 7901A + Ultra320 SCSI Card (one external + 68-pin, two internal 68-pin, one + internal 50-pin) + Adaptec SCSI Card 29320A Single Channel 64-bit PCI-X 133MHz to 7901B + Ultra320 SCSI Card (one external + 68-pin, two internal 68-pin, one + internal 50-pin) + Adaptec SCSI Card 29320LP Single Channel 64-bit Low Profile 7901A + PCI-X 133MHz to Ultra320 SCSI Card + (One external VHDC, one internal + 68-pin) + Adaptec SCSI Card 29320ALP Single Channel 64-bit Low Profile 7901B + PCI-X 133MHz to Ultra320 SCSI Card + (One external VHDC, one internal + 68-pin) + ========================== ===================================== ============ + +2. Version History +================== + + + * 3.0 (December 1st, 2005) + - Updated driver to use SCSI transport class infrastructure + - Upported sequencer and core fixes from adaptec released + version 2.0.15 of the driver. + + * 1.3.11 (July 11, 2003) + - Fix several deadlock issues. + - Add 29320ALP and 39320B Id's. + + * 1.3.10 (June 3rd, 2003) + - Align the SCB_TAG field on a 16byte boundary. This avoids + SCB corruption on some PCI-33 busses. + - Correct non-zero luns on Rev B. hardware. + - Update for change in 2.5.X SCSI proc FS interface. + - When negotiation async via an 8bit WDTR message, send + an SDTR with an offset of 0 to be sure the target + knows we are async. This works around a firmware defect + in the Quantum Atlas 10K. + - Implement controller suspend and resume. + - Clear PCI error state during driver attach so that we + don't disable memory mapped I/O due to a stray write + by some other driver probe that occurred before we + claimed the controller. + + * 1.3.9 (May 22nd, 2003) + - Fix compiler errors. + - Remove S/G splitting for segments that cross a 4GB boundary. + This is guaranteed not to happen in Linux. + - Add support for scsi_report_device_reset() found in + 2.5.X kernels. + - Add 7901B support. + - Simplify handling of the packetized lun Rev A workaround. + - Correct and simplify handling of the ignore wide residue + message. The previous code would fail to report a residual + if the transaction data length was even and we received + an IWR message. + + * 1.3.8 (April 29th, 2003) + - Fix types accessed via the command line interface code. + - Perform a few firmware optimizations. + - Fix "Unexpected PKT busfree" errors. + - Use a sequencer interrupt to notify the host of + commands with bad status. We defer the notification + until there are no outstanding selections to ensure + that the host is interrupted for as short a time as + possible. + - Remove pre-2.2.X support. + - Add support for new 2.5.X interrupt API. + - Correct big-endian architecture support. + + * 1.3.7 (April 16th, 2003) + - Use del_timer_sync() to ensure that no timeouts + are pending during controller shutdown. + - For pre-2.5.X kernels, carefully adjust our segment + list size to avoid SCSI malloc pool fragmentation. + - Cleanup channel display in our /proc output. + - Workaround duplicate device entries in the mid-layer + device list during add-single-device. + + * 1.3.6 (March 28th, 2003) + - Correct a double free in the Domain Validation code. + - Correct a reference to free'ed memory during controller + shutdown. + - Reset the bus on an SE->LVD change. This is required + to reset our transceivers. + + * 1.3.5 (March 24th, 2003) + - Fix a few register window mode bugs. + - Include read streaming in the PPR flags we display in + diagnostics as well as /proc. + - Add PCI hot plug support for 2.5.X kernels. + - Correct default precompensation value for RevA hardware. + - Fix Domain Validation thread shutdown. + - Add a firmware workaround to make the LED blink + brighter during packetized operations on the H2A4. + - Correct /proc display of user read streaming settings. + - Simplify driver locking by releasing the io_request_lock + upon driver entry from the mid-layer. + - Cleanup command line parsing and move much of this code + to aiclib. + + * 1.3.4 (February 28th, 2003) + - Correct a race condition in our error recovery handler. + - Allow Test Unit Ready commands to take a full 5 seconds + during Domain Validation. + + * 1.3.2 (February 19th, 2003) + - Correct a Rev B. regression due to the GEM318 + compatibility fix included in 1.3.1. + + * 1.3.1 (February 11th, 2003) + - Add support for the 39320A. + - Improve recovery for certain PCI-X errors. + - Fix handling of LQ/DATA/LQ/DATA for the + same write transaction that can occur without + interveining training. + - Correct compatibility issues with the GEM318 + enclosure services device. + - Correct data corruption issue that occurred under + high tag depth write loads. + - Adapt to a change in the 2.5.X daemonize() API. + - Correct a "Missing case in ahd_handle_scsiint" panic. + + * 1.3.0 (January 21st, 2003) + - Full regression testing for all U320 products completed. + - Added abort and target/lun reset error recovery handler and + interrupt coalescing. + + * 1.2.0 (November 14th, 2002) + - Added support for Domain Validation + - Add support for the Hewlett-Packard version of the 39320D + and AIC-7902 adapters. + + Support for previous adapters has not been fully tested and should + only be used at the customer's own risk. + + * 1.1.1 (September 24th, 2002) + - Added support for the Linux 2.5.X kernel series + + * 1.1.0 (September 17th, 2002) + - Added support for four additional SCSI products: + ASC-39320, ASC-29320, ASC-29320LP, AIC-7901. + + * 1.0.0 (May 30th, 2002) + - Initial driver release. + + * 2.1. Software/Hardware Features + - Support for the SPI-4 "Ultra320" standard: + - 320MB/s transfer rates + - Packetized SCSI Protocol at 160MB/s and 320MB/s + - Quick Arbitration Selection (QAS) + - Retained Training Information (Rev B. ASIC only) + - Interrupt Coalescing + - Initiator Mode (target mode not currently + supported) + - Support for the PCI-X standard up to 133MHz + - Support for the PCI v2.2 standard + - Domain Validation + + * 2.2. Operating System Support: + - Redhat Linux 7.2, 7.3, 8.0, Advanced Server 2.1 + - SuSE Linux 7.3, 8.0, 8.1, Enterprise Server 7 + - only Intel and AMD x86 supported at this time + - >4GB memory configurations supported. + + Refer to the User's Guide for more details on this. + +3. Command Line Options +======================= + + .. Warning:: + + ALTERING OR ADDING THESE DRIVER PARAMETERS + INCORRECTLY CAN RENDER YOUR SYSTEM INOPERABLE. + USE THEM WITH CAUTION. + + Put a .conf file in the /etc/modprobe.d/ directory and add/edit a + line containing ``options aic79xx aic79xx=[command[,command...]]`` where + ``command`` is one or more of the following: + + +verbose + :Definition: enable additional informative messages during driver operation. + :Possible Values: This option is a flag + :Default Value: disabled + +debug:[value] + :Definition: Enables various levels of debugging information + The bit definitions for the debugging mask can + be found in drivers/scsi/aic7xxx/aic79xx.h under + the "Debug" heading. + :Possible Values: 0x0000 = no debugging, 0xffff = full debugging + :Default Value: 0x0000 + +no_reset + :Definition: Do not reset the bus during the initial probe + phase + :Possible Values: This option is a flag + :Default Value: disabled + +extended + :Definition: Force extended translation on the controller + :Possible Values: This option is a flag + :Default Value: disabled + +periodic_otag + :Definition: Send an ordered tag periodically to prevent + tag starvation. Needed for some older devices + :Possible Values: This option is a flag + :Default Value: disabled + +reverse_scan + :Definition: Probe the scsi bus in reverse order, starting with target 15 + :Possible Values: This option is a flag + :Default Value: disabled + +global_tag_depth + :Definition: Global tag depth for all targets on all busses. + This option sets the default tag depth which + may be selectively overridden vi the tag_info + option. + + :Possible Values: 1 - 253 + :Default Value: 32 + +tag_info:{{value[,value...]}[,{value[,value...]}...]} + :Definition: Set the per-target tagged queue depth on a + per controller basis. Both controllers and targets + may be omitted indicating that they should retain + the default tag depth. + + :Possible Values: 1 - 253 + :Default Value: 32 + + Examples: + + + :: + + tag_info:{{16,32,32,64,8,8,,32,32,32,32,32,32,32,32,32} + + On Controller 0 + + - specifies a tag depth of 16 for target 0 + - specifies a tag depth of 64 for target 3 + - specifies a tag depth of 8 for targets 4 and 5 + - leaves target 6 at the default + - specifies a tag depth of 32 for targets 1,2,7-15 + + All other targets retain the default depth. + + :: + + tag_info:{{},{32,,32}} + + On Controller 1 + + - specifies a tag depth of 32 for targets 0 and 2 + + All other targets retain the default depth. + + +rd_strm: {rd_strm_bitmask[,rd_strm_bitmask...]} + :Definition: Enable read streaming on a per target basis. + The rd_strm_bitmask is a 16 bit hex value in which + each bit represents a target. Setting the target's + bit to '1' enables read streaming for that + target. Controllers may be omitted indicating that + they should retain the default read streaming setting. + + Examples: + + :: + + rd_strm:{0x0041} + + On Controller 0 + + - enables read streaming for targets 0 and 6. + - disables read streaming for targets 1-5,7-15. + + All other targets retain the default read + streaming setting. + + :: + + rd_strm:{0x0023,,0xFFFF} + + On Controller 0 + + - enables read streaming for targets 1,2, and 5. + - disables read streaming for targets 3,4,6-15. + + On Controller 2 + + - enables read streaming for all targets. + + All other targets retain the default read + streaming setting. + + :Possible Values: 0x0000 - 0xffff + :Default Value: 0x0000 + +dv: {value[,value...]} + :Definition: Set Domain Validation Policy on a per-controller basis. + Controllers may be omitted indicating that + they should retain the default read streaming setting. + + :Possible Values: + + ==== =============================== + < 0 Use setting from serial EEPROM. + 0 Disable DV + > 0 Enable DV + ==== =============================== + + :Default Value: DV Serial EEPROM configuration setting. + + Example: + + :: + + dv:{-1,0,,1,1,0} + + - On Controller 0 leave DV at its default setting. + - On Controller 1 disable DV. + - Skip configuration on Controller 2. + - On Controllers 3 and 4 enable DV. + - On Controller 5 disable DV. + +seltime:[value] + :Definition: Specifies the selection timeout value + :Possible Values: 0 = 256ms, 1 = 128ms, 2 = 64ms, 3 = 32ms + :Default Value: 0 + +.. Warning: + + The following three options should only be changed at + the direction of a technical support representative. + + +precomp: {value[,value...]} + :Definition: Set IO Cell precompensation value on a per-controller basis. + Controllers may be omitted indicating that + they should retain the default precompensation setting. + + :Possible Values: 0 - 7 + :Default Value: Varies based on chip revision + + Examples: + + :: + + precomp:{0x1} + + On Controller 0 set precompensation to 1. + + :: + + precomp:{1,,7} + + - On Controller 0 set precompensation to 1. + - On Controller 2 set precompensation to 8. + +slewrate: {value[,value...]} + :Definition: Set IO Cell slew rate on a per-controller basis. + Controllers may be omitted indicating that + they should retain the default slew rate setting. + + :Possible Values: 0 - 15 + :Default Value: Varies based on chip revision + + Examples: + + :: + + slewrate:{0x1} + + - On Controller 0 set slew rate to 1. + + :: + + slewrate :{1,,8} + + - On Controller 0 set slew rate to 1. + - On Controller 2 set slew rate to 8. + +amplitude: {value[,value...]} + :Definition: Set IO Cell signal amplitude on a per-controller basis. + Controllers may be omitted indicating that + they should retain the default read streaming setting. + + :Possible Values: 1 - 7 + :Default Value: Varies based on chip revision + + Examples: + + :: + + amplitude:{0x1} + + On Controller 0 set amplitude to 1. + + :: + + amplitude :{1,,7} + + - On Controller 0 set amplitude to 1. + - On Controller 2 set amplitude to 7. + +Example:: + + options aic79xx aic79xx=verbose,rd_strm:{{0x0041}} + +enables verbose output in the driver and turns read streaming on +for targets 0 and 6 of Controller 0. + +4. Additional Notes +=================== + +4.1. Known/Unresolved or FYI Issues +----------------------------------- + + * Under SuSE Linux Enterprise 7, the driver may fail to operate + correctly due to a problem with PCI interrupt routing in the + Linux kernel. Please contact SuSE for an updated Linux + kernel. + +4.2. Third-Party Compatibility Issues +------------------------------------- + + * Adaptec only supports Ultra320 hard drives running + the latest firmware available. Please check with + your hard drive manufacturer to ensure you have the + latest version. + +4.3. Operating System or Technology Limitations +----------------------------------------------- + + * PCI Hot Plug is untested and may cause the operating system + to stop responding. + * Luns that are not numbered contiguously starting with 0 might not + be automatically probed during system startup. This is a limitation + of the OS. Please contact your Linux vendor for instructions on + manually probing non-contiguous luns. + * Using the Driver Update Disk version of this package during OS + installation under RedHat might result in two versions of this + driver being installed into the system module directory. This + might cause problems with the /sbin/mkinitrd program and/or + other RPM packages that try to install system modules. The best + way to correct this once the system is running is to install + the latest RPM package version of this driver, available from + http://www.adaptec.com. + + +5. Adaptec Customer Support +=========================== + + A Technical Support Identification (TSID) Number is required for + Adaptec technical support. + + - The 12-digit TSID can be found on the white barcode-type label + included inside the box with your product. The TSID helps us + provide more efficient service by accurately identifying your + product and support status. + + Support Options + - Search the Adaptec Support Knowledgebase (ASK) at + http://ask.adaptec.com for articles, troubleshooting tips, and + frequently asked questions about your product. + - For support via Email, submit your question to Adaptec's + Technical Support Specialists at http://ask.adaptec.com/. + + North America + - Visit our Web site at http://www.adaptec.com/. + - For information about Adaptec's support options, call + 408-957-2550, 24 hours a day, 7 days a week. + - To speak with a Technical Support Specialist, + + * For hardware products, call 408-934-7274, + Monday to Friday, 3:00 am to 5:00 pm, PDT. + * For RAID and Fibre Channel products, call 321-207-2000, + Monday to Friday, 3:00 am to 5:00 pm, PDT. + + To expedite your service, have your computer with you. + - To order Adaptec products, including accessories and cables, + call 408-957-7274. To order cables online go to + http://www.adaptec.com/buy-cables/. + + Europe + - Visit our Web site at http://www.adaptec.com/en-US/_common/world_index. + - To speak with a Technical Support Specialist, call, or email, + + * German: +49 89 4366 5522, Monday-Friday, 9:00-17:00 CET, + http://ask-de.adaptec.com/. + * French: +49 89 4366 5533, Monday-Friday, 9:00-17:00 CET, + http://ask-fr.adaptec.com/. + * English: +49 89 4366 5544, Monday-Friday, 9:00-17:00 GMT, + http://ask.adaptec.com/. + + - You can order Adaptec cables online at + http://www.adaptec.com/buy-cables/. + + Japan + - Visit our web site at http://www.adaptec.co.jp/. + - To speak with a Technical Support Specialist, call + +81 3 5308 6120, Monday-Friday, 9:00 a.m. to 12:00 p.m., + 1:00 p.m. to 6:00 p.m. + +Copyright |copy| 2003 Adaptec Inc. 691 S. Milpitas Blvd., Milpitas CA 95035 USA. +All rights reserved. + +You are permitted to redistribute, use and modify this README file in whole +or in part in conjunction with redistribution of software governed by the +General Public License, provided that the following conditions are met: + +1. Redistributions of README file must retain the above copyright + notice, this list of conditions, and the following disclaimer, + without modification. +2. The name of the author may not be used to endorse or promote products + derived from this software without specific prior written permission. +3. Modifications or new contributions must be attributed in a copyright + notice identifying the author ("Contributor") and added below the + original copyright notice. The copyright notice is for purposes of + identifying contributors and should not be deemed as permission to alter + the permissions given by Adaptec. + +THIS README FILE IS PROVIDED BY ADAPTEC AND CONTRIBUTORS ``AS IS`` AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ANY +WARRANTIES OF NON-INFRINGEMENT OR THE IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +ADAPTEC OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS README +FILE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/Documentation/scsi/aic79xx.txt b/Documentation/scsi/aic79xx.txt deleted file mode 100644 index e2d3273000d4..000000000000 --- a/Documentation/scsi/aic79xx.txt +++ /dev/null @@ -1,497 +0,0 @@ -==================================================================== -= Adaptec Ultra320 Family Manager Set = -= = -= README for = -= The Linux Operating System = -==================================================================== - -The following information is available in this file: - - 1. Supported Hardware - 2. Version History - 3. Command Line Options - 4. Additional Notes - 5. Contacting Adaptec - - -1. Supported Hardware - - The following Adaptec SCSI Host Adapters are supported by this - driver set. - - Ultra320 ASIC Description - ---------------------------------------------------------------- - AIC-7901A Single Channel 64-bit PCI-X 133MHz to - Ultra320 SCSI ASIC - AIC-7901B Single Channel 64-bit PCI-X 133MHz to - Ultra320 SCSI ASIC with Retained Training - AIC-7902A4 Dual Channel 64-bit PCI-X 133MHz to - Ultra320 SCSI ASIC - AIC-7902B Dual Channel 64-bit PCI-X 133MHz to - Ultra320 SCSI ASIC with Retained Training - - Ultra320 Adapters Description ASIC - -------------------------------------------------------------------------- - Adaptec SCSI Card 39320 Dual Channel 64-bit PCI-X 133MHz to 7902A4/7902B - Ultra320 SCSI Card (one external - 68-pin, two internal 68-pin) - Adaptec SCSI Card 39320A Dual Channel 64-bit PCI-X 133MHz to 7902B - Ultra320 SCSI Card (one external - 68-pin, two internal 68-pin) - Adaptec SCSI Card 39320D Dual Channel 64-bit PCI-X 133MHz to 7902A4 - Ultra320 SCSI Card (two external VHDC - and one internal 68-pin) - Adaptec SCSI Card 39320D Dual Channel 64-bit PCI-X 133MHz to 7902A4 - Ultra320 SCSI Card (two external VHDC - and one internal 68-pin) based on the - AIC-7902B ASIC - Adaptec SCSI Card 29320 Single Channel 64-bit PCI-X 133MHz to 7901A - Ultra320 SCSI Card (one external - 68-pin, two internal 68-pin, one - internal 50-pin) - Adaptec SCSI Card 29320A Single Channel 64-bit PCI-X 133MHz to 7901B - Ultra320 SCSI Card (one external - 68-pin, two internal 68-pin, one - internal 50-pin) - Adaptec SCSI Card 29320LP Single Channel 64-bit Low Profile 7901A - PCI-X 133MHz to Ultra320 SCSI Card - (One external VHDC, one internal - 68-pin) - Adaptec SCSI Card 29320ALP Single Channel 64-bit Low Profile 7901B - PCI-X 133MHz to Ultra320 SCSI Card - (One external VHDC, one internal - 68-pin) -2. Version History - - 3.0 (December 1st, 2005) - - Updated driver to use SCSI transport class infrastructure - - Upported sequencer and core fixes from adaptec released - version 2.0.15 of the driver. - - 1.3.11 (July 11, 2003) - - Fix several deadlock issues. - - Add 29320ALP and 39320B Id's. - - 1.3.10 (June 3rd, 2003) - - Align the SCB_TAG field on a 16byte boundary. This avoids - SCB corruption on some PCI-33 busses. - - Correct non-zero luns on Rev B. hardware. - - Update for change in 2.5.X SCSI proc FS interface. - - When negotiation async via an 8bit WDTR message, send - an SDTR with an offset of 0 to be sure the target - knows we are async. This works around a firmware defect - in the Quantum Atlas 10K. - - Implement controller suspend and resume. - - Clear PCI error state during driver attach so that we - don't disable memory mapped I/O due to a stray write - by some other driver probe that occurred before we - claimed the controller. - - 1.3.9 (May 22nd, 2003) - - Fix compiler errors. - - Remove S/G splitting for segments that cross a 4GB boundary. - This is guaranteed not to happen in Linux. - - Add support for scsi_report_device_reset() found in - 2.5.X kernels. - - Add 7901B support. - - Simplify handling of the packetized lun Rev A workaround. - - Correct and simplify handling of the ignore wide residue - message. The previous code would fail to report a residual - if the transaction data length was even and we received - an IWR message. - - 1.3.8 (April 29th, 2003) - - Fix types accessed via the command line interface code. - - Perform a few firmware optimizations. - - Fix "Unexpected PKT busfree" errors. - - Use a sequencer interrupt to notify the host of - commands with bad status. We defer the notification - until there are no outstanding selections to ensure - that the host is interrupted for as short a time as - possible. - - Remove pre-2.2.X support. - - Add support for new 2.5.X interrupt API. - - Correct big-endian architecture support. - - 1.3.7 (April 16th, 2003) - - Use del_timer_sync() to ensure that no timeouts - are pending during controller shutdown. - - For pre-2.5.X kernels, carefully adjust our segment - list size to avoid SCSI malloc pool fragmentation. - - Cleanup channel display in our /proc output. - - Workaround duplicate device entries in the mid-layer - device list during add-single-device. - - 1.3.6 (March 28th, 2003) - - Correct a double free in the Domain Validation code. - - Correct a reference to free'ed memory during controller - shutdown. - - Reset the bus on an SE->LVD change. This is required - to reset our transceivers. - - 1.3.5 (March 24th, 2003) - - Fix a few register window mode bugs. - - Include read streaming in the PPR flags we display in - diagnostics as well as /proc. - - Add PCI hot plug support for 2.5.X kernels. - - Correct default precompensation value for RevA hardware. - - Fix Domain Validation thread shutdown. - - Add a firmware workaround to make the LED blink - brighter during packetized operations on the H2A4. - - Correct /proc display of user read streaming settings. - - Simplify driver locking by releasing the io_request_lock - upon driver entry from the mid-layer. - - Cleanup command line parsing and move much of this code - to aiclib. - - 1.3.4 (February 28th, 2003) - - Correct a race condition in our error recovery handler. - - Allow Test Unit Ready commands to take a full 5 seconds - during Domain Validation. - - 1.3.2 (February 19th, 2003) - - Correct a Rev B. regression due to the GEM318 - compatibility fix included in 1.3.1. - - 1.3.1 (February 11th, 2003) - - Add support for the 39320A. - - Improve recovery for certain PCI-X errors. - - Fix handling of LQ/DATA/LQ/DATA for the - same write transaction that can occur without - interveining training. - - Correct compatibility issues with the GEM318 - enclosure services device. - - Correct data corruption issue that occurred under - high tag depth write loads. - - Adapt to a change in the 2.5.X daemonize() API. - - Correct a "Missing case in ahd_handle_scsiint" panic. - - 1.3.0 (January 21st, 2003) - - Full regression testing for all U320 products completed. - - Added abort and target/lun reset error recovery handler and - interrupt coalescing. - - 1.2.0 (November 14th, 2002) - - Added support for Domain Validation - - Add support for the Hewlett-Packard version of the 39320D - and AIC-7902 adapters. - Support for previous adapters has not been fully tested and should - only be used at the customer's own risk. - - 1.1.1 (September 24th, 2002) - - Added support for the Linux 2.5.X kernel series - - 1.1.0 (September 17th, 2002) - - Added support for four additional SCSI products: - ASC-39320, ASC-29320, ASC-29320LP, AIC-7901. - - 1.0.0 (May 30th, 2002) - - Initial driver release. - - 2.1. Software/Hardware Features - - Support for the SPI-4 "Ultra320" standard: - - 320MB/s transfer rates - - Packetized SCSI Protocol at 160MB/s and 320MB/s - - Quick Arbitration Selection (QAS) - - Retained Training Information (Rev B. ASIC only) - - Interrupt Coalescing - - Initiator Mode (target mode not currently - supported) - - Support for the PCI-X standard up to 133MHz - - Support for the PCI v2.2 standard - - Domain Validation - - 2.2. Operating System Support: - - Redhat Linux 7.2, 7.3, 8.0, Advanced Server 2.1 - - SuSE Linux 7.3, 8.0, 8.1, Enterprise Server 7 - - only Intel and AMD x86 supported at this time - - >4GB memory configurations supported. - - Refer to the User's Guide for more details on this. - -3. Command Line Options - - WARNING: ALTERING OR ADDING THESE DRIVER PARAMETERS - INCORRECTLY CAN RENDER YOUR SYSTEM INOPERABLE. - USE THEM WITH CAUTION. - - Put a .conf file in the /etc/modprobe.d/ directory and add/edit a - line containing 'options aic79xx aic79xx=[command[,command...]]' where - 'command' is one or more of the following: - ----------------------------------------------------------------- - Option: verbose - Definition: enable additional informative messages during - driver operation. - Possible Values: This option is a flag - Default Value: disabled - ----------------------------------------------------------------- - Option: debug:[value] - Definition: Enables various levels of debugging information - The bit definitions for the debugging mask can - be found in drivers/scsi/aic7xxx/aic79xx.h under - the "Debug" heading. - Possible Values: 0x0000 = no debugging, 0xffff = full debugging - Default Value: 0x0000 - ----------------------------------------------------------------- - Option: no_reset - Definition: Do not reset the bus during the initial probe - phase - Possible Values: This option is a flag - Default Value: disabled - ----------------------------------------------------------------- - Option: extended - Definition: Force extended translation on the controller - Possible Values: This option is a flag - Default Value: disabled - ----------------------------------------------------------------- - Option: periodic_otag - Definition: Send an ordered tag periodically to prevent - tag starvation. Needed for some older devices - Possible Values: This option is a flag - Default Value: disabled - ----------------------------------------------------------------- - Option: reverse_scan - Definition: Probe the scsi bus in reverse order, starting - with target 15 - Possible Values: This option is a flag - Default Value: disabled - ----------------------------------------------------------------- - Option: global_tag_depth - Definition: Global tag depth for all targets on all busses. - This option sets the default tag depth which - may be selectively overridden vi the tag_info - option. - Possible Values: 1 - 253 - Default Value: 32 - ----------------------------------------------------------------- - Option: tag_info:{{value[,value...]}[,{value[,value...]}...]} - Definition: Set the per-target tagged queue depth on a - per controller basis. Both controllers and targets - may be omitted indicating that they should retain - the default tag depth. - Examples: tag_info:{{16,32,32,64,8,8,,32,32,32,32,32,32,32,32,32} - On Controller 0 - specifies a tag depth of 16 for target 0 - specifies a tag depth of 64 for target 3 - specifies a tag depth of 8 for targets 4 and 5 - leaves target 6 at the default - specifies a tag depth of 32 for targets 1,2,7-15 - All other targets retain the default depth. - - tag_info:{{},{32,,32}} - On Controller 1 - specifies a tag depth of 32 for targets 0 and 2 - All other targets retain the default depth. - - Possible Values: 1 - 253 - Default Value: 32 - ----------------------------------------------------------------- - Option: rd_strm: {rd_strm_bitmask[,rd_strm_bitmask...]} - Definition: Enable read streaming on a per target basis. - The rd_strm_bitmask is a 16 bit hex value in which - each bit represents a target. Setting the target's - bit to '1' enables read streaming for that - target. Controllers may be omitted indicating that - they should retain the default read streaming setting. - Example: rd_strm:{0x0041} - On Controller 0 - enables read streaming for targets 0 and 6. - disables read streaming for targets 1-5,7-15. - All other targets retain the default read - streaming setting. - Example: rd_strm:{0x0023,,0xFFFF} - On Controller 0 - enables read streaming for targets 1,2, and 5. - disables read streaming for targets 3,4,6-15. - On Controller 2 - enables read streaming for all targets. - All other targets retain the default read - streaming setting. - - Possible Values: 0x0000 - 0xffff - Default Value: 0x0000 - ----------------------------------------------------------------- - Option: dv: {value[,value...]} - Definition: Set Domain Validation Policy on a per-controller basis. - Controllers may be omitted indicating that - they should retain the default read streaming setting. - Example: dv:{-1,0,,1,1,0} - On Controller 0 leave DV at its default setting. - On Controller 1 disable DV. - Skip configuration on Controller 2. - On Controllers 3 and 4 enable DV. - On Controller 5 disable DV. - - Possible Values: < 0 Use setting from serial EEPROM. - 0 Disable DV - > 0 Enable DV - Default Value: DV Serial EEPROM configuration setting. - ----------------------------------------------------------------- - Option: seltime:[value] - Definition: Specifies the selection timeout value - Possible Values: 0 = 256ms, 1 = 128ms, 2 = 64ms, 3 = 32ms - Default Value: 0 - ----------------------------------------------------------------- - - *** The following three options should only be changed at *** - *** the direction of a technical support representative. *** - - ----------------------------------------------------------------- - Option: precomp: {value[,value...]} - Definition: Set IO Cell precompensation value on a per-controller - basis. - Controllers may be omitted indicating that - they should retain the default precompensation setting. - Example: precomp:{0x1} - On Controller 0 set precompensation to 1. - Example: precomp:{1,,7} - On Controller 0 set precompensation to 1. - On Controller 2 set precompensation to 8. - - Possible Values: 0 - 7 - Default Value: Varies based on chip revision - ----------------------------------------------------------------- - Option: slewrate: {value[,value...]} - Definition: Set IO Cell slew rate on a per-controller basis. - Controllers may be omitted indicating that - they should retain the default slew rate setting. - Example: slewrate:{0x1} - On Controller 0 set slew rate to 1. - Example: slewrate :{1,,8} - On Controller 0 set slew rate to 1. - On Controller 2 set slew rate to 8. - - Possible Values: 0 - 15 - Default Value: Varies based on chip revision - ----------------------------------------------------------------- - Option: amplitude: {value[,value...]} - Definition: Set IO Cell signal amplitude on a per-controller basis. - Controllers may be omitted indicating that - they should retain the default read streaming setting. - Example: amplitude:{0x1} - On Controller 0 set amplitude to 1. - Example: amplitude :{1,,7} - On Controller 0 set amplitude to 1. - On Controller 2 set amplitude to 7. - - Possible Values: 1 - 7 - Default Value: Varies based on chip revision - ----------------------------------------------------------------- - - Example: 'options aic79xx aic79xx=verbose,rd_strm:{{0x0041}}' - enables verbose output in the driver and turns read streaming on - for targets 0 and 6 of Controller 0. - -4. Additional Notes - - 4.1. Known/Unresolved or FYI Issues - - * Under SuSE Linux Enterprise 7, the driver may fail to operate - correctly due to a problem with PCI interrupt routing in the - Linux kernel. Please contact SuSE for an updated Linux - kernel. - - 4.2. Third-Party Compatibility Issues - - * Adaptec only supports Ultra320 hard drives running - the latest firmware available. Please check with - your hard drive manufacturer to ensure you have the - latest version. - - 4.3. Operating System or Technology Limitations - - * PCI Hot Plug is untested and may cause the operating system - to stop responding. - * Luns that are not numbered contiguously starting with 0 might not - be automatically probed during system startup. This is a limitation - of the OS. Please contact your Linux vendor for instructions on - manually probing non-contiguous luns. - * Using the Driver Update Disk version of this package during OS - installation under RedHat might result in two versions of this - driver being installed into the system module directory. This - might cause problems with the /sbin/mkinitrd program and/or - other RPM packages that try to install system modules. The best - way to correct this once the system is running is to install - the latest RPM package version of this driver, available from - http://www.adaptec.com. - - -5. Adaptec Customer Support - - A Technical Support Identification (TSID) Number is required for - Adaptec technical support. - - The 12-digit TSID can be found on the white barcode-type label - included inside the box with your product. The TSID helps us - provide more efficient service by accurately identifying your - product and support status. - - Support Options - - Search the Adaptec Support Knowledgebase (ASK) at - http://ask.adaptec.com for articles, troubleshooting tips, and - frequently asked questions about your product. - - For support via Email, submit your question to Adaptec's - Technical Support Specialists at http://ask.adaptec.com/. - - North America - - Visit our Web site at http://www.adaptec.com/. - - For information about Adaptec's support options, call - 408-957-2550, 24 hours a day, 7 days a week. - - To speak with a Technical Support Specialist, - * For hardware products, call 408-934-7274, - Monday to Friday, 3:00 am to 5:00 pm, PDT. - * For RAID and Fibre Channel products, call 321-207-2000, - Monday to Friday, 3:00 am to 5:00 pm, PDT. - To expedite your service, have your computer with you. - - To order Adaptec products, including accessories and cables, - call 408-957-7274. To order cables online go to - http://www.adaptec.com/buy-cables/. - - Europe - - Visit our Web site at http://www.adaptec.com/en-US/_common/world_index. - - To speak with a Technical Support Specialist, call, or email, - * German: +49 89 4366 5522, Monday-Friday, 9:00-17:00 CET, - http://ask-de.adaptec.com/. - * French: +49 89 4366 5533, Monday-Friday, 9:00-17:00 CET, - http://ask-fr.adaptec.com/. - * English: +49 89 4366 5544, Monday-Friday, 9:00-17:00 GMT, - http://ask.adaptec.com/. - - You can order Adaptec cables online at - http://www.adaptec.com/buy-cables/. - - Japan - - Visit our web site at http://www.adaptec.co.jp/. - - To speak with a Technical Support Specialist, call - +81 3 5308 6120, Monday-Friday, 9:00 a.m. to 12:00 p.m., - 1:00 p.m. to 6:00 p.m. - -------------------------------------------------------------------- -/* - * Copyright (c) 2003 Adaptec Inc. 691 S. Milpitas Blvd., Milpitas CA 95035 USA. - * All rights reserved. - * - * You are permitted to redistribute, use and modify this README file in whole - * or in part in conjunction with redistribution of software governed by the - * General Public License, provided that the following conditions are met: - * 1. Redistributions of README file must retain the above copyright - * notice, this list of conditions, and the following disclaimer, - * without modification. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * 3. Modifications or new contributions must be attributed in a copyright - * notice identifying the author ("Contributor") and added below the - * original copyright notice. The copyright notice is for purposes of - * identifying contributors and should not be deemed as permission to alter - * the permissions given by Adaptec. - * - * THIS README FILE IS PROVIDED BY ADAPTEC AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ANY - * WARRANTIES OF NON-INFRINGEMENT OR THE IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL - * ADAPTEC OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED - * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS README - * FILE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ diff --git a/Documentation/scsi/aic7xxx.rst b/Documentation/scsi/aic7xxx.rst new file mode 100644 index 000000000000..bad0e5567b21 --- /dev/null +++ b/Documentation/scsi/aic7xxx.rst @@ -0,0 +1,458 @@ +.. SPDX-License-Identifier: GPL-2.0 +.. include:: <isonum.txt> + +======================================================== +Adaptec Aic7xxx Fast -> Ultra160 Family Manager Set v7.0 +======================================================== + +README for The Linux Operating System + +The following information is available in this file: + + 1. Supported Hardware + 2. Version History + 3. Command Line Options + 4. Contacting Adaptec + +1. Supported Hardware +===================== + + The following Adaptec SCSI Chips and Host Adapters are supported by + the aic7xxx driver. + + ======== ===== ========= ======== ========= ===== =============== + Chip MIPS Host Bus MaxSync MaxWidth SCBs Notes + ======== ===== ========= ======== ========= ===== =============== + aic7770 10 EISA/VL 10MHz 16Bit 4 1 + aic7850 10 PCI/32 10MHz 8Bit 3 + aic7855 10 PCI/32 10MHz 8Bit 3 + aic7856 10 PCI/32 10MHz 8Bit 3 + aic7859 10 PCI/32 20MHz 8Bit 3 + aic7860 10 PCI/32 20MHz 8Bit 3 + aic7870 10 PCI/32 10MHz 16Bit 16 + aic7880 10 PCI/32 20MHz 16Bit 16 + aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8 + aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8 + aic7892 20 PCI/64-66 80MHz 16Bit 16 3 4 5 6 7 8 + aic7895 15 PCI/32 20MHz 16Bit 16 2 3 4 5 + aic7895C 15 PCI/32 20MHz 16Bit 16 2 3 4 5 8 + aic7896 20 PCI/32 40MHz 16Bit 16 2 3 4 5 6 7 8 + aic7897 20 PCI/64 40MHz 16Bit 16 2 3 4 5 6 7 8 + aic7899 20 PCI/64-66 80MHz 16Bit 16 2 3 4 5 6 7 8 + ======== ===== ========= ======== ========= ===== =============== + + 1. Multiplexed Twin Channel Device - One controller servicing two + busses. + 2. Multi-function Twin Channel Device - Two controllers on one chip. + 3. Command Channel Secondary DMA Engine - Allows scatter gather list + and SCB prefetch. + 4. 64 Byte SCB Support - Allows disconnected, untagged request table + for all possible target/lun combinations. + 5. Block Move Instruction Support - Doubles the speed of certain + sequencer operations. + 6. 'Bayonet' style Scatter Gather Engine - Improves S/G prefetch + performance. + 7. Queuing Registers - Allows queuing of new transactions without + pausing the sequencer. + 8. Multiple Target IDs - Allows the controller to respond to selection + as a target on multiple SCSI IDs. + + ============== ======= =========== =============== =============== ========= + Controller Chip Host-Bus Int-Connectors Ext-Connectors Notes + ============== ======= =========== =============== =============== ========= + AHA-274X[A] aic7770 EISA SE-50M SE-HD50F + AHA-274X[A]W aic7770 EISA SE-HD68F SE-HD68F + SE-50M + AHA-274X[A]T aic7770 EISA 2 X SE-50M SE-HD50F + AHA-2842 aic7770 VL SE-50M SE-HD50F + AHA-2940AU aic7860 PCI/32 SE-50M SE-HD50F + AVA-2902I aic7860 PCI/32 SE-50M + AVA-2902E aic7860 PCI/32 SE-50M + AVA-2906 aic7856 PCI/32 SE-50M SE-DB25F + APC-7850 aic7850 PCI/32 SE-50M 1 + AVA-2940 aic7860 PCI/32 SE-50M + AHA-2920B aic7860 PCI/32 SE-50M + AHA-2930B aic7860 PCI/32 SE-50M + AHA-2920C aic7856 PCI/32 SE-50M SE-HD50F + AHA-2930C aic7860 PCI/32 SE-50M + AHA-2930C aic7860 PCI/32 SE-50M + AHA-2910C aic7860 PCI/32 SE-50M + AHA-2915C aic7860 PCI/32 SE-50M + AHA-2940AU/CN aic7860 PCI/32 SE-50M SE-HD50F + AHA-2944W aic7870 PCI/32 HVD-HD68F HVD-HD68F + HVD-50M + AHA-3940W aic7870 PCI/32 2 X SE-HD68F SE-HD68F 2 + AHA-2940UW aic7880 PCI/32 SE-HD68F + SE-50M SE-HD68F + AHA-2940U aic7880 PCI/32 SE-50M SE-HD50F + AHA-2940D aic7880 PCI/32 + aHA-2940 A/T aic7880 PCI/32 + AHA-2940D A/T aic7880 PCI/32 + AHA-3940UW aic7880 PCI/32 2 X SE-HD68F SE-HD68F 3 + AHA-3940UWD aic7880 PCI/32 2 X SE-HD68F 2 X SE-VHD68F 3 + AHA-3940U aic7880 PCI/32 2 X SE-50M SE-HD50F 3 + AHA-2944UW aic7880 PCI/32 HVD-HD68F HVD-HD68F + HVD-50M + AHA-3944UWD aic7880 PCI/32 2 X HVD-HD68F 2 X HVD-VHD68F 3 + AHA-4944UW aic7880 PCI/32 + AHA-2930UW aic7880 PCI/32 + AHA-2940UW Pro aic7880 PCI/32 SE-HD68F SE-HD68F 4 + SE-50M + AHA-2940UW/CN aic7880 PCI/32 + AHA-2940UDual aic7895 PCI/32 + AHA-2940UWDual aic7895 PCI/32 + AHA-3940UWD aic7895 PCI/32 + AHA-3940AUW aic7895 PCI/32 + AHA-3940AUWD aic7895 PCI/32 + AHA-3940AU aic7895 PCI/32 + AHA-3944AUWD aic7895 PCI/32 2 X HVD-HD68F 2 X HVD-VHD68F + AHA-2940U2B aic7890 PCI/32 LVD-HD68F LVD-HD68F + AHA-2940U2 OEM aic7891 PCI/64 + AHA-2940U2W aic7890 PCI/32 LVD-HD68F LVD-HD68F + SE-HD68F + SE-50M + AHA-2950U2B aic7891 PCI/64 LVD-HD68F LVD-HD68F + AHA-2930U2 aic7890 PCI/32 LVD-HD68F SE-HD50F + SE-50M + AHA-3950U2B aic7897 PCI/64 + AHA-3950U2D aic7897 PCI/64 + AHA-29160 aic7892 PCI/64-66 + AHA-29160 CPQ aic7892 PCI/64-66 + AHA-29160N aic7892 PCI/32 LVD-HD68F SE-HD50F + SE-50M + AHA-29160LP aic7892 PCI/64-66 + AHA-19160 aic7892 PCI/64-66 + AHA-29150LP aic7892 PCI/64-66 + AHA-29130LP aic7892 PCI/64-66 + AHA-3960D aic7899 PCI/64-66 2 X LVD-HD68F 2 X LVD-VHD68F + LVD-50M + AHA-3960D CPQ aic7899 PCI/64-66 2 X LVD-HD68F 2 X LVD-VHD68F + LVD-50M + AHA-39160 aic7899 PCI/64-66 2 X LVD-HD68F 2 X LVD-VHD68F + LVD-50M + ============== ======= =========== =============== =============== ========= + + 1. No BIOS support + 2. DEC21050 PCI-PCI bridge with multiple controller chips on secondary bus + 3. DEC2115X PCI-PCI bridge with multiple controller chips on secondary bus + 4. All three SCSI connectors may be used simultaneously without + SCSI "stub" effects. + +2. Version History +================== + + * 7.0 (4th August, 2005) + - Updated driver to use SCSI transport class infrastructure + - Upported sequencer and core fixes from last adaptec released + version of the driver. + + * 6.2.36 (June 3rd, 2003) + - Correct code that disables PCI parity error checking. + - Correct and simplify handling of the ignore wide residue + message. The previous code would fail to report a residual + if the transaction data length was even and we received + an IWR message. + - Add support for the 2.5.X EISA framework. + - Update for change in 2.5.X SCSI proc FS interface. + - Correct Domain Validation command-line option parsing. + - When negotiation async via an 8bit WDTR message, send + an SDTR with an offset of 0 to be sure the target + knows we are async. This works around a firmware defect + in the Quantum Atlas 10K. + - Clear PCI error state during driver attach so that we + don't disable memory mapped I/O due to a stray write + by some other driver probe that occurred before we + claimed the controller. + + * 6.2.35 (May 14th, 2003) + - Fix a few GCC 3.3 compiler warnings. + - Correct operation on EISA Twin Channel controller. + - Add support for 2.5.X's scsi_report_device_reset(). + + * 6.2.34 (May 5th, 2003) + - Fix locking regression introduced in 6.2.29 that + could cause a lock order reversal between the io_request_lock + and our per-softc lock. This was only possible on RH9, + SuSE, and kernel.org 2.4.X kernels. + + * 6.2.33 (April 30th, 2003) + - Dynamically disable PCI parity error reporting after + 10 errors are reported to the user. These errors are + the result of some other device issuing PCI transactions + with bad parity. Once the user has been informed of the + problem, continuing to report the errors just degrades + our performance. + + * 6.2.32 (March 28th, 2003) + - Dynamically sized S/G lists to avoid SCSI malloc + pool fragmentation and SCSI mid-layer deadlock. + + * 6.2.28 (January 20th, 2003) + - Domain Validation Fixes + - Add ability to disable PCI parity error checking. + - Enhanced Memory Mapped I/O probe + + * 6.2.20 (November 7th, 2002) + - Added Domain Validation. + +3. Command Line Options +======================= + + + .. Warning:: + + ALTERING OR ADDING THESE DRIVER PARAMETERS + INCORRECTLY CAN RENDER YOUR SYSTEM INOPERABLE. + USE THEM WITH CAUTION. + + Put a .conf file in the /etc/modprobe.d directory and add/edit a + line containing ``options aic7xxx aic7xxx=[command[,command...]]`` where + ``command`` is one or more of the following: + +verbose + + :Definition: enable additional informative messages during driver operation. + :Possible Values: This option is a flag + :Default Value: disabled + + +debug:[value] + + :Definition: Enables various levels of debugging information + :Possible Values: 0x0000 = no debugging, 0xffff = full debugging + :Default Value: 0x0000 + +no_probe + +probe_eisa_vl + + :Definition: Do not probe for EISA/VLB controllers. + This is a toggle. If the driver is compiled + to not probe EISA/VLB controllers by default, + specifying "no_probe" will enable this probing. + If the driver is compiled to probe EISA/VLB + controllers by default, specifying "no_probe" + will disable this probing. + + :Possible Values: This option is a toggle + :Default Value: EISA/VLB probing is disabled by default. + +pci_parity + + :Definition: Toggles the detection of PCI parity errors. + On many motherboards with VIA chipsets, + PCI parity is not generated correctly on the + PCI bus. It is impossible for the hardware to + differentiate between these "spurious" parity + errors and real parity errors. The symptom of + this problem is a stream of the message:: + + "scsi0: Data Parity Error Detected during address or write data phase" + + output by the driver. + + :Possible Values: This option is a toggle + :Default Value: PCI Parity Error reporting is disabled + +no_reset + + :Definition: Do not reset the bus during the initial probe + phase + + :Possible Values: This option is a flag + :Default Value: disabled + +extended + + :Definition: Force extended translation on the controller + :Possible Values: This option is a flag + :Default Value: disabled + +periodic_otag + + :Definition: Send an ordered tag periodically to prevent + tag starvation. Needed for some older devices + + :Possible Values: This option is a flag + :Default Value: disabled + +reverse_scan + + :Definition: Probe the scsi bus in reverse order, starting + with target 15 + + :Possible Values: This option is a flag + :Default Value: disabled + +global_tag_depth:[value] + + :Definition: Global tag depth for all targets on all busses. + This option sets the default tag depth which + may be selectively overridden vi the tag_info + option. + + :Possible Values: 1 - 253 + :Default Value: 32 + +tag_info:{{value[,value...]}[,{value[,value...]}...]} + + :Definition: Set the per-target tagged queue depth on a + per controller basis. Both controllers and targets + may be omitted indicating that they should retain + the default tag depth. + + :Possible Values: 1 - 253 + :Default Value: 32 + + Examples: + + :: + + tag_info:{{16,32,32,64,8,8,,32,32,32,32,32,32,32,32,32} + + On Controller 0: + + - specifies a tag depth of 16 for target 0 + - specifies a tag depth of 64 for target 3 + - specifies a tag depth of 8 for targets 4 and 5 + - leaves target 6 at the default + - specifies a tag depth of 32 for targets 1,2,7-15 + - All other targets retain the default depth. + + :: + + tag_info:{{},{32,,32}} + + On Controller 1: + + - specifies a tag depth of 32 for targets 0 and 2 + - All other targets retain the default depth. + +seltime:[value] + + :Definition: Specifies the selection timeout value + :Possible Values: 0 = 256ms, 1 = 128ms, 2 = 64ms, 3 = 32ms + :Default Value: 0 + +dv: {value[,value...]} + + :Definition: Set Domain Validation Policy on a per-controller basis. + Controllers may be omitted indicating that + they should retain the default read streaming setting. + + :Possible Values: + + ==== =============================== + < 0 Use setting from serial EEPROM. + 0 Disable DV + > 0 Enable DV + ==== =============================== + + + :Default Value: SCSI-Select setting on controllers with a SCSI Select + option for DV. Otherwise, on for controllers supporting + U160 speeds and off for all other controller types. + + Example: + + :: + + dv:{-1,0,,1,1,0} + + - On Controller 0 leave DV at its default setting. + - On Controller 1 disable DV. + - Skip configuration on Controller 2. + - On Controllers 3 and 4 enable DV. + - On Controller 5 disable DV. + +Example:: + + options aic7xxx aic7xxx=verbose,no_probe,tag_info:{{},{,,10}},seltime:1 + +enables verbose logging, Disable EISA/VLB probing, +and set tag depth on Controller 1/Target 2 to 10 tags. + +4. Adaptec Customer Support +=========================== + + A Technical Support Identification (TSID) Number is required for + Adaptec technical support. + + - The 12-digit TSID can be found on the white barcode-type label + included inside the box with your product. The TSID helps us + provide more efficient service by accurately identifying your + product and support status. + + Support Options + - Search the Adaptec Support Knowledgebase (ASK) at + http://ask.adaptec.com for articles, troubleshooting tips, and + frequently asked questions about your product. + - For support via Email, submit your question to Adaptec's + Technical Support Specialists at http://ask.adaptec.com/. + + North America + - Visit our Web site at http://www.adaptec.com/. + - For information about Adaptec's support options, call + 408-957-2550, 24 hours a day, 7 days a week. + - To speak with a Technical Support Specialist, + + * For hardware products, call 408-934-7274, + Monday to Friday, 3:00 am to 5:00 pm, PDT. + * For RAID and Fibre Channel products, call 321-207-2000, + Monday to Friday, 3:00 am to 5:00 pm, PDT. + + To expedite your service, have your computer with you. + - To order Adaptec products, including accessories and cables, + call 408-957-7274. To order cables online go to + http://www.adaptec.com/buy-cables/. + + Europe + - Visit our Web site at http://www.adaptec.com/en-US/_common/world_index. + - To speak with a Technical Support Specialist, call, or email, + + * German: +49 89 4366 5522, Monday-Friday, 9:00-17:00 CET, + http://ask-de.adaptec.com/. + * French: +49 89 4366 5533, Monday-Friday, 9:00-17:00 CET, + http://ask-fr.adaptec.com/. + * English: +49 89 4366 5544, Monday-Friday, 9:00-17:00 GMT, + http://ask.adaptec.com/. + + - You can order Adaptec cables online at + http://www.adaptec.com/buy-cables/. + + Japan + - Visit our web site at http://www.adaptec.co.jp/. + - To speak with a Technical Support Specialist, call + +81 3 5308 6120, Monday-Friday, 9:00 a.m. to 12:00 p.m., + 1:00 p.m. to 6:00 p.m. + +Copyright |copy| 2003 Adaptec Inc. 691 S. Milpitas Blvd., Milpitas CA 95035 USA. + +All rights reserved. + +You are permitted to redistribute, use and modify this README file in whole +or in part in conjunction with redistribution of software governed by the +General Public License, provided that the following conditions are met: + +1. Redistributions of README file must retain the above copyright + notice, this list of conditions, and the following disclaimer, + without modification. +2. The name of the author may not be used to endorse or promote products + derived from this software without specific prior written permission. +3. Modifications or new contributions must be attributed in a copyright + notice identifying the author ("Contributor") and added below the + original copyright notice. The copyright notice is for purposes of + identifying contributors and should not be deemed as permission to alter + the permissions given by Adaptec. + +THIS README FILE IS PROVIDED BY ADAPTEC AND CONTRIBUTORS ``AS IS`` AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ANY +WARRANTIES OF NON-INFRINGEMENT OR THE IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +ADAPTEC OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS README +FILE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/Documentation/scsi/aic7xxx.txt b/Documentation/scsi/aic7xxx.txt deleted file mode 100644 index 7c5d0223d444..000000000000 --- a/Documentation/scsi/aic7xxx.txt +++ /dev/null @@ -1,394 +0,0 @@ -==================================================================== -= Adaptec Aic7xxx Fast -> Ultra160 Family Manager Set v7.0 = -= README for = -= The Linux Operating System = -==================================================================== - -The following information is available in this file: - - 1. Supported Hardware - 2. Version History - 3. Command Line Options - 4. Contacting Adaptec - -1. Supported Hardware - - The following Adaptec SCSI Chips and Host Adapters are supported by - the aic7xxx driver. - - Chip MIPS Host Bus MaxSync MaxWidth SCBs Notes - --------------------------------------------------------------- - aic7770 10 EISA/VL 10MHz 16Bit 4 1 - aic7850 10 PCI/32 10MHz 8Bit 3 - aic7855 10 PCI/32 10MHz 8Bit 3 - aic7856 10 PCI/32 10MHz 8Bit 3 - aic7859 10 PCI/32 20MHz 8Bit 3 - aic7860 10 PCI/32 20MHz 8Bit 3 - aic7870 10 PCI/32 10MHz 16Bit 16 - aic7880 10 PCI/32 20MHz 16Bit 16 - aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8 - aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8 - aic7892 20 PCI/64-66 80MHz 16Bit 16 3 4 5 6 7 8 - aic7895 15 PCI/32 20MHz 16Bit 16 2 3 4 5 - aic7895C 15 PCI/32 20MHz 16Bit 16 2 3 4 5 8 - aic7896 20 PCI/32 40MHz 16Bit 16 2 3 4 5 6 7 8 - aic7897 20 PCI/64 40MHz 16Bit 16 2 3 4 5 6 7 8 - aic7899 20 PCI/64-66 80MHz 16Bit 16 2 3 4 5 6 7 8 - - 1. Multiplexed Twin Channel Device - One controller servicing two - busses. - 2. Multi-function Twin Channel Device - Two controllers on one chip. - 3. Command Channel Secondary DMA Engine - Allows scatter gather list - and SCB prefetch. - 4. 64 Byte SCB Support - Allows disconnected, untagged request table - for all possible target/lun combinations. - 5. Block Move Instruction Support - Doubles the speed of certain - sequencer operations. - 6. `Bayonet' style Scatter Gather Engine - Improves S/G prefetch - performance. - 7. Queuing Registers - Allows queuing of new transactions without - pausing the sequencer. - 8. Multiple Target IDs - Allows the controller to respond to selection - as a target on multiple SCSI IDs. - - Controller Chip Host-Bus Int-Connectors Ext-Connectors Notes - -------------------------------------------------------------------------- - AHA-274X[A] aic7770 EISA SE-50M SE-HD50F - AHA-274X[A]W aic7770 EISA SE-HD68F SE-HD68F - SE-50M - AHA-274X[A]T aic7770 EISA 2 X SE-50M SE-HD50F - AHA-2842 aic7770 VL SE-50M SE-HD50F - AHA-2940AU aic7860 PCI/32 SE-50M SE-HD50F - AVA-2902I aic7860 PCI/32 SE-50M - AVA-2902E aic7860 PCI/32 SE-50M - AVA-2906 aic7856 PCI/32 SE-50M SE-DB25F - APC-7850 aic7850 PCI/32 SE-50M 1 - AVA-2940 aic7860 PCI/32 SE-50M - AHA-2920B aic7860 PCI/32 SE-50M - AHA-2930B aic7860 PCI/32 SE-50M - AHA-2920C aic7856 PCI/32 SE-50M SE-HD50F - AHA-2930C aic7860 PCI/32 SE-50M - AHA-2930C aic7860 PCI/32 SE-50M - AHA-2910C aic7860 PCI/32 SE-50M - AHA-2915C aic7860 PCI/32 SE-50M - AHA-2940AU/CN aic7860 PCI/32 SE-50M SE-HD50F - AHA-2944W aic7870 PCI/32 HVD-HD68F HVD-HD68F - HVD-50M - AHA-3940W aic7870 PCI/32 2 X SE-HD68F SE-HD68F 2 - AHA-2940UW aic7880 PCI/32 SE-HD68F - SE-50M SE-HD68F - AHA-2940U aic7880 PCI/32 SE-50M SE-HD50F - AHA-2940D aic7880 PCI/32 - aHA-2940 A/T aic7880 PCI/32 - AHA-2940D A/T aic7880 PCI/32 - AHA-3940UW aic7880 PCI/32 2 X SE-HD68F SE-HD68F 3 - AHA-3940UWD aic7880 PCI/32 2 X SE-HD68F 2 X SE-VHD68F 3 - AHA-3940U aic7880 PCI/32 2 X SE-50M SE-HD50F 3 - AHA-2944UW aic7880 PCI/32 HVD-HD68F HVD-HD68F - HVD-50M - AHA-3944UWD aic7880 PCI/32 2 X HVD-HD68F 2 X HVD-VHD68F 3 - AHA-4944UW aic7880 PCI/32 - AHA-2930UW aic7880 PCI/32 - AHA-2940UW Pro aic7880 PCI/32 SE-HD68F SE-HD68F 4 - SE-50M - AHA-2940UW/CN aic7880 PCI/32 - AHA-2940UDual aic7895 PCI/32 - AHA-2940UWDual aic7895 PCI/32 - AHA-3940UWD aic7895 PCI/32 - AHA-3940AUW aic7895 PCI/32 - AHA-3940AUWD aic7895 PCI/32 - AHA-3940AU aic7895 PCI/32 - AHA-3944AUWD aic7895 PCI/32 2 X HVD-HD68F 2 X HVD-VHD68F - AHA-2940U2B aic7890 PCI/32 LVD-HD68F LVD-HD68F - AHA-2940U2 OEM aic7891 PCI/64 - AHA-2940U2W aic7890 PCI/32 LVD-HD68F LVD-HD68F - SE-HD68F - SE-50M - AHA-2950U2B aic7891 PCI/64 LVD-HD68F LVD-HD68F - AHA-2930U2 aic7890 PCI/32 LVD-HD68F SE-HD50F - SE-50M - AHA-3950U2B aic7897 PCI/64 - AHA-3950U2D aic7897 PCI/64 - AHA-29160 aic7892 PCI/64-66 - AHA-29160 CPQ aic7892 PCI/64-66 - AHA-29160N aic7892 PCI/32 LVD-HD68F SE-HD50F - SE-50M - AHA-29160LP aic7892 PCI/64-66 - AHA-19160 aic7892 PCI/64-66 - AHA-29150LP aic7892 PCI/64-66 - AHA-29130LP aic7892 PCI/64-66 - AHA-3960D aic7899 PCI/64-66 2 X LVD-HD68F 2 X LVD-VHD68F - LVD-50M - AHA-3960D CPQ aic7899 PCI/64-66 2 X LVD-HD68F 2 X LVD-VHD68F - LVD-50M - AHA-39160 aic7899 PCI/64-66 2 X LVD-HD68F 2 X LVD-VHD68F - LVD-50M - - 1. No BIOS support - 2. DEC21050 PCI-PCI bridge with multiple controller chips on secondary bus - 3. DEC2115X PCI-PCI bridge with multiple controller chips on secondary bus - 4. All three SCSI connectors may be used simultaneously without - SCSI "stub" effects. - -2. Version History - 7.0 (4th August, 2005) - - Updated driver to use SCSI transport class infrastructure - - Upported sequencer and core fixes from last adaptec released - version of the driver. - 6.2.36 (June 3rd, 2003) - - Correct code that disables PCI parity error checking. - - Correct and simplify handling of the ignore wide residue - message. The previous code would fail to report a residual - if the transaction data length was even and we received - an IWR message. - - Add support for the 2.5.X EISA framework. - - Update for change in 2.5.X SCSI proc FS interface. - - Correct Domain Validation command-line option parsing. - - When negotiation async via an 8bit WDTR message, send - an SDTR with an offset of 0 to be sure the target - knows we are async. This works around a firmware defect - in the Quantum Atlas 10K. - - Clear PCI error state during driver attach so that we - don't disable memory mapped I/O due to a stray write - by some other driver probe that occurred before we - claimed the controller. - - 6.2.35 (May 14th, 2003) - - Fix a few GCC 3.3 compiler warnings. - - Correct operation on EISA Twin Channel controller. - - Add support for 2.5.X's scsi_report_device_reset(). - - 6.2.34 (May 5th, 2003) - - Fix locking regression introduced in 6.2.29 that - could cause a lock order reversal between the io_request_lock - and our per-softc lock. This was only possible on RH9, - SuSE, and kernel.org 2.4.X kernels. - - 6.2.33 (April 30th, 2003) - - Dynamically disable PCI parity error reporting after - 10 errors are reported to the user. These errors are - the result of some other device issuing PCI transactions - with bad parity. Once the user has been informed of the - problem, continuing to report the errors just degrades - our performance. - - 6.2.32 (March 28th, 2003) - - Dynamically sized S/G lists to avoid SCSI malloc - pool fragmentation and SCSI mid-layer deadlock. - - 6.2.28 (January 20th, 2003) - - Domain Validation Fixes - - Add ability to disable PCI parity error checking. - - Enhanced Memory Mapped I/O probe - - 6.2.20 (November 7th, 2002) - - Added Domain Validation. - -3. Command Line Options - - WARNING: ALTERING OR ADDING THESE DRIVER PARAMETERS - INCORRECTLY CAN RENDER YOUR SYSTEM INOPERABLE. - USE THEM WITH CAUTION. - - Put a .conf file in the /etc/modprobe.d directory and add/edit a - line containing 'options aic7xxx aic7xxx=[command[,command...]]' where - 'command' is one or more of the following: - ----------------------------------------------------------------- - Option: verbose - Definition: enable additional informative messages during - driver operation. - Possible Values: This option is a flag - Default Value: disabled - ----------------------------------------------------------------- - Option: debug:[value] - Definition: Enables various levels of debugging information - Possible Values: 0x0000 = no debugging, 0xffff = full debugging - Default Value: 0x0000 - ----------------------------------------------------------------- - Option: no_probe - Option: probe_eisa_vl - Definition: Do not probe for EISA/VLB controllers. - This is a toggle. If the driver is compiled - to not probe EISA/VLB controllers by default, - specifying "no_probe" will enable this probing. - If the driver is compiled to probe EISA/VLB - controllers by default, specifying "no_probe" - will disable this probing. - Possible Values: This option is a toggle - Default Value: EISA/VLB probing is disabled by default. - ----------------------------------------------------------------- - Option: pci_parity - Definition: Toggles the detection of PCI parity errors. - On many motherboards with VIA chipsets, - PCI parity is not generated correctly on the - PCI bus. It is impossible for the hardware to - differentiate between these "spurious" parity - errors and real parity errors. The symptom of - this problem is a stream of the message: - "scsi0: Data Parity Error Detected during address or write data phase" - output by the driver. - Possible Values: This option is a toggle - Default Value: PCI Parity Error reporting is disabled - ----------------------------------------------------------------- - Option: no_reset - Definition: Do not reset the bus during the initial probe - phase - Possible Values: This option is a flag - Default Value: disabled - ----------------------------------------------------------------- - Option: extended - Definition: Force extended translation on the controller - Possible Values: This option is a flag - Default Value: disabled - ----------------------------------------------------------------- - Option: periodic_otag - Definition: Send an ordered tag periodically to prevent - tag starvation. Needed for some older devices - Possible Values: This option is a flag - Default Value: disabled - ----------------------------------------------------------------- - Option: reverse_scan - Definition: Probe the scsi bus in reverse order, starting - with target 15 - Possible Values: This option is a flag - Default Value: disabled - ----------------------------------------------------------------- - Option: global_tag_depth:[value] - Definition: Global tag depth for all targets on all busses. - This option sets the default tag depth which - may be selectively overridden vi the tag_info - option. - Possible Values: 1 - 253 - Default Value: 32 - ----------------------------------------------------------------- - Option: tag_info:{{value[,value...]}[,{value[,value...]}...]} - Definition: Set the per-target tagged queue depth on a - per controller basis. Both controllers and targets - may be omitted indicating that they should retain - the default tag depth. - Examples: tag_info:{{16,32,32,64,8,8,,32,32,32,32,32,32,32,32,32} - On Controller 0 - specifies a tag depth of 16 for target 0 - specifies a tag depth of 64 for target 3 - specifies a tag depth of 8 for targets 4 and 5 - leaves target 6 at the default - specifies a tag depth of 32 for targets 1,2,7-15 - All other targets retain the default depth. - - tag_info:{{},{32,,32}} - On Controller 1 - specifies a tag depth of 32 for targets 0 and 2 - All other targets retain the default depth. - - Possible Values: 1 - 253 - Default Value: 32 - ----------------------------------------------------------------- - Option: seltime:[value] - Definition: Specifies the selection timeout value - Possible Values: 0 = 256ms, 1 = 128ms, 2 = 64ms, 3 = 32ms - Default Value: 0 - ----------------------------------------------------------------- - Option: dv: {value[,value...]} - Definition: Set Domain Validation Policy on a per-controller basis. - Controllers may be omitted indicating that - they should retain the default read streaming setting. - Example: dv:{-1,0,,1,1,0} - On Controller 0 leave DV at its default setting. - On Controller 1 disable DV. - Skip configuration on Controller 2. - On Controllers 3 and 4 enable DV. - On Controller 5 disable DV. - - Possible Values: < 0 Use setting from serial EEPROM. - 0 Disable DV - > 0 Enable DV - - Default Value: SCSI-Select setting on controllers with a SCSI Select - option for DV. Otherwise, on for controllers supporting - U160 speeds and off for all other controller types. - ----------------------------------------------------------------- - - Example: - 'options aic7xxx aic7xxx=verbose,no_probe,tag_info:{{},{,,10}},seltime:1' - enables verbose logging, Disable EISA/VLB probing, - and set tag depth on Controller 1/Target 2 to 10 tags. - -4. Adaptec Customer Support - - A Technical Support Identification (TSID) Number is required for - Adaptec technical support. - - The 12-digit TSID can be found on the white barcode-type label - included inside the box with your product. The TSID helps us - provide more efficient service by accurately identifying your - product and support status. - - Support Options - - Search the Adaptec Support Knowledgebase (ASK) at - http://ask.adaptec.com for articles, troubleshooting tips, and - frequently asked questions about your product. - - For support via Email, submit your question to Adaptec's - Technical Support Specialists at http://ask.adaptec.com/. - - North America - - Visit our Web site at http://www.adaptec.com/. - - For information about Adaptec's support options, call - 408-957-2550, 24 hours a day, 7 days a week. - - To speak with a Technical Support Specialist, - * For hardware products, call 408-934-7274, - Monday to Friday, 3:00 am to 5:00 pm, PDT. - * For RAID and Fibre Channel products, call 321-207-2000, - Monday to Friday, 3:00 am to 5:00 pm, PDT. - To expedite your service, have your computer with you. - - To order Adaptec products, including accessories and cables, - call 408-957-7274. To order cables online go to - http://www.adaptec.com/buy-cables/. - - Europe - - Visit our Web site at http://www.adaptec.com/en-US/_common/world_index. - - To speak with a Technical Support Specialist, call, or email, - * German: +49 89 4366 5522, Monday-Friday, 9:00-17:00 CET, - http://ask-de.adaptec.com/. - * French: +49 89 4366 5533, Monday-Friday, 9:00-17:00 CET, - http://ask-fr.adaptec.com/. - * English: +49 89 4366 5544, Monday-Friday, 9:00-17:00 GMT, - http://ask.adaptec.com/. - - You can order Adaptec cables online at - http://www.adaptec.com/buy-cables/. - - Japan - - Visit our web site at http://www.adaptec.co.jp/. - - To speak with a Technical Support Specialist, call - +81 3 5308 6120, Monday-Friday, 9:00 a.m. to 12:00 p.m., - 1:00 p.m. to 6:00 p.m. - -------------------------------------------------------------------- -/* - * Copyright (c) 2003 Adaptec Inc. 691 S. Milpitas Blvd., Milpitas CA 95035 USA. - * All rights reserved. - * - * You are permitted to redistribute, use and modify this README file in whole - * or in part in conjunction with redistribution of software governed by the - * General Public License, provided that the following conditions are met: - * 1. Redistributions of README file must retain the above copyright - * notice, this list of conditions, and the following disclaimer, - * without modification. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * 3. Modifications or new contributions must be attributed in a copyright - * notice identifying the author ("Contributor") and added below the - * original copyright notice. The copyright notice is for purposes of - * identifying contributors and should not be deemed as permission to alter - * the permissions given by Adaptec. - * - * THIS README FILE IS PROVIDED BY ADAPTEC AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ANY - * WARRANTIES OF NON-INFRINGEMENT OR THE IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL - * ADAPTEC OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED - * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS README - * FILE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ diff --git a/Documentation/scsi/arcmsr_spec.rst b/Documentation/scsi/arcmsr_spec.rst new file mode 100644 index 000000000000..83dd53bcff78 --- /dev/null +++ b/Documentation/scsi/arcmsr_spec.rst @@ -0,0 +1,907 @@ +ARECA FIRMWARE SPEC +=================== + +Usage of IOP331 adapter +======================= + +(All In/Out is in IOP331's view) + +1. Message 0 +------------ + +- InitThread message and return code + +2. Doorbell is used for RS-232 emulation +---------------------------------------- + +inDoorBell + bit0 + data in ready + zDRIVER DATA WRITE OK) + bit1 + data out has been read + (DRIVER DATA READ OK) + +outDooeBell: + bit0 + data out ready + (IOP331 DATA WRITE OK) + bit1 + data in has been read + (IOP331 DATA READ OK) + +3. Index Memory Usage +--------------------- + +============ ========================================== +offset 0xf00 for RS232 out (request buffer) +offset 0xe00 for RS232 in (scratch buffer) +offset 0xa00 for inbound message code message_rwbuffer + (driver send to IOP331) +offset 0xa00 for outbound message code message_rwbuffer + (IOP331 send to driver) +============ ========================================== + +4. RS-232 emulation +------------------- + +Currently 128 byte buffer is used: + +============ ===================== +1st uint32_t Data length (1--124) +Byte 4--127 Max 124 bytes of data +============ ===================== + +5. PostQ +-------- + +All SCSI Command must be sent through postQ: + + (inbound queue port) + Request frame must be 32 bytes aligned: + + #bit27--bit31 + flag for post ccb + #bit0--bit26 + real address (bit27--bit31) of post arcmsr_cdb + + ===== =================== + bit31 == =============== + 0 256 bytes frame + 1 512 bytes frame + == =============== + bit30 == ============== + 0 normal request + 1 BIOS request + == ============== + bit29 reserved + bit28 reserved + bit27 reserved + ===== =================== + + (outbount queue port) + Request reply: + + #bit27--bit31 + flag for reply + #bit0--bit26 + real address (bit27--bit31) of reply arcmsr_cdb + + ===== ======================================================= + bit31 must be 0 (for this type of reply) + bit30 reserved for BIOS handshake + bit29 reserved + bit28 == =================================================== + 0 no error, ignore AdapStatus/DevStatus/SenseData + 1 Error, error code in AdapStatus/DevStatus/SenseData + == =================================================== + bit27 reserved + ===== ======================================================= + +6. BIOS request +--------------- + +All BIOS request is the same with request from PostQ + +Except: + +Request frame is sent from configuration space: + + ============ ========================== + offset: 0x78 Request Frame (bit30 == 1) + offset: 0x18 writeonly to generate + IRQ to IOP331 + ============ ========================== + +Completion of request:: + + (bit30 == 0, bit28==err flag) + +7. Definition of SGL entry (structure) +-------------------------------------- + +8. Message1 Out - Diag Status Code (????) +----------------------------------------- + +9. Message0 message code +------------------------ + +====== ================================================================= +0x00 NOP +0x01 Get Config + ->offset 0xa00 :for outbound message code message_rwbuffer + (IOP331 send to driver) + + ===================== ========================================== + Signature 0x87974060(4) + Request len 0x00000200(4) + numbers of queue 0x00000100(4) + SDRAM Size 0x00000100(4)-->256 MB + IDE Channels 0x00000008(4) + vendor 40 bytes char + model 8 bytes char + FirmVer 16 bytes char + Device Map 16 bytes char + FirmwareVersion DWORD + + - Added for checking of + new firmware capability + ===================== ========================================== +0x02 Set Config + ->offset 0xa00 :for inbound message code message_rwbuffer + (driver send to IOP331) + + ========================= ================== + Signature 0x87974063(4) + UPPER32 of Request Frame (4)-->Driver Only + ========================= ================== +0x03 Reset (Abort all queued Command) +0x04 Stop Background Activity +0x05 Flush Cache +0x06 Start Background Activity + (re-start if background is halted) +0x07 Check If Host Command Pending + (Novell May Need This Function) +0x08 Set controller time + ->offset 0xa00 for inbound message code message_rwbuffer + (driver to IOP331) + + ====== ================== + byte 0 0xaa <-- signature + byte 1 0x55 <-- signature + byte 2 year (04) + byte 3 month (1..12) + byte 4 date (1..31) + byte 5 hour (0..23) + byte 6 minute (0..59) + byte 7 second (0..59) + ====== ================== +====== ================================================================= + + +RS-232 Interface for Areca Raid Controller +========================================== + + The low level command interface is exclusive with VT100 terminal + +1. Sequence of command execution +-------------------------------- + + (A) Header + 3 bytes sequence (0x5E, 0x01, 0x61) + + (B) Command block + variable length of data including length, + command code, data and checksum byte + + (C) Return data + variable length of data + +2. Command block +---------------- + + (A) 1st byte + command block length (low byte) + + (B) 2nd byte + command block length (high byte) + + .. Note:: command block length shouldn't > 2040 bytes, + length excludes these two bytes + + (C) 3rd byte + command code + + (D) 4th and following bytes + variable length data bytes + + depends on command code + + (E) last byte + checksum byte (sum of 1st byte until last data byte) + +3. Command code and associated data +----------------------------------- + +The following are command code defined in raid controller Command +code 0x10--0x1? are used for system level management, +no password checking is needed and should be implemented in separate +well controlled utility and not for end user access. +Command code 0x20--0x?? always check the password, +password must be entered to enable these command:: + + enum + { + GUI_SET_SERIAL=0x10, + GUI_SET_VENDOR, + GUI_SET_MODEL, + GUI_IDENTIFY, + GUI_CHECK_PASSWORD, + GUI_LOGOUT, + GUI_HTTP, + GUI_SET_ETHERNET_ADDR, + GUI_SET_LOGO, + GUI_POLL_EVENT, + GUI_GET_EVENT, + GUI_GET_HW_MONITOR, + // GUI_QUICK_CREATE=0x20, (function removed) + GUI_GET_INFO_R=0x20, + GUI_GET_INFO_V, + GUI_GET_INFO_P, + GUI_GET_INFO_S, + GUI_CLEAR_EVENT, + GUI_MUTE_BEEPER=0x30, + GUI_BEEPER_SETTING, + GUI_SET_PASSWORD, + GUI_HOST_INTERFACE_MODE, + GUI_REBUILD_PRIORITY, + GUI_MAX_ATA_MODE, + GUI_RESET_CONTROLLER, + GUI_COM_PORT_SETTING, + GUI_NO_OPERATION, + GUI_DHCP_IP, + GUI_CREATE_PASS_THROUGH=0x40, + GUI_MODIFY_PASS_THROUGH, + GUI_DELETE_PASS_THROUGH, + GUI_IDENTIFY_DEVICE, + GUI_CREATE_RAIDSET=0x50, + GUI_DELETE_RAIDSET, + GUI_EXPAND_RAIDSET, + GUI_ACTIVATE_RAIDSET, + GUI_CREATE_HOT_SPARE, + GUI_DELETE_HOT_SPARE, + GUI_CREATE_VOLUME=0x60, + GUI_MODIFY_VOLUME, + GUI_DELETE_VOLUME, + GUI_START_CHECK_VOLUME, + GUI_STOP_CHECK_VOLUME + }; + +Command description +^^^^^^^^^^^^^^^^^^^ + +GUI_SET_SERIAL + Set the controller serial# + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x10 + byte 3 password length (should be 0x0f) + byte 4-0x13 should be "ArEcATecHnoLogY" + byte 0x14--0x23 Serial number string (must be 16 bytes) + ================ ============================================= + +GUI_SET_VENDOR + Set vendor string for the controller + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x11 + byte 3 password length (should be 0x08) + byte 4-0x13 should be "ArEcAvAr" + byte 0x14--0x3B vendor string (must be 40 bytes) + ================ ============================================= + +GUI_SET_MODEL + Set the model name of the controller + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x12 + byte 3 password length (should be 0x08) + byte 4-0x13 should be "ArEcAvAr" + byte 0x14--0x1B model string (must be 8 bytes) + ================ ============================================= + +GUI_IDENTIFY + Identify device + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x13 + return "Areca RAID Subsystem " + ================ ============================================= + +GUI_CHECK_PASSWORD + Verify password + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x14 + byte 3 password length + byte 4-0x?? user password to be checked + ================ ============================================= + +GUI_LOGOUT + Logout GUI (force password checking on next command) + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x15 + ================ ============================================= + +GUI_HTTP + HTTP interface (reserved for Http proxy service)(0x16) + +GUI_SET_ETHERNET_ADDR + Set the ethernet MAC address + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x17 + byte 3 password length (should be 0x08) + byte 4-0x13 should be "ArEcAvAr" + byte 0x14--0x19 Ethernet MAC address (must be 6 bytes) + ================ ============================================= + +GUI_SET_LOGO + Set logo in HTTP + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x18 + byte 3 Page# (0/1/2/3) (0xff --> clear OEM logo) + byte 4/5/6/7 0x55/0xaa/0xa5/0x5a + byte 8 TITLE.JPG data (each page must be 2000 bytes) + + .. Note:: page0 1st 2 byte must be + actual length of the JPG file + ================ ============================================= + +GUI_POLL_EVENT + Poll If Event Log Changed + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x19 + ================ ============================================= + +GUI_GET_EVENT + Read Event + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x1a + byte 3 Event Page (0:1st page/1/2/3:last page) + ================ ============================================= + +GUI_GET_HW_MONITOR + Get HW monitor data + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x1b + byte 3 # of FANs(example 2) + byte 4 # of Voltage sensor(example 3) + byte 5 # of temperature sensor(example 2) + byte 6 # of power + byte 7/8 Fan#0 (RPM) + byte 9/10 Fan#1 + byte 11/12 Voltage#0 original value in ``*1000`` + byte 13/14 Voltage#0 value + byte 15/16 Voltage#1 org + byte 17/18 Voltage#1 + byte 19/20 Voltage#2 org + byte 21/22 Voltage#2 + byte 23 Temp#0 + byte 24 Temp#1 + byte 25 Power indicator (bit0 power#0, + bit1 power#1) + byte 26 UPS indicator + ================ ============================================= + +GUI_QUICK_CREATE + Quick create raid/volume set + + ================ ============================================== + byte 0,1 length + byte 2 command code 0x20 + byte 3/4/5/6 raw capacity + byte 7 raid level + byte 8 stripe size + byte 9 spare + byte 10/11/12/13 device mask (the devices to create raid/volume) + ================ ============================================== + + This function is removed, application like + to implement quick create function + + need to use GUI_CREATE_RAIDSET and GUI_CREATE_VOLUMESET function. + +GUI_GET_INFO_R + Get Raid Set Information + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x20 + byte 3 raidset# + ================ ============================================= + + :: + + typedef struct sGUI_RAIDSET + { + BYTE grsRaidSetName[16]; + DWORD grsCapacity; + DWORD grsCapacityX; + DWORD grsFailMask; + BYTE grsDevArray[32]; + BYTE grsMemberDevices; + BYTE grsNewMemberDevices; + BYTE grsRaidState; + BYTE grsVolumes; + BYTE grsVolumeList[16]; + BYTE grsRes1; + BYTE grsRes2; + BYTE grsRes3; + BYTE grsFreeSegments; + DWORD grsRawStripes[8]; + DWORD grsRes4; + DWORD grsRes5; // Total to 128 bytes + DWORD grsRes6; // Total to 128 bytes + } sGUI_RAIDSET, *pGUI_RAIDSET; + +GUI_GET_INFO_V + Get Volume Set Information + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x21 + byte 3 volumeset# + ================ ============================================= + + :: + + typedef struct sGUI_VOLUMESET + { + BYTE gvsVolumeName[16]; // 16 + DWORD gvsCapacity; + DWORD gvsCapacityX; + DWORD gvsFailMask; + DWORD gvsStripeSize; + DWORD gvsNewFailMask; + DWORD gvsNewStripeSize; + DWORD gvsVolumeStatus; + DWORD gvsProgress; // 32 + sSCSI_ATTR gvsScsi; + BYTE gvsMemberDisks; + BYTE gvsRaidLevel; // 8 + BYTE gvsNewMemberDisks; + BYTE gvsNewRaidLevel; + BYTE gvsRaidSetNumber; + BYTE gvsRes0; // 4 + BYTE gvsRes1[4]; // 64 bytes + } sGUI_VOLUMESET, *pGUI_VOLUMESET; + +GUI_GET_INFO_P + Get Physical Drive Information + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x22 + byte 3 drive # (from 0 to max-channels - 1) + ================ ============================================= + + :: + + typedef struct sGUI_PHY_DRV + { + BYTE gpdModelName[40]; + BYTE gpdSerialNumber[20]; + BYTE gpdFirmRev[8]; + DWORD gpdCapacity; + DWORD gpdCapacityX; // Reserved for expansion + BYTE gpdDeviceState; + BYTE gpdPioMode; + BYTE gpdCurrentUdmaMode; + BYTE gpdUdmaMode; + BYTE gpdDriveSelect; + BYTE gpdRaidNumber; // 0xff if not belongs to a raid set + sSCSI_ATTR gpdScsi; + BYTE gpdReserved[40]; // Total to 128 bytes + } sGUI_PHY_DRV, *pGUI_PHY_DRV; + +GUI_GET_INFO_S + Get System Information + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x23 + ================ ============================================= + + :: + + typedef struct sCOM_ATTR + { + BYTE comBaudRate; + BYTE comDataBits; + BYTE comStopBits; + BYTE comParity; + BYTE comFlowControl; + } sCOM_ATTR, *pCOM_ATTR; + typedef struct sSYSTEM_INFO + { + BYTE gsiVendorName[40]; + BYTE gsiSerialNumber[16]; + BYTE gsiFirmVersion[16]; + BYTE gsiBootVersion[16]; + BYTE gsiMbVersion[16]; + BYTE gsiModelName[8]; + BYTE gsiLocalIp[4]; + BYTE gsiCurrentIp[4]; + DWORD gsiTimeTick; + DWORD gsiCpuSpeed; + DWORD gsiICache; + DWORD gsiDCache; + DWORD gsiScache; + DWORD gsiMemorySize; + DWORD gsiMemorySpeed; + DWORD gsiEvents; + BYTE gsiMacAddress[6]; + BYTE gsiDhcp; + BYTE gsiBeeper; + BYTE gsiChannelUsage; + BYTE gsiMaxAtaMode; + BYTE gsiSdramEcc; // 1:if ECC enabled + BYTE gsiRebuildPriority; + sCOM_ATTR gsiComA; // 5 bytes + sCOM_ATTR gsiComB; // 5 bytes + BYTE gsiIdeChannels; + BYTE gsiScsiHostChannels; + BYTE gsiIdeHostChannels; + BYTE gsiMaxVolumeSet; + BYTE gsiMaxRaidSet; + BYTE gsiEtherPort; // 1:if ether net port supported + BYTE gsiRaid6Engine; // 1:Raid6 engine supported + BYTE gsiRes[75]; + } sSYSTEM_INFO, *pSYSTEM_INFO; + +GUI_CLEAR_EVENT + Clear System Event + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x24 + ================ ============================================= + +GUI_MUTE_BEEPER + Mute current beeper + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x30 + ================ ============================================= +GUI_BEEPER_SETTING + Disable beeper + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x31 + byte 3 0->disable, 1->enable + ================ ============================================= + +GUI_SET_PASSWORD + Change password + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x32 + byte 3 pass word length ( must <= 15 ) + byte 4 password (must be alpha-numerical) + ================ ============================================= + +GUI_HOST_INTERFACE_MODE + Set host interface mode + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x33 + byte 3 0->Independent, 1->cluster + ================ ============================================= + +GUI_REBUILD_PRIORITY + Set rebuild priority + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x34 + byte 3 0/1/2/3 (low->high) + ================ ============================================= + +GUI_MAX_ATA_MODE + Set maximum ATA mode to be used + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x35 + byte 3 0/1/2/3 (133/100/66/33) + ================ ============================================= + +GUI_RESET_CONTROLLER + Reset Controller + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x36 + * Response with VT100 screen (discard it) + ================ ============================================= + +GUI_COM_PORT_SETTING + COM port setting + + ================ ================================================= + byte 0,1 length + byte 2 command code 0x37 + byte 3 0->COMA (term port), + 1->COMB (debug port) + byte 4 0/1/2/3/4/5/6/7 + (1200/2400/4800/9600/19200/38400/57600/115200) + byte 5 data bit + (0:7 bit, 1:8 bit must be 8 bit) + byte 6 stop bit (0:1, 1:2 stop bits) + byte 7 parity (0:none, 1:off, 2:even) + byte 8 flow control + (0:none, 1:xon/xoff, 2:hardware => must use none) + ================ ================================================= + +GUI_NO_OPERATION + No operation + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x38 + ================ ============================================= + +GUI_DHCP_IP + Set DHCP option and local IP address + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x39 + byte 3 0:dhcp disabled, 1:dhcp enabled + byte 4/5/6/7 IP address + ================ ============================================= + +GUI_CREATE_PASS_THROUGH + Create pass through disk + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x40 + byte 3 device # + byte 4 scsi channel (0/1) + byte 5 scsi id (0-->15) + byte 6 scsi lun (0-->7) + byte 7 tagged queue (1 enabled) + byte 8 cache mode (1 enabled) + byte 9 max speed (0/1/2/3/4, + async/20/40/80/160 for scsi) + (0/1/2/3/4, 33/66/100/133/150 for ide ) + ================ ============================================= + +GUI_MODIFY_PASS_THROUGH + Modify pass through disk + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x41 + byte 3 device # + byte 4 scsi channel (0/1) + byte 5 scsi id (0-->15) + byte 6 scsi lun (0-->7) + byte 7 tagged queue (1 enabled) + byte 8 cache mode (1 enabled) + byte 9 max speed (0/1/2/3/4, + async/20/40/80/160 for scsi) + (0/1/2/3/4, 33/66/100/133/150 for ide ) + ================ ============================================= + +GUI_DELETE_PASS_THROUGH + Delete pass through disk + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x42 + byte 3 device# to be deleted + ================ ============================================= +GUI_IDENTIFY_DEVICE + Identify Device + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x43 + byte 3 Flash Method + (0:flash selected, 1:flash not selected) + byte 4/5/6/7 IDE device mask to be flashed + .. Note:: no response data available + ================ ============================================= + +GUI_CREATE_RAIDSET + Create Raid Set + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x50 + byte 3/4/5/6 device mask + byte 7-22 raidset name (if byte 7 == 0:use default) + ================ ============================================= + +GUI_DELETE_RAIDSET + Delete Raid Set + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x51 + byte 3 raidset# + ================ ============================================= + +GUI_EXPAND_RAIDSET + Expand Raid Set + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x52 + byte 3 raidset# + byte 4/5/6/7 device mask for expansion + byte 8/9/10 (8:0 no change, 1 change, 0xff:terminate, + 9:new raid level, + 10:new stripe size + 0/1/2/3/4/5->4/8/16/32/64/128K ) + byte 11/12/13 repeat for each volume in the raidset + ================ ============================================= + +GUI_ACTIVATE_RAIDSET + Activate incomplete raid set + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x53 + byte 3 raidset# + ================ ============================================= + +GUI_CREATE_HOT_SPARE + Create hot spare disk + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x54 + byte 3/4/5/6 device mask for hot spare creation + ================ ============================================= + +GUI_DELETE_HOT_SPARE + Delete hot spare disk + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x55 + byte 3/4/5/6 device mask for hot spare deletion + ================ ============================================= + +GUI_CREATE_VOLUME + Create volume set + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x60 + byte 3 raidset# + byte 4-19 volume set name + (if byte4 == 0, use default) + byte 20-27 volume capacity (blocks) + byte 28 raid level + byte 29 stripe size + (0/1/2/3/4/5->4/8/16/32/64/128K) + byte 30 channel + byte 31 ID + byte 32 LUN + byte 33 1 enable tag + byte 34 1 enable cache + byte 35 speed + (0/1/2/3/4->async/20/40/80/160 for scsi) + (0/1/2/3/4->33/66/100/133/150 for IDE ) + byte 36 1 to select quick init + ================ ============================================= + +GUI_MODIFY_VOLUME + Modify volume Set + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x61 + byte 3 volumeset# + byte 4-19 new volume set name + (if byte4 == 0, not change) + byte 20-27 new volume capacity (reserved) + byte 28 new raid level + byte 29 new stripe size + (0/1/2/3/4/5->4/8/16/32/64/128K) + byte 30 new channel + byte 31 new ID + byte 32 new LUN + byte 33 1 enable tag + byte 34 1 enable cache + byte 35 speed + (0/1/2/3/4->async/20/40/80/160 for scsi) + (0/1/2/3/4->33/66/100/133/150 for IDE ) + ================ ============================================= + +GUI_DELETE_VOLUME + Delete volume set + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x62 + byte 3 volumeset# + ================ ============================================= + +GUI_START_CHECK_VOLUME + Start volume consistency check + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x63 + byte 3 volumeset# + ================ ============================================= + +GUI_STOP_CHECK_VOLUME + Stop volume consistency check + + ================ ============================================= + byte 0,1 length + byte 2 command code 0x64 + ================ ============================================= + +4. Returned data +---------------- + +(A) Header + 3 bytes sequence (0x5E, 0x01, 0x61) +(B) Length + 2 bytes + (low byte 1st, excludes length and checksum byte) +(C) + status or data: + + 1) If length == 1 ==> 1 byte status code:: + + #define GUI_OK 0x41 + #define GUI_RAIDSET_NOT_NORMAL 0x42 + #define GUI_VOLUMESET_NOT_NORMAL 0x43 + #define GUI_NO_RAIDSET 0x44 + #define GUI_NO_VOLUMESET 0x45 + #define GUI_NO_PHYSICAL_DRIVE 0x46 + #define GUI_PARAMETER_ERROR 0x47 + #define GUI_UNSUPPORTED_COMMAND 0x48 + #define GUI_DISK_CONFIG_CHANGED 0x49 + #define GUI_INVALID_PASSWORD 0x4a + #define GUI_NO_DISK_SPACE 0x4b + #define GUI_CHECKSUM_ERROR 0x4c + #define GUI_PASSWORD_REQUIRED 0x4d + + 2) If length > 1: + + data block returned from controller + and the contents depends on the command code + +(E) Checksum + checksum of length and status or data byte + diff --git a/Documentation/scsi/arcmsr_spec.txt b/Documentation/scsi/arcmsr_spec.txt deleted file mode 100644 index 45d9482c1517..000000000000 --- a/Documentation/scsi/arcmsr_spec.txt +++ /dev/null @@ -1,574 +0,0 @@ -******************************************************************************* -** ARECA FIRMWARE SPEC -******************************************************************************* -** Usage of IOP331 adapter -** (All In/Out is in IOP331's view) -** 1. Message 0 --> InitThread message and return code -** 2. Doorbell is used for RS-232 emulation -** inDoorBell : bit0 -- data in ready -** (DRIVER DATA WRITE OK) -** bit1 -- data out has been read -** (DRIVER DATA READ OK) -** outDooeBell: bit0 -- data out ready -** (IOP331 DATA WRITE OK) -** bit1 -- data in has been read -** (IOP331 DATA READ OK) -** 3. Index Memory Usage -** offset 0xf00 : for RS232 out (request buffer) -** offset 0xe00 : for RS232 in (scratch buffer) -** offset 0xa00 : for inbound message code message_rwbuffer -** (driver send to IOP331) -** offset 0xa00 : for outbound message code message_rwbuffer -** (IOP331 send to driver) -** 4. RS-232 emulation -** Currently 128 byte buffer is used -** 1st uint32_t : Data length (1--124) -** Byte 4--127 : Max 124 bytes of data -** 5. PostQ -** All SCSI Command must be sent through postQ: -** (inbound queue port) Request frame must be 32 bytes aligned -** #bit27--bit31 => flag for post ccb -** #bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb -** bit31 : -** 0 : 256 bytes frame -** 1 : 512 bytes frame -** bit30 : -** 0 : normal request -** 1 : BIOS request -** bit29 : reserved -** bit28 : reserved -** bit27 : reserved -** --------------------------------------------------------------------------- -** (outbount queue port) Request reply -** #bit27--bit31 -** => flag for reply -** #bit0--bit26 -** => real address (bit27--bit31) of reply arcmsr_cdb -** bit31 : must be 0 (for this type of reply) -** bit30 : reserved for BIOS handshake -** bit29 : reserved -** bit28 : -** 0 : no error, ignore AdapStatus/DevStatus/SenseData -** 1 : Error, error code in AdapStatus/DevStatus/SenseData -** bit27 : reserved -** 6. BIOS request -** All BIOS request is the same with request from PostQ -** Except : -** Request frame is sent from configuration space -** offset: 0x78 : Request Frame (bit30 == 1) -** offset: 0x18 : writeonly to generate -** IRQ to IOP331 -** Completion of request: -** (bit30 == 0, bit28==err flag) -** 7. Definition of SGL entry (structure) -** 8. Message1 Out - Diag Status Code (????) -** 9. Message0 message code : -** 0x00 : NOP -** 0x01 : Get Config -** ->offset 0xa00 :for outbound message code message_rwbuffer -** (IOP331 send to driver) -** Signature 0x87974060(4) -** Request len 0x00000200(4) -** numbers of queue 0x00000100(4) -** SDRAM Size 0x00000100(4)-->256 MB -** IDE Channels 0x00000008(4) -** vendor 40 bytes char -** model 8 bytes char -** FirmVer 16 bytes char -** Device Map 16 bytes char -** FirmwareVersion DWORD <== Added for checking of -** new firmware capability -** 0x02 : Set Config -** ->offset 0xa00 :for inbound message code message_rwbuffer -** (driver send to IOP331) -** Signature 0x87974063(4) -** UPPER32 of Request Frame (4)-->Driver Only -** 0x03 : Reset (Abort all queued Command) -** 0x04 : Stop Background Activity -** 0x05 : Flush Cache -** 0x06 : Start Background Activity -** (re-start if background is halted) -** 0x07 : Check If Host Command Pending -** (Novell May Need This Function) -** 0x08 : Set controller time -** ->offset 0xa00 : for inbound message code message_rwbuffer -** (driver to IOP331) -** byte 0 : 0xaa <-- signature -** byte 1 : 0x55 <-- signature -** byte 2 : year (04) -** byte 3 : month (1..12) -** byte 4 : date (1..31) -** byte 5 : hour (0..23) -** byte 6 : minute (0..59) -** byte 7 : second (0..59) -******************************************************************************* -******************************************************************************* -** RS-232 Interface for Areca Raid Controller -** The low level command interface is exclusive with VT100 terminal -** -------------------------------------------------------------------- -** 1. Sequence of command execution -** -------------------------------------------------------------------- -** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) -** (B) Command block : variable length of data including length, -** command code, data and checksum byte -** (C) Return data : variable length of data -** -------------------------------------------------------------------- -** 2. Command block -** -------------------------------------------------------------------- -** (A) 1st byte : command block length (low byte) -** (B) 2nd byte : command block length (high byte) -** note ..command block length shouldn't > 2040 bytes, -** length excludes these two bytes -** (C) 3rd byte : command code -** (D) 4th and following bytes : variable length data bytes -** depends on command code -** (E) last byte : checksum byte (sum of 1st byte until last data byte) -** -------------------------------------------------------------------- -** 3. Command code and associated data -** -------------------------------------------------------------------- -** The following are command code defined in raid controller Command -** code 0x10--0x1? are used for system level management, -** no password checking is needed and should be implemented in separate -** well controlled utility and not for end user access. -** Command code 0x20--0x?? always check the password, -** password must be entered to enable these command. -** enum -** { -** GUI_SET_SERIAL=0x10, -** GUI_SET_VENDOR, -** GUI_SET_MODEL, -** GUI_IDENTIFY, -** GUI_CHECK_PASSWORD, -** GUI_LOGOUT, -** GUI_HTTP, -** GUI_SET_ETHERNET_ADDR, -** GUI_SET_LOGO, -** GUI_POLL_EVENT, -** GUI_GET_EVENT, -** GUI_GET_HW_MONITOR, -** // GUI_QUICK_CREATE=0x20, (function removed) -** GUI_GET_INFO_R=0x20, -** GUI_GET_INFO_V, -** GUI_GET_INFO_P, -** GUI_GET_INFO_S, -** GUI_CLEAR_EVENT, -** GUI_MUTE_BEEPER=0x30, -** GUI_BEEPER_SETTING, -** GUI_SET_PASSWORD, -** GUI_HOST_INTERFACE_MODE, -** GUI_REBUILD_PRIORITY, -** GUI_MAX_ATA_MODE, -** GUI_RESET_CONTROLLER, -** GUI_COM_PORT_SETTING, -** GUI_NO_OPERATION, -** GUI_DHCP_IP, -** GUI_CREATE_PASS_THROUGH=0x40, -** GUI_MODIFY_PASS_THROUGH, -** GUI_DELETE_PASS_THROUGH, -** GUI_IDENTIFY_DEVICE, -** GUI_CREATE_RAIDSET=0x50, -** GUI_DELETE_RAIDSET, -** GUI_EXPAND_RAIDSET, -** GUI_ACTIVATE_RAIDSET, -** GUI_CREATE_HOT_SPARE, -** GUI_DELETE_HOT_SPARE, -** GUI_CREATE_VOLUME=0x60, -** GUI_MODIFY_VOLUME, -** GUI_DELETE_VOLUME, -** GUI_START_CHECK_VOLUME, -** GUI_STOP_CHECK_VOLUME -** }; -** Command description : -** GUI_SET_SERIAL : Set the controller serial# -** byte 0,1 : length -** byte 2 : command code 0x10 -** byte 3 : password length (should be 0x0f) -** byte 4-0x13 : should be "ArEcATecHnoLogY" -** byte 0x14--0x23 : Serial number string (must be 16 bytes) -** GUI_SET_VENDOR : Set vendor string for the controller -** byte 0,1 : length -** byte 2 : command code 0x11 -** byte 3 : password length (should be 0x08) -** byte 4-0x13 : should be "ArEcAvAr" -** byte 0x14--0x3B : vendor string (must be 40 bytes) -** GUI_SET_MODEL : Set the model name of the controller -** byte 0,1 : length -** byte 2 : command code 0x12 -** byte 3 : password length (should be 0x08) -** byte 4-0x13 : should be "ArEcAvAr" -** byte 0x14--0x1B : model string (must be 8 bytes) -** GUI_IDENTIFY : Identify device -** byte 0,1 : length -** byte 2 : command code 0x13 -** return "Areca RAID Subsystem " -** GUI_CHECK_PASSWORD : Verify password -** byte 0,1 : length -** byte 2 : command code 0x14 -** byte 3 : password length -** byte 4-0x?? : user password to be checked -** GUI_LOGOUT : Logout GUI (force password checking on next command) -** byte 0,1 : length -** byte 2 : command code 0x15 -** GUI_HTTP : HTTP interface (reserved for Http proxy service)(0x16) -** -** GUI_SET_ETHERNET_ADDR : Set the ethernet MAC address -** byte 0,1 : length -** byte 2 : command code 0x17 -** byte 3 : password length (should be 0x08) -** byte 4-0x13 : should be "ArEcAvAr" -** byte 0x14--0x19 : Ethernet MAC address (must be 6 bytes) -** GUI_SET_LOGO : Set logo in HTTP -** byte 0,1 : length -** byte 2 : command code 0x18 -** byte 3 : Page# (0/1/2/3) (0xff --> clear OEM logo) -** byte 4/5/6/7 : 0x55/0xaa/0xa5/0x5a -** byte 8 : TITLE.JPG data (each page must be 2000 bytes) -** note page0 1st 2 byte must be -** actual length of the JPG file -** GUI_POLL_EVENT : Poll If Event Log Changed -** byte 0,1 : length -** byte 2 : command code 0x19 -** GUI_GET_EVENT : Read Event -** byte 0,1 : length -** byte 2 : command code 0x1a -** byte 3 : Event Page (0:1st page/1/2/3:last page) -** GUI_GET_HW_MONITOR : Get HW monitor data -** byte 0,1 : length -** byte 2 : command code 0x1b -** byte 3 : # of FANs(example 2) -** byte 4 : # of Voltage sensor(example 3) -** byte 5 : # of temperature sensor(example 2) -** byte 6 : # of power -** byte 7/8 : Fan#0 (RPM) -** byte 9/10 : Fan#1 -** byte 11/12 : Voltage#0 original value in *1000 -** byte 13/14 : Voltage#0 value -** byte 15/16 : Voltage#1 org -** byte 17/18 : Voltage#1 -** byte 19/20 : Voltage#2 org -** byte 21/22 : Voltage#2 -** byte 23 : Temp#0 -** byte 24 : Temp#1 -** byte 25 : Power indicator (bit0 : power#0, -** bit1 : power#1) -** byte 26 : UPS indicator -** GUI_QUICK_CREATE : Quick create raid/volume set -** byte 0,1 : length -** byte 2 : command code 0x20 -** byte 3/4/5/6 : raw capacity -** byte 7 : raid level -** byte 8 : stripe size -** byte 9 : spare -** byte 10/11/12/13: device mask (the devices to create raid/volume) -** This function is removed, application like -** to implement quick create function -** need to use GUI_CREATE_RAIDSET and GUI_CREATE_VOLUMESET function. -** GUI_GET_INFO_R : Get Raid Set Information -** byte 0,1 : length -** byte 2 : command code 0x20 -** byte 3 : raidset# -** typedef struct sGUI_RAIDSET -** { -** BYTE grsRaidSetName[16]; -** DWORD grsCapacity; -** DWORD grsCapacityX; -** DWORD grsFailMask; -** BYTE grsDevArray[32]; -** BYTE grsMemberDevices; -** BYTE grsNewMemberDevices; -** BYTE grsRaidState; -** BYTE grsVolumes; -** BYTE grsVolumeList[16]; -** BYTE grsRes1; -** BYTE grsRes2; -** BYTE grsRes3; -** BYTE grsFreeSegments; -** DWORD grsRawStripes[8]; -** DWORD grsRes4; -** DWORD grsRes5; // Total to 128 bytes -** DWORD grsRes6; // Total to 128 bytes -** } sGUI_RAIDSET, *pGUI_RAIDSET; -** GUI_GET_INFO_V : Get Volume Set Information -** byte 0,1 : length -** byte 2 : command code 0x21 -** byte 3 : volumeset# -** typedef struct sGUI_VOLUMESET -** { -** BYTE gvsVolumeName[16]; // 16 -** DWORD gvsCapacity; -** DWORD gvsCapacityX; -** DWORD gvsFailMask; -** DWORD gvsStripeSize; -** DWORD gvsNewFailMask; -** DWORD gvsNewStripeSize; -** DWORD gvsVolumeStatus; -** DWORD gvsProgress; // 32 -** sSCSI_ATTR gvsScsi; -** BYTE gvsMemberDisks; -** BYTE gvsRaidLevel; // 8 -** BYTE gvsNewMemberDisks; -** BYTE gvsNewRaidLevel; -** BYTE gvsRaidSetNumber; -** BYTE gvsRes0; // 4 -** BYTE gvsRes1[4]; // 64 bytes -** } sGUI_VOLUMESET, *pGUI_VOLUMESET; -** GUI_GET_INFO_P : Get Physical Drive Information -** byte 0,1 : length -** byte 2 : command code 0x22 -** byte 3 : drive # (from 0 to max-channels - 1) -** typedef struct sGUI_PHY_DRV -** { -** BYTE gpdModelName[40]; -** BYTE gpdSerialNumber[20]; -** BYTE gpdFirmRev[8]; -** DWORD gpdCapacity; -** DWORD gpdCapacityX; // Reserved for expansion -** BYTE gpdDeviceState; -** BYTE gpdPioMode; -** BYTE gpdCurrentUdmaMode; -** BYTE gpdUdmaMode; -** BYTE gpdDriveSelect; -** BYTE gpdRaidNumber; // 0xff if not belongs to a raid set -** sSCSI_ATTR gpdScsi; -** BYTE gpdReserved[40]; // Total to 128 bytes -** } sGUI_PHY_DRV, *pGUI_PHY_DRV; -** GUI_GET_INFO_S : Get System Information -** byte 0,1 : length -** byte 2 : command code 0x23 -** typedef struct sCOM_ATTR -** { -** BYTE comBaudRate; -** BYTE comDataBits; -** BYTE comStopBits; -** BYTE comParity; -** BYTE comFlowControl; -** } sCOM_ATTR, *pCOM_ATTR; -** typedef struct sSYSTEM_INFO -** { -** BYTE gsiVendorName[40]; -** BYTE gsiSerialNumber[16]; -** BYTE gsiFirmVersion[16]; -** BYTE gsiBootVersion[16]; -** BYTE gsiMbVersion[16]; -** BYTE gsiModelName[8]; -** BYTE gsiLocalIp[4]; -** BYTE gsiCurrentIp[4]; -** DWORD gsiTimeTick; -** DWORD gsiCpuSpeed; -** DWORD gsiICache; -** DWORD gsiDCache; -** DWORD gsiScache; -** DWORD gsiMemorySize; -** DWORD gsiMemorySpeed; -** DWORD gsiEvents; -** BYTE gsiMacAddress[6]; -** BYTE gsiDhcp; -** BYTE gsiBeeper; -** BYTE gsiChannelUsage; -** BYTE gsiMaxAtaMode; -** BYTE gsiSdramEcc; // 1:if ECC enabled -** BYTE gsiRebuildPriority; -** sCOM_ATTR gsiComA; // 5 bytes -** sCOM_ATTR gsiComB; // 5 bytes -** BYTE gsiIdeChannels; -** BYTE gsiScsiHostChannels; -** BYTE gsiIdeHostChannels; -** BYTE gsiMaxVolumeSet; -** BYTE gsiMaxRaidSet; -** BYTE gsiEtherPort; // 1:if ether net port supported -** BYTE gsiRaid6Engine; // 1:Raid6 engine supported -** BYTE gsiRes[75]; -** } sSYSTEM_INFO, *pSYSTEM_INFO; -** GUI_CLEAR_EVENT : Clear System Event -** byte 0,1 : length -** byte 2 : command code 0x24 -** GUI_MUTE_BEEPER : Mute current beeper -** byte 0,1 : length -** byte 2 : command code 0x30 -** GUI_BEEPER_SETTING : Disable beeper -** byte 0,1 : length -** byte 2 : command code 0x31 -** byte 3 : 0->disable, 1->enable -** GUI_SET_PASSWORD : Change password -** byte 0,1 : length -** byte 2 : command code 0x32 -** byte 3 : pass word length ( must <= 15 ) -** byte 4 : password (must be alpha-numerical) -** GUI_HOST_INTERFACE_MODE : Set host interface mode -** byte 0,1 : length -** byte 2 : command code 0x33 -** byte 3 : 0->Independent, 1->cluster -** GUI_REBUILD_PRIORITY : Set rebuild priority -** byte 0,1 : length -** byte 2 : command code 0x34 -** byte 3 : 0/1/2/3 (low->high) -** GUI_MAX_ATA_MODE : Set maximum ATA mode to be used -** byte 0,1 : length -** byte 2 : command code 0x35 -** byte 3 : 0/1/2/3 (133/100/66/33) -** GUI_RESET_CONTROLLER : Reset Controller -** byte 0,1 : length -** byte 2 : command code 0x36 -** *Response with VT100 screen (discard it) -** GUI_COM_PORT_SETTING : COM port setting -** byte 0,1 : length -** byte 2 : command code 0x37 -** byte 3 : 0->COMA (term port), -** 1->COMB (debug port) -** byte 4 : 0/1/2/3/4/5/6/7 -** (1200/2400/4800/9600/19200/38400/57600/115200) -** byte 5 : data bit -** (0:7 bit, 1:8 bit : must be 8 bit) -** byte 6 : stop bit (0:1, 1:2 stop bits) -** byte 7 : parity (0:none, 1:off, 2:even) -** byte 8 : flow control -** (0:none, 1:xon/xoff, 2:hardware => must use none) -** GUI_NO_OPERATION : No operation -** byte 0,1 : length -** byte 2 : command code 0x38 -** GUI_DHCP_IP : Set DHCP option and local IP address -** byte 0,1 : length -** byte 2 : command code 0x39 -** byte 3 : 0:dhcp disabled, 1:dhcp enabled -** byte 4/5/6/7 : IP address -** GUI_CREATE_PASS_THROUGH : Create pass through disk -** byte 0,1 : length -** byte 2 : command code 0x40 -** byte 3 : device # -** byte 4 : scsi channel (0/1) -** byte 5 : scsi id (0-->15) -** byte 6 : scsi lun (0-->7) -** byte 7 : tagged queue (1 : enabled) -** byte 8 : cache mode (1 : enabled) -** byte 9 : max speed (0/1/2/3/4, -** async/20/40/80/160 for scsi) -** (0/1/2/3/4, 33/66/100/133/150 for ide ) -** GUI_MODIFY_PASS_THROUGH : Modify pass through disk -** byte 0,1 : length -** byte 2 : command code 0x41 -** byte 3 : device # -** byte 4 : scsi channel (0/1) -** byte 5 : scsi id (0-->15) -** byte 6 : scsi lun (0-->7) -** byte 7 : tagged queue (1 : enabled) -** byte 8 : cache mode (1 : enabled) -** byte 9 : max speed (0/1/2/3/4, -** async/20/40/80/160 for scsi) -** (0/1/2/3/4, 33/66/100/133/150 for ide ) -** GUI_DELETE_PASS_THROUGH : Delete pass through disk -** byte 0,1 : length -** byte 2 : command code 0x42 -** byte 3 : device# to be deleted -** GUI_IDENTIFY_DEVICE : Identify Device -** byte 0,1 : length -** byte 2 : command code 0x43 -** byte 3 : Flash Method -** (0:flash selected, 1:flash not selected) -** byte 4/5/6/7 : IDE device mask to be flashed -** note .... no response data available -** GUI_CREATE_RAIDSET : Create Raid Set -** byte 0,1 : length -** byte 2 : command code 0x50 -** byte 3/4/5/6 : device mask -** byte 7-22 : raidset name (if byte 7 == 0:use default) -** GUI_DELETE_RAIDSET : Delete Raid Set -** byte 0,1 : length -** byte 2 : command code 0x51 -** byte 3 : raidset# -** GUI_EXPAND_RAIDSET : Expand Raid Set -** byte 0,1 : length -** byte 2 : command code 0x52 -** byte 3 : raidset# -** byte 4/5/6/7 : device mask for expansion -** byte 8/9/10 : (8:0 no change, 1 change, 0xff:terminate, -** 9:new raid level, -** 10:new stripe size -** 0/1/2/3/4/5->4/8/16/32/64/128K ) -** byte 11/12/13 : repeat for each volume in the raidset -** GUI_ACTIVATE_RAIDSET : Activate incomplete raid set -** byte 0,1 : length -** byte 2 : command code 0x53 -** byte 3 : raidset# -** GUI_CREATE_HOT_SPARE : Create hot spare disk -** byte 0,1 : length -** byte 2 : command code 0x54 -** byte 3/4/5/6 : device mask for hot spare creation -** GUI_DELETE_HOT_SPARE : Delete hot spare disk -** byte 0,1 : length -** byte 2 : command code 0x55 -** byte 3/4/5/6 : device mask for hot spare deletion -** GUI_CREATE_VOLUME : Create volume set -** byte 0,1 : length -** byte 2 : command code 0x60 -** byte 3 : raidset# -** byte 4-19 : volume set name -** (if byte4 == 0, use default) -** byte 20-27 : volume capacity (blocks) -** byte 28 : raid level -** byte 29 : stripe size -** (0/1/2/3/4/5->4/8/16/32/64/128K) -** byte 30 : channel -** byte 31 : ID -** byte 32 : LUN -** byte 33 : 1 enable tag -** byte 34 : 1 enable cache -** byte 35 : speed -** (0/1/2/3/4->async/20/40/80/160 for scsi) -** (0/1/2/3/4->33/66/100/133/150 for IDE ) -** byte 36 : 1 to select quick init -** -** GUI_MODIFY_VOLUME : Modify volume Set -** byte 0,1 : length -** byte 2 : command code 0x61 -** byte 3 : volumeset# -** byte 4-19 : new volume set name -** (if byte4 == 0, not change) -** byte 20-27 : new volume capacity (reserved) -** byte 28 : new raid level -** byte 29 : new stripe size -** (0/1/2/3/4/5->4/8/16/32/64/128K) -** byte 30 : new channel -** byte 31 : new ID -** byte 32 : new LUN -** byte 33 : 1 enable tag -** byte 34 : 1 enable cache -** byte 35 : speed -** (0/1/2/3/4->async/20/40/80/160 for scsi) -** (0/1/2/3/4->33/66/100/133/150 for IDE ) -** GUI_DELETE_VOLUME : Delete volume set -** byte 0,1 : length -** byte 2 : command code 0x62 -** byte 3 : volumeset# -** GUI_START_CHECK_VOLUME : Start volume consistency check -** byte 0,1 : length -** byte 2 : command code 0x63 -** byte 3 : volumeset# -** GUI_STOP_CHECK_VOLUME : Stop volume consistency check -** byte 0,1 : length -** byte 2 : command code 0x64 -** --------------------------------------------------------------------- -** 4. Returned data -** --------------------------------------------------------------------- -** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) -** (B) Length : 2 bytes -** (low byte 1st, excludes length and checksum byte) -** (C) status or data : -** <1> If length == 1 ==> 1 byte status code -** #define GUI_OK 0x41 -** #define GUI_RAIDSET_NOT_NORMAL 0x42 -** #define GUI_VOLUMESET_NOT_NORMAL 0x43 -** #define GUI_NO_RAIDSET 0x44 -** #define GUI_NO_VOLUMESET 0x45 -** #define GUI_NO_PHYSICAL_DRIVE 0x46 -** #define GUI_PARAMETER_ERROR 0x47 -** #define GUI_UNSUPPORTED_COMMAND 0x48 -** #define GUI_DISK_CONFIG_CHANGED 0x49 -** #define GUI_INVALID_PASSWORD 0x4a -** #define GUI_NO_DISK_SPACE 0x4b -** #define GUI_CHECKSUM_ERROR 0x4c -** #define GUI_PASSWORD_REQUIRED 0x4d -** <2> If length > 1 ==> -** data block returned from controller -** and the contents depends on the command code -** (E) Checksum : checksum of length and status or data byte -************************************************************************** diff --git a/Documentation/scsi/bfa.txt b/Documentation/scsi/bfa.rst index 3cc4d80d6092..3abc0411857d 100644 --- a/Documentation/scsi/bfa.txt +++ b/Documentation/scsi/bfa.rst @@ -1,5 +1,8 @@ -Linux driver for Brocade FC/FCOE adapters +.. SPDX-License-Identifier: GPL-2.0 +========================================= +Linux driver for Brocade FC/FCOE adapters +========================================= Supported Hardware ------------------ @@ -7,8 +10,9 @@ Supported Hardware bfa 3.0.2.2 driver supports all Brocade FC/FCOE adapters. Below is a list of adapter models with corresponding PCIIDs. - PCIID Model - + =================== =========================================== + PCIID Model + =================== =========================================== 1657:0013:1657:0014 425 4Gbps dual port FC HBA 1657:0013:1657:0014 825 8Gbps PCIe dual port FC HBA 1657:0013:103c:1742 HP 82B 8Gbps PCIedual port FC HBA @@ -26,6 +30,7 @@ adapter models with corresponding PCIIDs. 1657:0022:1657:0024 1860 16Gbps FC HBA 1657:0022:1657:0022 1860 10Gbps CNA - FCOE + =================== =========================================== Firmware download @@ -37,9 +42,11 @@ http://www.brocade.com/services-support/drivers-downloads/adapters/Linux.page and then click following respective util package link: - Version Link - + ========= ======================================================= + Version Link + ========= ======================================================= v3.0.0.0 Linux Adapter Firmware package for RHEL 6.2, SLES 11SP2 + ========= ======================================================= Configuration & Management utility download @@ -52,9 +59,11 @@ http://www.brocade.com/services-support/drivers-downloads/adapters/Linux.page and then click following respective util package link - Version Link - + ========= ======================================================= + Version Link + ========= ======================================================= v3.0.2.0 Linux Adapter Firmware package for RHEL 6.2, SLES 11SP2 + ========= ======================================================= Documentation @@ -69,10 +78,11 @@ http://www.brocade.com/services-support/drivers-downloads/adapters/Linux.page and use the following inbox and out-of-box driver version mapping to find the corresponding documentation: + ============= ================== Inbox Version Out-of-box Version - + ============= ================== v3.0.2.2 v3.0.0.0 - + ============= ================== Support ------- diff --git a/Documentation/scsi/bnx2fc.txt b/Documentation/scsi/bnx2fc.rst index 80823556d62f..2fef2dff80c7 100644 --- a/Documentation/scsi/bnx2fc.txt +++ b/Documentation/scsi/bnx2fc.rst @@ -1,3 +1,6 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=========================== Operating FCoE using bnx2fc =========================== Broadcom FCoE offload through bnx2fc is full stateful hardware offload that @@ -24,6 +27,7 @@ Driver Usage Model: 2. Configure the interfaces on which bnx2fc driver has to operate on. Here are the steps to configure: + a. cd /etc/fcoe b. copy cfg-ethx to cfg-eth5 if FCoE has to be enabled on eth5. c. Repeat this for all the interfaces where FCoE has to be enabled. @@ -39,8 +43,10 @@ discovery and log into the targets. 5. "Symbolic Name" in 'fcoeadm -i' output would display if bnx2fc has claimed the interface. -Eg: -[root@bh2 ~]# fcoeadm -i + +Eg:: + + [root@bh2 ~]# fcoeadm -i Description: NetXtreme II BCM57712 10 Gigabit Ethernet Revision: 01 Manufacturer: Broadcom Corporation @@ -60,16 +66,16 @@ Eg: State: Online 6. Verify the vlan discovery is performed by running ifconfig and notice -<INTERFACE>.<VLAN>-fcoe interfaces are automatically created. + <INTERFACE>.<VLAN>-fcoe interfaces are automatically created. Refer to fcoeadm manpage for more information on fcoeadm operations to create/destroy interfaces or to display lun/target information. -NOTE: +NOTE ==== ** Broadcom FCoE capable devices implement a DCBX/LLDP client on-chip. Only one LLDP client is allowed per interface. For proper operation all host software based DCBX/LLDP clients (e.g. lldpad) must be disabled. To disable lldpad on a -given interface, run the following command: +given interface, run the following command:: -lldptool set-lldp -i <interface_name> adminStatus=disabled + lldptool set-lldp -i <interface_name> adminStatus=disabled diff --git a/Documentation/scsi/cxgb3i.txt b/Documentation/scsi/cxgb3i.rst index 7ac8032ee9b2..e01f18fbfa9f 100644 --- a/Documentation/scsi/cxgb3i.txt +++ b/Documentation/scsi/cxgb3i.rst @@ -1,4 +1,8 @@ +.. SPDX-License-Identifier: GPL-2.0 + +================================= Chelsio S3 iSCSI Driver for Linux +================================= Introduction ============ @@ -49,7 +53,8 @@ The following steps need to be taken to accelerates the open-iscsi initiator: The cxgb3i module registers a new transport class "cxgb3i" with open-iscsi. - * in the case of recompiling the kernel, the cxgb3i selection is located at + * in the case of recompiling the kernel, the cxgb3i selection is located at:: + Device Drivers SCSI device support ---> [*] SCSI low-level drivers ---> @@ -58,25 +63,26 @@ The following steps need to be taken to accelerates the open-iscsi initiator: 2. Create an interface file located under /etc/iscsi/ifaces/ for the new transport class "cxgb3i". - The content of the file should be in the following format: + The content of the file should be in the following format:: + iface.transport_name = cxgb3i iface.net_ifacename = <ethX> iface.ipaddress = <iscsi ip address> * if iface.ipaddress is specified, <iscsi ip address> needs to be either the - same as the ethX's ip address or an address on the same subnet. Make - sure the ip address is unique in the network. + same as the ethX's ip address or an address on the same subnet. Make + sure the ip address is unique in the network. 3. edit /etc/iscsi/iscsid.conf The default setting for MaxRecvDataSegmentLength (131072) is too big; - replace with a value no bigger than 15360 (for example 8192): + replace with a value no bigger than 15360 (for example 8192):: node.conn[0].iscsi.MaxRecvDataSegmentLength = 8192 * The login would fail for a normal session if MaxRecvDataSegmentLength is - too big. A error message in the format of - "cxgb3i: ERR! MaxRecvSegmentLength <X> too big. Need to be <= <Y>." - would be logged to dmesg. + too big. A error message in the format of + "cxgb3i: ERR! MaxRecvSegmentLength <X> too big. Need to be <= <Y>." + would be logged to dmesg. 4. To direct open-iscsi traffic to go through cxgb3i's accelerated path, "-I <iface file name>" option needs to be specified with most of the diff --git a/Documentation/scsi/dc395x.txt b/Documentation/scsi/dc395x.rst index 88219f96633d..d779e782b1cb 100644 --- a/Documentation/scsi/dc395x.txt +++ b/Documentation/scsi/dc395x.rst @@ -1,5 +1,8 @@ +.. SPDX-License-Identifier: GPL-2.0 + +====================================== README file for the dc395x SCSI driver -========================================== +====================================== Status ------ @@ -18,14 +21,14 @@ http://lists.twibble.org/mailman/listinfo/dc395x/ Parameters ---------- -The driver uses the settings from the EEPROM set in the SCSI BIOS +The driver uses the settings from the EEPROM set in the SCSI BIOS setup. If there is no EEPROM, the driver uses default values. Both can be overridden by command line parameters (module or kernel parameters). The following parameters are available: - - safe +safe Default: 0, Acceptable values: 0 or 1 If safe is set to 1 then the adapter will use conservative @@ -33,52 +36,63 @@ The following parameters are available: shortcut for dc395x=7,4,9,15,2,10 - - adapter_id +adapter_id Default: 7, Acceptable values: 0 to 15 Sets the host adapter SCSI ID. - - max_speed +max_speed Default: 1, Acceptable value: 0 to 7 - 0 = 20 Mhz - 1 = 12.2 Mhz - 2 = 10 Mhz - 3 = 8 Mhz - 4 = 6.7 Mhz - 5 = 5.8 Hhz - 6 = 5 Mhz - 7 = 4 Mhz - - - dev_mode + + == ======== + 0 20 Mhz + 1 12.2 Mhz + 2 10 Mhz + 3 8 Mhz + 4 6.7 Mhz + 5 5.8 Hhz + 6 5 Mhz + 7 4 Mhz + == ======== + +dev_mode Bitmap for device configuration DevMode bit definition: + + === ======== ======== ========================================= Bit Val(hex) Val(dec) Meaning - *0 0x01 1 Parity check - *1 0x02 2 Synchronous Negotiation - *2 0x04 4 Disconnection - *3 0x08 8 Send Start command on startup. (Not used) - *4 0x10 16 Tagged Command Queueing - *5 0x20 32 Wide Negotiation - - - adapter_mode + === ======== ======== ========================================= + 0 0x01 1 Parity check + 1 0x02 2 Synchronous Negotiation + 2 0x04 4 Disconnection + 3 0x08 8 Send Start command on startup. (Not used) + 4 0x10 16 Tagged Command Queueing + 5 0x20 32 Wide Negotiation + === ======== ======== ========================================= + +adapter_mode Bitmap for adapter configuration AdaptMode bit definition + + ===== ======== ======== ==================================================== Bit Val(hex) Val(dec) Meaning - *0 0x01 1 Support more than two drives. (Not used) - *1 0x02 2 Use DOS compatible mapping for HDs greater than 1GB. - *2 0x04 4 Reset SCSI Bus on startup. - *3 0x08 8 Active Negation: Improves SCSI Bus noise immunity. + ===== ======== ======== ==================================================== + 0 0x01 1 Support more than two drives. (Not used) + 1 0x02 2 Use DOS compatible mapping for HDs greater than 1GB. + 2 0x04 4 Reset SCSI Bus on startup. + 3 0x08 8 Active Negation: Improves SCSI Bus noise immunity. 4 0x10 16 Immediate return on BIOS seek command. (Not used) (*)5 0x20 32 Check for LUNs >= 1. + ===== ======== ======== ==================================================== - - tags +tags Default: 3, Acceptable values: 0-5 - + The number of tags is 1<<x, if x has been specified - - reset_delay +reset_delay Default: 1, Acceptable values: 0-180 The seconds to not accept commands after a SCSI Reset @@ -95,8 +109,9 @@ License (GPL). Please read it, before using this driver. It should be included in your kernel sources and with your distribution. It carries the filename COPYING. If you don't have it, please ask me to send you one by email. -Note: The GNU GPL says also something about warranty and liability. + +Note: The GNU GPL says also something about warranty and liability. Please be aware the following: While we do my best to provide a working and -reliable driver, there is a chance, that it will kill your valuable data. +reliable driver, there is a chance, that it will kill your valuable data. We refuse to take any responsibility for that. The driver is provided as-is and YOU USE IT AT YOUR OWN RESPONSIBILITY. diff --git a/Documentation/scsi/dpti.rst b/Documentation/scsi/dpti.rst new file mode 100644 index 000000000000..0496919d87d3 --- /dev/null +++ b/Documentation/scsi/dpti.rst @@ -0,0 +1,92 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=================== +Adaptec dpti driver +=================== + +Redistribution and use in source form, with or without modification, are +permitted provided that redistributions of source code must retain the +above copyright notice, this list of conditions and the following disclaimer. + +This software is provided ``as is`` by Adaptec and +any express or implied warranties, including, but not limited to, the +implied warranties of merchantability and fitness for a particular purpose, +are disclaimed. In no event shall Adaptec be +liable for any direct, indirect, incidental, special, exemplary or +consequential damages (including, but not limited to, procurement of +substitute goods or services; loss of use, data, or profits; or business +interruptions) however caused and on any theory of liability, whether in +contract, strict liability, or tort (including negligence or otherwise) +arising in any way out of the use of this driver software, even if advised +of the possibility of such damage. + +This driver supports the Adaptec I2O RAID and DPT SmartRAID V I2O boards. + +Credits +======= + +The original linux driver was ported to Linux by Karen White while at +Dell Computer. It was ported from Bob Pasteur's (of DPT) original +non-Linux driver. Mark Salyzyn and Bob Pasteur consulted on the original +driver. + +2.0 version of the driver by Deanna Bonds and Mark Salyzyn. + +History +======= + +The driver was originally ported to linux version 2.0.34 + +==== ========================================================================== +V2.0 Rewrite of driver. Re-architectured based on i2o subsystem. + This was the first full GPL version since the last version used + i2osig headers which were not GPL. Developer Testing version. +V2.1 Internal testing +V2.2 First released version + +V2.3 Changes: + + - Added Raptor Support + - Fixed bug causing system to hang under extreme load with + - management utilities running (removed GFP_DMA from kmalloc flags) + +V2.4 First version ready to be submitted to be embedded in the kernel + + Changes: + + - Implemented suggestions from Alan Cox + - Added calculation of resid for sg layer + - Better error handling + - Added checking underflow conditions + - Added DATAPROTECT checking + - Changed error return codes + - Fixed pointer bug in bus reset routine + - Enabled hba reset from ioctls (allows a FW flash to reboot and use + the new FW without having to reboot) + - Changed proc output +==== ========================================================================== + +TODO +==== +- Add 64 bit Scatter Gather when compiled on 64 bit architectures +- Add sparse lun scanning +- Add code that checks if a device that had been taken offline is + now online (at the FW level) when test unit ready or inquiry + command from scsi-core +- Add proc read interface +- busrescan command +- rescan command +- Add code to rescan routine that notifies scsi-core about new devices +- Add support for C-PCI (hotplug stuff) +- Add ioctl passthru error recovery + +Notes +===== +The DPT card optimizes the order of processing commands. Consequently, +a command may take up to 6 minutes to complete after it has been sent +to the board. + +The files dpti_ioctl.h dptsig.h osd_defs.h osd_util.h sys_info.h are part of the +interface files for Adaptec's management routines. These define the structures used +in the ioctls. They are written to be portable. They are hard to read, but I need +to use them 'as is' or I can miss changes in the interface. diff --git a/Documentation/scsi/dpti.txt b/Documentation/scsi/dpti.txt deleted file mode 100644 index f36dc0e7c8da..000000000000 --- a/Documentation/scsi/dpti.txt +++ /dev/null @@ -1,83 +0,0 @@ - /* TERMS AND CONDITIONS OF USE - * - * Redistribution and use in source form, with or without modification, are - * permitted provided that redistributions of source code must retain the - * above copyright notice, this list of conditions and the following disclaimer. - * - * This software is provided `as is' by Adaptec and - * any express or implied warranties, including, but not limited to, the - * implied warranties of merchantability and fitness for a particular purpose, - * are disclaimed. In no event shall Adaptec be - * liable for any direct, indirect, incidental, special, exemplary or - * consequential damages (including, but not limited to, procurement of - * substitute goods or services; loss of use, data, or profits; or business - * interruptions) however caused and on any theory of liability, whether in - * contract, strict liability, or tort (including negligence or otherwise) - * arising in any way out of the use of this driver software, even if advised - * of the possibility of such damage. - * - **************************************************************** - * This driver supports the Adaptec I2O RAID and DPT SmartRAID V I2O boards. - * - * CREDITS: - * The original linux driver was ported to Linux by Karen White while at - * Dell Computer. It was ported from Bob Pasteur's (of DPT) original - * non-Linux driver. Mark Salyzyn and Bob Pasteur consulted on the original - * driver. - * - * 2.0 version of the driver by Deanna Bonds and Mark Salyzyn. - * - * HISTORY: - * The driver was originally ported to linux version 2.0.34 - * - * V2.0 Rewrite of driver. Re-architectured based on i2o subsystem. - * This was the first full GPL version since the last version used - * i2osig headers which were not GPL. Developer Testing version. - * V2.1 Internal testing - * V2.2 First released version - * - * V2.3 - * Changes: - * Added Raptor Support - * Fixed bug causing system to hang under extreme load with - * management utilities running (removed GFP_DMA from kmalloc flags) - * - * - * V2.4 First version ready to be submitted to be embedded in the kernel - * Changes: - * Implemented suggestions from Alan Cox - * Added calculation of resid for sg layer - * Better error handling - * Added checking underflow conditions - * Added DATAPROTECT checking - * Changed error return codes - * Fixed pointer bug in bus reset routine - * Enabled hba reset from ioctls (allows a FW flash to reboot and use the new - * FW without having to reboot) - * Changed proc output - * - * TODO: - * Add 64 bit Scatter Gather when compiled on 64 bit architectures - * Add sparse lun scanning - * Add code that checks if a device that had been taken offline is - * now online (at the FW level) when test unit ready or inquiry - * command from scsi-core - * Add proc read interface - * busrescan command - * rescan command - * Add code to rescan routine that notifies scsi-core about new devices - * Add support for C-PCI (hotplug stuff) - * Add ioctl passthru error recovery - * - * NOTES: - * The DPT card optimizes the order of processing commands. Consequently, - * a command may take up to 6 minutes to complete after it has been sent - * to the board. - * - * The files dpti_ioctl.h dptsig.h osd_defs.h osd_util.h sys_info.h are part of the - * interface files for Adaptec's management routines. These define the structures used - * in the ioctls. They are written to be portable. They are hard to read, but I need - * to use them 'as is' or I can miss changes in the interface. - * - */ - diff --git a/Documentation/scsi/g_NCR5380.rst b/Documentation/scsi/g_NCR5380.rst new file mode 100644 index 000000000000..a282059fec43 --- /dev/null +++ b/Documentation/scsi/g_NCR5380.rst @@ -0,0 +1,93 @@ +.. SPDX-License-Identifier: GPL-2.0 +.. include:: <isonum.txt> + +========================================== +README file for the Linux g_NCR5380 driver +========================================== + +Copyright |copy| 1993 Drew Eckhard + +NCR53c400 extensions Copyright |copy| 1994,1995,1996 Kevin Lentin + +This file documents the NCR53c400 extensions by Kevin Lentin and some +enhancements to the NCR5380 core. + +This driver supports NCR5380 and NCR53c400 and compatible cards in port or +memory mapped modes. + +Use of an interrupt is recommended, if supported by the board, as this will +allow targets to disconnect and thereby improve SCSI bus utilization. + +If the irq parameter is 254 or is omitted entirely, the driver will probe +for the correct IRQ line automatically. If the irq parameter is 0 or 255 +then no IRQ will be used. + +The NCR53c400 does not support DMA but it does have Pseudo-DMA which is +supported by the driver. + +This driver provides some information on what it has detected in +/proc/scsi/g_NCR5380/x where x is the scsi card number as detected at boot +time. More info to come in the future. + +This driver works as a module. +When included as a module, parameters can be passed on the insmod/modprobe +command line: + + ============= =============================================================== + irq=xx[,...] the interrupt(s) + base=xx[,...] the port or base address(es) (for port or memory mapped, resp.) + card=xx[,...] card type(s): + + == ====================================== + 0 NCR5380, + 1 NCR53C400, + 2 NCR53C400A, + 3 Domex Technology Corp 3181E (DTC3181E) + 4 Hewlett Packard C2502 + == ====================================== + ============= =============================================================== + +These old-style parameters can support only one card: + + ============= ================================================= + ncr_irq=xx the interrupt + ncr_addr=xx the port or base address (for port or memory + mapped, resp.) + ncr_5380=1 to set up for a NCR5380 board + ncr_53c400=1 to set up for a NCR53C400 board + ncr_53c400a=1 to set up for a NCR53C400A board + dtc_3181e=1 to set up for a Domex Technology Corp 3181E board + hp_c2502=1 to set up for a Hewlett Packard C2502 board + ============= ================================================= + +E.g. Trantor T130B in its default configuration:: + + modprobe g_NCR5380 irq=5 base=0x350 card=1 + +or alternatively, using the old syntax:: + + modprobe g_NCR5380 ncr_irq=5 ncr_addr=0x350 ncr_53c400=1 + +E.g. a port mapped NCR5380 board, driver to probe for IRQ:: + + modprobe g_NCR5380 base=0x350 card=0 + +or alternatively:: + + modprobe g_NCR5380 ncr_addr=0x350 ncr_5380=1 + +E.g. a memory mapped NCR53C400 board with no IRQ:: + + modprobe g_NCR5380 irq=255 base=0xc8000 card=1 + +or alternatively:: + + modprobe g_NCR5380 ncr_irq=255 ncr_addr=0xc8000 ncr_53c400=1 + +E.g. two cards, DTC3181 (in non-PnP mode) at 0x240 with no IRQ +and HP C2502 at 0x300 with IRQ 7:: + + modprobe g_NCR5380 irq=0,7 base=0x240,0x300 card=3,4 + +Kevin Lentin +K.Lentin@cs.monash.edu.au diff --git a/Documentation/scsi/g_NCR5380.txt b/Documentation/scsi/g_NCR5380.txt deleted file mode 100644 index 37b1967a00a9..000000000000 --- a/Documentation/scsi/g_NCR5380.txt +++ /dev/null @@ -1,68 +0,0 @@ -README file for the Linux g_NCR5380 driver. - -(c) 1993 Drew Eckhard -NCR53c400 extensions (c) 1994,1995,1996 Kevin Lentin - -This file documents the NCR53c400 extensions by Kevin Lentin and some -enhancements to the NCR5380 core. - -This driver supports NCR5380 and NCR53c400 and compatible cards in port or -memory mapped modes. - -Use of an interrupt is recommended, if supported by the board, as this will -allow targets to disconnect and thereby improve SCSI bus utilization. - -If the irq parameter is 254 or is omitted entirely, the driver will probe -for the correct IRQ line automatically. If the irq parameter is 0 or 255 -then no IRQ will be used. - -The NCR53c400 does not support DMA but it does have Pseudo-DMA which is -supported by the driver. - -This driver provides some information on what it has detected in -/proc/scsi/g_NCR5380/x where x is the scsi card number as detected at boot -time. More info to come in the future. - -This driver works as a module. -When included as a module, parameters can be passed on the insmod/modprobe -command line: - irq=xx[,...] the interrupt(s) - base=xx[,...] the port or base address(es) (for port or memory mapped, resp.) - card=xx[,...] card type(s): - 0 = NCR5380, - 1 = NCR53C400, - 2 = NCR53C400A, - 3 = Domex Technology Corp 3181E (DTC3181E) - 4 = Hewlett Packard C2502 - -These old-style parameters can support only one card: - ncr_irq=xx the interrupt - ncr_addr=xx the port or base address (for port or memory - mapped, resp.) - ncr_5380=1 to set up for a NCR5380 board - ncr_53c400=1 to set up for a NCR53C400 board - ncr_53c400a=1 to set up for a NCR53C400A board - dtc_3181e=1 to set up for a Domex Technology Corp 3181E board - hp_c2502=1 to set up for a Hewlett Packard C2502 board - -E.g. Trantor T130B in its default configuration: -modprobe g_NCR5380 irq=5 base=0x350 card=1 -or alternatively, using the old syntax, -modprobe g_NCR5380 ncr_irq=5 ncr_addr=0x350 ncr_53c400=1 - -E.g. a port mapped NCR5380 board, driver to probe for IRQ: -modprobe g_NCR5380 base=0x350 card=0 -or alternatively, -modprobe g_NCR5380 ncr_addr=0x350 ncr_5380=1 - -E.g. a memory mapped NCR53C400 board with no IRQ: -modprobe g_NCR5380 irq=255 base=0xc8000 card=1 -or alternatively, -modprobe g_NCR5380 ncr_irq=255 ncr_addr=0xc8000 ncr_53c400=1 - -E.g. two cards, DTC3181 (in non-PnP mode) at 0x240 with no IRQ -and HP C2502 at 0x300 with IRQ 7: -modprobe g_NCR5380 irq=0,7 base=0x240,0x300 card=3,4 - -Kevin Lentin -K.Lentin@cs.monash.edu.au diff --git a/Documentation/scsi/hpsa.txt b/Documentation/scsi/hpsa.rst index 891435a72fce..340e10c6e35f 100644 --- a/Documentation/scsi/hpsa.txt +++ b/Documentation/scsi/hpsa.rst @@ -1,6 +1,8 @@ +.. SPDX-License-Identifier: GPL-2.0 +========================================= HPSA - Hewlett Packard Smart Array driver ------------------------------------------ +========================================= This file describes the hpsa SCSI driver for HP Smart Array controllers. The hpsa driver is intended to supplant the cciss driver for newer @@ -11,17 +13,17 @@ driver (for logical drives) AND a SCSI driver (for tape drives). This complexity and eliminating that complexity is one of the reasons for hpsa to exist. -Supported devices: ------------------- +Supported devices +================= -Smart Array P212 -Smart Array P410 -Smart Array P410i -Smart Array P411 -Smart Array P812 -Smart Array P712m -Smart Array P711m -StorageWorks P1210m +- Smart Array P212 +- Smart Array P410 +- Smart Array P410i +- Smart Array P411 +- Smart Array P812 +- Smart Array P712m +- Smart Array P711m +- StorageWorks P1210m Additionally, older Smart Arrays may work with the hpsa driver if the kernel boot parameter "hpsa_allow_any=1" is specified, however these are not tested @@ -35,18 +37,20 @@ mode, each command completion requires an interrupt, while with "performant mode command completions indicated by a single interrupt. HPSA specific entries in /sys ------------------------------ +============================= In addition to the generic SCSI attributes available in /sys, hpsa supports the following attributes: - HPSA specific host attributes: - ------------------------------ +HPSA specific host attributes +============================= + + :: - /sys/class/scsi_host/host*/rescan - /sys/class/scsi_host/host*/firmware_revision - /sys/class/scsi_host/host*/resettable - /sys/class/scsi_host/host*/transport_mode + /sys/class/scsi_host/host*/rescan + /sys/class/scsi_host/host*/firmware_revision + /sys/class/scsi_host/host*/resettable + /sys/class/scsi_host/host*/transport_mode the host "rescan" attribute is a write only attribute. Writing to this attribute will cause the driver to scan for new, changed, or removed devices @@ -58,7 +62,7 @@ HPSA specific entries in /sys tape drives, or entire storage boxes containing pre-configured logical drives. The "firmware_revision" attribute contains the firmware version of the Smart Array. - For example: + For example:: root@host:/sys/class/scsi_host/host4# cat firmware_revision 7.14 @@ -78,16 +82,18 @@ HPSA specific entries in /sys kexec tools to warn the user if they attempt to designate a device which is unable to honor the reset_devices kernel parameter as a dump device. - HPSA specific disk attributes: - ------------------------------ +HPSA specific disk attributes +----------------------------- + + :: - /sys/class/scsi_disk/c:b:t:l/device/unique_id - /sys/class/scsi_disk/c:b:t:l/device/raid_level - /sys/class/scsi_disk/c:b:t:l/device/lunid + /sys/class/scsi_disk/c:b:t:l/device/unique_id + /sys/class/scsi_disk/c:b:t:l/device/raid_level + /sys/class/scsi_disk/c:b:t:l/device/lunid (where c:b:t:l are the controller, bus, target and lun of the device) - For example: + For example:: root@host:/sys/class/scsi_disk/4:0:0:0/device# cat unique_id 600508B1001044395355323037570F77 @@ -96,35 +102,28 @@ HPSA specific entries in /sys root@host:/sys/class/scsi_disk/4:0:0:0/device# cat raid_level RAID 0 -HPSA specific ioctls: ---------------------- +HPSA specific ioctls +==================== For compatibility with applications written for the cciss driver, many, but not all of the ioctls supported by the cciss driver are also supported by the hpsa driver. The data structures used by these are described in include/linux/cciss_ioctl.h - CCISS_DEREGDISK - CCISS_REGNEWDISK - CCISS_REGNEWD - - The above three ioctls all do exactly the same thing, which is to cause the driver - to rescan for new devices. This does exactly the same thing as writing to the - hpsa specific host "rescan" attribute. + CCISS_DEREGDISK, CCISS_REGNEWDISK, CCISS_REGNEWD + The above three ioctls all do exactly the same thing, which is to cause the driver + to rescan for new devices. This does exactly the same thing as writing to the + hpsa specific host "rescan" attribute. CCISS_GETPCIINFO - Returns PCI domain, bus, device and function and "board ID" (PCI subsystem ID). CCISS_GETDRIVVER + Returns driver version in three bytes encoded as:: - Returns driver version in three bytes encoded as: (major_version << 16) | (minor_version << 8) | (subminor_version) - CCISS_PASSTHRU - CCISS_BIG_PASSTHRU - + CCISS_PASSTHRU, CCISS_BIG_PASSTHRU Allows "BMIC" and "CISS" commands to be passed through to the Smart Array. These are used extensively by the HP Array Configuration Utility, SNMP storage agents, etc. See cciss_vol_status at http://cciss.sf.net for some examples. - diff --git a/Documentation/scsi/hptiop.txt b/Documentation/scsi/hptiop.rst index 12ecfd308e55..23ae7ae36971 100644 --- a/Documentation/scsi/hptiop.txt +++ b/Documentation/scsi/hptiop.rst @@ -1,15 +1,25 @@ -HIGHPOINT ROCKETRAID 3xxx/4xxx ADAPTER DRIVER (hptiop) +.. SPDX-License-Identifier: GPL-2.0 +.. include:: <isonum.txt> + +====================================================== +Highpoint RocketRAID 3xxx/4xxx Adapter Driver (hptiop) +====================================================== Controller Register Map -------------------------- +----------------------- -For RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 and BAR2: +For RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 and BAR2 + ============== ================================== BAR0 offset Register + ============== ================================== 0x11C5C Link Interface IRQ Set 0x11C60 Link Interface IRQ Clear + ============== ================================== + ============== ================================== BAR2 offset Register + ============== ================================== 0x10 Inbound Message Register 0 0x14 Inbound Message Register 1 0x18 Outbound Message Register 0 @@ -21,10 +31,13 @@ For RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 0x34 Outbound Interrupt Mask Register 0x40 Inbound Queue Port 0x44 Outbound Queue Port + ============== ================================== For Intel IOP based adapters, the controller IOP is accessed via PCI BAR0: + ============== ================================== BAR0 offset Register + ============== ================================== 0x10 Inbound Message Register 0 0x14 Inbound Message Register 1 0x18 Outbound Message Register 0 @@ -36,16 +49,22 @@ For Intel IOP based adapters, the controller IOP is accessed via PCI BAR0: 0x34 Outbound Interrupt Mask Register 0x40 Inbound Queue Port 0x44 Outbound Queue Port + ============== ================================== For Marvell not Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1: + ============== ================================== BAR0 offset Register + ============== ================================== 0x20400 Inbound Doorbell Register 0x20404 Inbound Interrupt Mask Register 0x20408 Outbound Doorbell Register 0x2040C Outbound Interrupt Mask Register + ============== ================================== + ============== ================================== BAR1 offset Register + ============== ================================== 0x0 Inbound Queue Head Pointer 0x4 Inbound Queue Tail Pointer 0x8 Outbound Queue Head Pointer @@ -53,14 +72,20 @@ For Marvell not Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BA 0x10 Inbound Message Register 0x14 Outbound Message Register 0x40-0x1040 Inbound Queue - 0x1040-0x2040 Outbound Queue + 0x1040-0x2040 Outbound Queue + ============== ================================== For Marvell Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1: + ============== ================================== BAR0 offset Register + ============== ================================== 0x0 IOP configuration information. + ============== ================================== + ============== =================================================== BAR1 offset Register + ============== =================================================== 0x4000 Inbound List Base Address Low 0x4004 Inbound List Base Address High 0x4018 Inbound List Write Pointer @@ -76,10 +101,11 @@ For Marvell Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1: 0x10420 CPU to PCIe Function 0 Message A 0x10480 CPU to PCIe Function 0 Doorbell 0x10484 CPU to PCIe Function 0 Doorbell Enable + ============== =================================================== I/O Request Workflow of Not Marvell Frey ------------------------------------------- +---------------------------------------- All queued requests are handled via inbound/outbound queue port. A request packet can be allocated in either IOP or host memory. @@ -124,7 +150,7 @@ of an inbound message. I/O Request Workflow of Marvell Frey --------------------------------------- +------------------------------------ All queued requests are handled via inbound/outbound list. @@ -167,13 +193,17 @@ User-level Interface The driver exposes following sysfs attributes: + ================== === ======================== NAME R/W Description + ================== === ======================== driver-version R driver version string firmware-version R firmware version string + ================== === ======================== ----------------------------------------------------------------------------- -Copyright (C) 2006-2012 HighPoint Technologies, Inc. All Rights Reserved. + +Copyright |copy| 2006-2012 HighPoint Technologies, Inc. All Rights Reserved. This file is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -181,4 +211,5 @@ Copyright (C) 2006-2012 HighPoint Technologies, Inc. All Rights Reserved. GNU General Public License for more details. linux@highpoint-tech.com + http://www.highpoint-tech.com diff --git a/Documentation/scsi/index.rst b/Documentation/scsi/index.rst new file mode 100644 index 000000000000..7c5f5f8f614e --- /dev/null +++ b/Documentation/scsi/index.rst @@ -0,0 +1,51 @@ +.. SPDX-License-Identifier: GPL-2.0 + +==================== +Linux SCSI Subsystem +==================== + +.. toctree:: + :maxdepth: 1 + + 53c700 + aacraid + advansys + aha152x + aic79xx + aic7xxx + arcmsr_spec + bfa + bnx2fc + BusLogic + cxgb3i + dc395x + dpti + FlashPoint + g_NCR5380 + hpsa + hptiop + libsas + link_power_management_policy + lpfc + megaraid + ncr53c8xx + NinjaSCSI + ppa + qlogicfas + scsi-changer + scsi_eh + scsi_fc_transport + scsi-generic + scsi_mid_low_api + scsi-parameters + scsi + sd-parameters + smartpqi + st + sym53c500_cs + sym53c8xx_2 + tcm_qla2xxx + ufs + wd719x + + scsi_transport_srp/figures diff --git a/Documentation/scsi/libsas.txt b/Documentation/scsi/libsas.rst index 8cac6492aade..7216b5d25800 100644 --- a/Documentation/scsi/libsas.txt +++ b/Documentation/scsi/libsas.rst @@ -1,5 +1,8 @@ +.. SPDX-License-Identifier: GPL-2.0 + +========= SAS Layer ---------- +========= The SAS Layer is a management infrastructure which manages SAS LLDDs. It sits between SCSI Core and SAS LLDDs. The @@ -37,16 +40,21 @@ It will then return. Then you enable your phys to actually start OOB (at which point your driver will start calling the notify_* event callbacks). -Structure descriptions: +Structure descriptions +====================== + +``struct sas_phy`` +------------------ -struct sas_phy -------------------- Normally this is statically embedded to your driver's -phy structure: - struct my_phy { - blah; - struct sas_phy sas_phy; - bleh; - }; +phy structure:: + + struct my_phy { + blah; + struct sas_phy sas_phy; + bleh; + }; + And then all the phys are an array of my_phy in your HA struct (shown below). @@ -63,94 +71,122 @@ There is a scheme where the LLDD can RW certain fields, and the SAS layer can only read such ones, and vice versa. The idea is to avoid unnecessary locking. -enabled -- must be set (0/1) -id -- must be set [0,MAX_PHYS) -class, proto, type, role, oob_mode, linkrate -- must be set -oob_mode -- you set this when OOB has finished and then notify -the SAS Layer. - -sas_addr -- this normally points to an array holding the sas -address of the phy, possibly somewhere in your my_phy -struct. - -attached_sas_addr -- set this when you (LLDD) receive an -IDENTIFY frame or a FIS frame, _before_ notifying the SAS -layer. The idea is that sometimes the LLDD may want to fake -or provide a different SAS address on that phy/port and this -allows it to do this. At best you should copy the sas -address from the IDENTIFY frame or maybe generate a SAS -address for SATA directly attached devices. The Discover -process may later change this. - -frame_rcvd -- this is where you copy the IDENTIFY/FIS frame -when you get it; you lock, copy, set frame_rcvd_size and -unlock the lock, and then call the event. It is a pointer -since there's no way to know your hw frame size _exactly_, -so you define the actual array in your phy struct and let -this pointer point to it. You copy the frame from your -DMAable memory to that area holding the lock. - -sas_prim -- this is where primitives go when they're -received. See sas.h. Grab the lock, set the primitive, -release the lock, notify. - -port -- this points to the sas_port if the phy belongs -to a port -- the LLDD only reads this. It points to the -sas_port this phy is part of. Set by the SAS Layer. - -ha -- may be set; the SAS layer sets it anyway. - -lldd_phy -- you should set this to point to your phy so you -can find your way around faster when the SAS layer calls one -of your callbacks and passes you a phy. If the sas_phy is -embedded you can also use container_of -- whatever you -prefer. - - -struct sas_port -------------------- +enabled + - must be set (0/1) + +id + - must be set [0,MAX_PHYS)] + +class, proto, type, role, oob_mode, linkrate + - must be set + +oob_mode + - you set this when OOB has finished and then notify + the SAS Layer. + +sas_addr + - this normally points to an array holding the sas + address of the phy, possibly somewhere in your my_phy + struct. + +attached_sas_addr + - set this when you (LLDD) receive an + IDENTIFY frame or a FIS frame, _before_ notifying the SAS + layer. The idea is that sometimes the LLDD may want to fake + or provide a different SAS address on that phy/port and this + allows it to do this. At best you should copy the sas + address from the IDENTIFY frame or maybe generate a SAS + address for SATA directly attached devices. The Discover + process may later change this. + +frame_rcvd + - this is where you copy the IDENTIFY/FIS frame + when you get it; you lock, copy, set frame_rcvd_size and + unlock the lock, and then call the event. It is a pointer + since there's no way to know your hw frame size _exactly_, + so you define the actual array in your phy struct and let + this pointer point to it. You copy the frame from your + DMAable memory to that area holding the lock. + +sas_prim + - this is where primitives go when they're + received. See sas.h. Grab the lock, set the primitive, + release the lock, notify. + +port + - this points to the sas_port if the phy belongs + to a port -- the LLDD only reads this. It points to the + sas_port this phy is part of. Set by the SAS Layer. + +ha + - may be set; the SAS layer sets it anyway. + +lldd_phy + - you should set this to point to your phy so you + can find your way around faster when the SAS layer calls one + of your callbacks and passes you a phy. If the sas_phy is + embedded you can also use container_of -- whatever you + prefer. + + +``struct sas_port`` +------------------- + The LLDD doesn't set any fields of this struct -- it only reads them. They should be self explanatory. phy_mask is 32 bit, this should be enough for now, as I haven't heard of a HA having more than 8 phys. -lldd_port -- I haven't found use for that -- maybe other -LLDD who wish to have internal port representation can make -use of this. +lldd_port + - I haven't found use for that -- maybe other + LLDD who wish to have internal port representation can make + use of this. +``struct sas_ha_struct`` +------------------------ -struct sas_ha_struct -------------------- It normally is statically declared in your own LLDD -structure describing your adapter: -struct my_sas_ha { - blah; - struct sas_ha_struct sas_ha; - struct my_phy phys[MAX_PHYS]; - struct sas_port sas_ports[MAX_PHYS]; /* (1) */ - bleh; -}; +structure describing your adapter:: + + struct my_sas_ha { + blah; + struct sas_ha_struct sas_ha; + struct my_phy phys[MAX_PHYS]; + struct sas_port sas_ports[MAX_PHYS]; /* (1) */ + bleh; + }; -(1) If your LLDD doesn't have its own port representation. + (1) If your LLDD doesn't have its own port representation. What needs to be initialized (sample function given below). pcidev -sas_addr -- since the SAS layer doesn't want to mess with +^^^^^^ + +sas_addr + - since the SAS layer doesn't want to mess with memory allocation, etc, this points to statically allocated array somewhere (say in your host adapter structure) and holds the SAS address of the host adapter as given by you or the manufacturer, etc. + sas_port -sas_phy -- an array of pointers to structures. (see +^^^^^^^^ + +sas_phy + - an array of pointers to structures. (see note above on sas_addr). These must be set. See more notes below. -num_phys -- the number of phys present in the sas_phy array, + +num_phys + - the number of phys present in the sas_phy array, and the number of ports present in the sas_port array. There can be a maximum num_phys ports (one per port) so we drop the num_ports, and only use num_phys. -The event interface: +The event interface:: /* LLDD calls these to notify the class of an event. */ void (*notify_ha_event)(struct sas_ha_struct *, enum ha_event); @@ -161,7 +197,7 @@ When sas_register_ha() returns, those are set and can be called by the LLDD to notify the SAS layer of such events the SAS layer. -The port notification: +The port notification:: /* The class calls these to notify the LLDD of an event. */ void (*lldd_port_formed)(struct sas_phy *); @@ -171,7 +207,7 @@ If the LLDD wants notification when a port has been formed or deformed it sets those to a function satisfying the type. A SAS LLDD should also implement at least one of the Task -Management Functions (TMFs) described in SAM: +Management Functions (TMFs) described in SAM:: /* Task Management Functions. Must be called from process context. */ int (*lldd_abort_task)(struct sas_task *); @@ -184,7 +220,7 @@ Management Functions (TMFs) described in SAM: For more information please read SAM from T10.org. -Port and Adapter management: +Port and Adapter management:: /* Port and Adapter management */ int (*lldd_clear_nexus_port)(struct sas_port *); @@ -192,75 +228,78 @@ Port and Adapter management: A SAS LLDD should implement at least one of those. -Phy management: +Phy management:: /* Phy management */ int (*lldd_control_phy)(struct sas_phy *, enum phy_func); -lldd_ha -- set this to point to your HA struct. You can also -use container_of if you embedded it as shown above. +lldd_ha + - set this to point to your HA struct. You can also + use container_of if you embedded it as shown above. A sample initialization and registration function can look like this (called last thing from probe()) -*but* before you enable the phys to do OOB: +*but* before you enable the phys to do OOB:: -static int register_sas_ha(struct my_sas_ha *my_ha) -{ - int i; - static struct sas_phy *sas_phys[MAX_PHYS]; - static struct sas_port *sas_ports[MAX_PHYS]; + static int register_sas_ha(struct my_sas_ha *my_ha) + { + int i; + static struct sas_phy *sas_phys[MAX_PHYS]; + static struct sas_port *sas_ports[MAX_PHYS]; - my_ha->sas_ha.sas_addr = &my_ha->sas_addr[0]; + my_ha->sas_ha.sas_addr = &my_ha->sas_addr[0]; - for (i = 0; i < MAX_PHYS; i++) { - sas_phys[i] = &my_ha->phys[i].sas_phy; - sas_ports[i] = &my_ha->sas_ports[i]; - } + for (i = 0; i < MAX_PHYS; i++) { + sas_phys[i] = &my_ha->phys[i].sas_phy; + sas_ports[i] = &my_ha->sas_ports[i]; + } - my_ha->sas_ha.sas_phy = sas_phys; - my_ha->sas_ha.sas_port = sas_ports; - my_ha->sas_ha.num_phys = MAX_PHYS; + my_ha->sas_ha.sas_phy = sas_phys; + my_ha->sas_ha.sas_port = sas_ports; + my_ha->sas_ha.num_phys = MAX_PHYS; - my_ha->sas_ha.lldd_port_formed = my_port_formed; + my_ha->sas_ha.lldd_port_formed = my_port_formed; - my_ha->sas_ha.lldd_dev_found = my_dev_found; - my_ha->sas_ha.lldd_dev_gone = my_dev_gone; + my_ha->sas_ha.lldd_dev_found = my_dev_found; + my_ha->sas_ha.lldd_dev_gone = my_dev_gone; - my_ha->sas_ha.lldd_execute_task = my_execute_task; + my_ha->sas_ha.lldd_execute_task = my_execute_task; - my_ha->sas_ha.lldd_abort_task = my_abort_task; - my_ha->sas_ha.lldd_abort_task_set = my_abort_task_set; - my_ha->sas_ha.lldd_clear_aca = my_clear_aca; - my_ha->sas_ha.lldd_clear_task_set = my_clear_task_set; - my_ha->sas_ha.lldd_I_T_nexus_reset= NULL; (2) - my_ha->sas_ha.lldd_lu_reset = my_lu_reset; - my_ha->sas_ha.lldd_query_task = my_query_task; + my_ha->sas_ha.lldd_abort_task = my_abort_task; + my_ha->sas_ha.lldd_abort_task_set = my_abort_task_set; + my_ha->sas_ha.lldd_clear_aca = my_clear_aca; + my_ha->sas_ha.lldd_clear_task_set = my_clear_task_set; + my_ha->sas_ha.lldd_I_T_nexus_reset= NULL; (2) + my_ha->sas_ha.lldd_lu_reset = my_lu_reset; + my_ha->sas_ha.lldd_query_task = my_query_task; - my_ha->sas_ha.lldd_clear_nexus_port = my_clear_nexus_port; - my_ha->sas_ha.lldd_clear_nexus_ha = my_clear_nexus_ha; + my_ha->sas_ha.lldd_clear_nexus_port = my_clear_nexus_port; + my_ha->sas_ha.lldd_clear_nexus_ha = my_clear_nexus_ha; - my_ha->sas_ha.lldd_control_phy = my_control_phy; + my_ha->sas_ha.lldd_control_phy = my_control_phy; - return sas_register_ha(&my_ha->sas_ha); -} + return sas_register_ha(&my_ha->sas_ha); + } (2) SAS 1.1 does not define I_T Nexus Reset TMF. Events ------- +====== -Events are _the only way_ a SAS LLDD notifies the SAS layer +Events are **the only way** a SAS LLDD notifies the SAS layer of anything. There is no other method or way a LLDD to tell the SAS layer of anything happening internally or in the SAS domain. -Phy events: +Phy events:: + PHYE_LOSS_OF_SIGNAL, (C) PHYE_OOB_DONE, PHYE_OOB_ERROR, (C) PHYE_SPINUP_HOLD. -Port events, passed on a _phy_: +Port events, passed on a _phy_:: + PORTE_BYTES_DMAED, (M) PORTE_BROADCAST_RCVD, (E) PORTE_LINK_RESET_ERR, (C) @@ -271,6 +310,7 @@ Host Adapter event: HAE_RESET A SAS LLDD should be able to generate + - at least one event from group C (choice), - events marked M (mandatory) are mandatory (only one), - events marked E (expander) if it wants the SAS layer @@ -279,26 +319,42 @@ A SAS LLDD should be able to generate Meaning: -HAE_RESET -- when your HA got internal error and was reset. +HAE_RESET + - when your HA got internal error and was reset. + +PORTE_BYTES_DMAED + - on receiving an IDENTIFY/FIS frame + +PORTE_BROADCAST_RCVD + - on receiving a primitive + +PORTE_LINK_RESET_ERR + - timer expired, loss of signal, loss of DWS, etc. [1]_ -PORTE_BYTES_DMAED -- on receiving an IDENTIFY/FIS frame -PORTE_BROADCAST_RCVD -- on receiving a primitive -PORTE_LINK_RESET_ERR -- timer expired, loss of signal, loss -of DWS, etc. (*) -PORTE_TIMER_EVENT -- DWS reset timeout timer expired (*) -PORTE_HARD_RESET -- Hard Reset primitive received. +PORTE_TIMER_EVENT + - DWS reset timeout timer expired [1]_ -PHYE_LOSS_OF_SIGNAL -- the device is gone (*) -PHYE_OOB_DONE -- OOB went fine and oob_mode is valid -PHYE_OOB_ERROR -- Error while doing OOB, the device probably -got disconnected. (*) -PHYE_SPINUP_HOLD -- SATA is present, COMWAKE not sent. +PORTE_HARD_RESET + - Hard Reset primitive received. -(*) should set/clear the appropriate fields in the phy, - or alternatively call the inlined sas_phy_disconnected() - which is just a helper, from their tasklet. +PHYE_LOSS_OF_SIGNAL + - the device is gone [1]_ -The Execute Command SCSI RPC: +PHYE_OOB_DONE + - OOB went fine and oob_mode is valid + +PHYE_OOB_ERROR + - Error while doing OOB, the device probably + got disconnected. [1]_ + +PHYE_SPINUP_HOLD + - SATA is present, COMWAKE not sent. + +.. [1] should set/clear the appropriate fields in the phy, + or alternatively call the inlined sas_phy_disconnected() + which is just a helper, from their tasklet. + +The Execute Command SCSI RPC:: int (*lldd_execute_task)(struct sas_task *, gfp_t gfp_flags); @@ -311,23 +367,28 @@ That is, when lldd_execute_task() is called, the command go out on the transport *immediately*. There is *no* queuing of any sort and at any level in a SAS LLDD. -Returns: -SAS_QUEUE_FULL, -ENOMEM, nothing was queued; - 0, the task(s) were queued. +Returns: -struct sas_task { - dev -- the device this task is destined to - task_proto -- _one_ of enum sas_proto - scatter -- pointer to scatter gather list array - num_scatter -- number of elements in scatter - total_xfer_len -- total number of bytes expected to be transferred - data_dir -- PCI_DMA_... - task_done -- callback when the task has finished execution -}; + * -SAS_QUEUE_FULL, -ENOMEM, nothing was queued; + * 0, the task(s) were queued. -DISCOVERY ---------- +:: + + struct sas_task { + dev -- the device this task is destined to + task_proto -- _one_ of enum sas_proto + scatter -- pointer to scatter gather list array + num_scatter -- number of elements in scatter + total_xfer_len -- total number of bytes expected to be transferred + data_dir -- PCI_DMA_... + task_done -- callback when the task has finished execution + }; + +Discovery +========= The sysfs tree has the following purposes: + a) It shows you the physical layout of the SAS domain at the current time, i.e. how the domain looks in the physical world right now. @@ -336,6 +397,7 @@ The sysfs tree has the following purposes: This is a link to the tree(1) program, very useful in viewing the SAS domain: ftp://mama.indstate.edu/linux/tree/ + I expect user space applications to actually create a graphical interface of this. @@ -359,7 +421,7 @@ contents of the domain_device structure, but it never creates or destroys one. Expander management from User Space ------------------------------------ +=================================== In each expander directory in sysfs, there is a file called "smp_portal". It is a binary sysfs attribute file, which @@ -371,15 +433,23 @@ Functionality is deceptively simple: 1. Build the SMP frame you want to send. The format and layout is described in the SAS spec. Leave the CRC field equal 0. + open(2) + 2. Open the expander's SMP portal sysfs file in RW mode. + write(2) + 3. Write the frame you built in 1. + read(2) + 4. Read the amount of data you expect to receive for the frame you built. If you receive different amount of data you expected to receive, then there was some kind of error. + close(2) + All this process is shown in detail in the function do_smp_func() and its callers, in the file "expander_conf.c". diff --git a/Documentation/scsi/link_power_management_policy.txt b/Documentation/scsi/link_power_management_policy.rst index d18993d01884..64288dcf10f6 100644 --- a/Documentation/scsi/link_power_management_policy.txt +++ b/Documentation/scsi/link_power_management_policy.rst @@ -1,8 +1,15 @@ +.. SPDX-License-Identifier: GPL-2.0 + +========================== +Link Power Managent Policy +========================== + This parameter allows the user to set the link (interface) power management. There are 3 possible options: +===================== ===================================================== Value Effect ----------------------------------------------------------------------------- +===================== ===================================================== min_power Tell the controller to try to make the link use the least possible power when possible. This may sacrifice some performance due to increased latency @@ -15,5 +22,4 @@ max_performance Generally, this means no power management. Tell medium_power Tell the controller to enter a lower power state when possible, but do not enter the lowest power state, thus improving latency over min_power setting. - - +===================== ===================================================== diff --git a/Documentation/scsi/lpfc.txt b/Documentation/scsi/lpfc.rst index 5741ea8aa88a..6e217e82b9b9 100644 --- a/Documentation/scsi/lpfc.txt +++ b/Documentation/scsi/lpfc.rst @@ -1,10 +1,11 @@ +.. SPDX-License-Identifier: GPL-2.0 -LPFC Driver Release Notes: +========================= +LPFC Driver Release Notes +========================= -============================================================================= - - IMPORTANT: +.. important:: Starting in the 8.0.17 release, the driver began to be targeted strictly toward the upstream kernel. As such, we removed #ifdefs for older kernels @@ -22,9 +23,6 @@ LPFC Driver Release Notes: Please heed these dependencies.... - ******************************************************************** - - The following information is provided for additional background on the history of the driver as we push for upstream acceptance. @@ -64,6 +62,7 @@ Cable pull and temporary device Loss: Kernel Support +============== This source package is targeted for the upstream kernel only. (See notes at the top of this file). It relies on interfaces that are slowing @@ -77,7 +76,6 @@ Kernel Support Patches +======= Thankfully, at this time, patches are not needed. - - diff --git a/Documentation/scsi/megaraid.txt b/Documentation/scsi/megaraid.rst index 3c7cea51e687..22b75a86ba72 100644 --- a/Documentation/scsi/megaraid.txt +++ b/Documentation/scsi/megaraid.rst @@ -1,7 +1,10 @@ - Notes on Management Module - ~~~~~~~~~~~~~~~~~~~~~~~~~~ +.. SPDX-License-Identifier: GPL-2.0 -Overview: +========================== +Notes on Management Module +========================== + +Overview -------- Different classes of controllers from LSI Logic accept and respond to the @@ -25,28 +28,32 @@ ioctl commands. But this module is envisioned to handle all user space level interactions. So any 'proc', 'sysfs' implementations will be localized in this common module. -Credits: +Credits ------- -"Shared code in a third module, a "library module", is an acceptable -solution. modprobe automatically loads dependent modules, so users -running "modprobe driver1" or "modprobe driver2" would automatically -load the shared library module." +:: + + "Shared code in a third module, a "library module", is an acceptable + solution. modprobe automatically loads dependent modules, so users + running "modprobe driver1" or "modprobe driver2" would automatically + load the shared library module." + +- Jeff Garzik (jgarzik@pobox.com), 02.25.2004 LKML - - Jeff Garzik (jgarzik@pobox.com), 02.25.2004 LKML +:: -"As Jeff hinted, if your userspace<->driver API is consistent between -your new MPT-based RAID controllers and your existing megaraid driver, -then perhaps you need a single small helper module (lsiioctl or some -better name), loaded by both mptraid and megaraid automatically, which -handles registering the /dev/megaraid node dynamically. In this case, -both mptraid and megaraid would register with lsiioctl for each -adapter discovered, and lsiioctl would essentially be a switch, -redirecting userspace tool ioctls to the appropriate driver." + "As Jeff hinted, if your userspace<->driver API is consistent between + your new MPT-based RAID controllers and your existing megaraid driver, + then perhaps you need a single small helper module (lsiioctl or some + better name), loaded by both mptraid and megaraid automatically, which + handles registering the /dev/megaraid node dynamically. In this case, + both mptraid and megaraid would register with lsiioctl for each + adapter discovered, and lsiioctl would essentially be a switch, + redirecting userspace tool ioctls to the appropriate driver." - - Matt Domsch, (Matt_Domsch@dell.com), 02.25.2004 LKML +- Matt Domsch, (Matt_Domsch@dell.com), 02.25.2004 LKML -Design: +Design ------ The Common Management Module is implemented in megaraid_mm.[ch] files. This @@ -61,7 +68,7 @@ uioc_t. The management module converts the older ioctl packets from the older applications into uioc_t. After driver handles the uioc_t, the common module will convert that back into the old format before returning to applications. -As new applications evolve and replace the old ones, the old packet format +As new applications evolve and replace the old ones, the old packet format will be retired. Common module dedicates one uioc_t packet to each controller registered. This diff --git a/Documentation/scsi/ncr53c8xx.txt b/Documentation/scsi/ncr53c8xx.rst index 8586efff1e99..c41cec99f07c 100644 --- a/Documentation/scsi/ncr53c8xx.txt +++ b/Documentation/scsi/ncr53c8xx.rst @@ -1,106 +1,114 @@ +.. SPDX-License-Identifier: GPL-2.0 + +================================================= The Linux NCR53C8XX/SYM53C8XX drivers README file +================================================= Written by Gerard Roudier <groudier@free.fr> + 21 Rue Carnot + 95170 DEUIL LA BARRE - FRANCE 29 May 1999 -=============================================================================== - -1. Introduction -2. Supported chips and SCSI features -3. Advantages of the enhanced 896 driver - 3.1 Optimized SCSI SCRIPTS - 3.2 New features of the SYM53C896 (64 bit PCI dual LVD SCSI controller) -4. Memory mapped I/O versus normal I/O -5. Tagged command queueing -6. Parity checking -7. Profiling information -8. Control commands - 8.1 Set minimum synchronous period - 8.2 Set wide size - 8.3 Set maximum number of concurrent tagged commands - 8.4 Set order type for tagged command - 8.5 Set debug mode - 8.6 Clear profile counters - 8.7 Set flag (no_disc) - 8.8 Set verbose level - 8.9 Reset all logical units of a target - 8.10 Abort all tasks of all logical units of a target -9. Configuration parameters -10. Boot setup commands - 10.1 Syntax - 10.2 Available arguments - 10.2.1 Master parity checking - 10.2.2 Scsi parity checking - 10.2.3 Scsi disconnections - 10.2.4 Special features - 10.2.5 Ultra SCSI support - 10.2.6 Default number of tagged commands - 10.2.7 Default synchronous period factor - 10.2.8 Negotiate synchronous with all devices - 10.2.9 Verbosity level - 10.2.10 Debug mode - 10.2.11 Burst max - 10.2.12 LED support - 10.2.13 Max wide - 10.2.14 Differential mode - 10.2.15 IRQ mode - 10.2.16 Reverse probe - 10.2.17 Fix up PCI configuration space - 10.2.18 Serial NVRAM - 10.2.19 Check SCSI BUS - 10.2.20 Exclude a host from being attached - 10.2.21 Suggest a default SCSI id for hosts - 10.2.22 Enable use of IMMEDIATE ARBITRATION - 10.3 Advised boot setup commands - 10.4 PCI configuration fix-up boot option - 10.5 Serial NVRAM support boot option - 10.6 SCSI BUS checking boot option - 10.7 IMMEDIATE ARBITRATION boot option -11. Some constants and flags of the ncr53c8xx.h header file -12. Installation -13. Architecture dependent features -14. Known problems - 14.1 Tagged commands with Iomega Jaz device - 14.2 Device names change when another controller is added - 14.3 Using only 8 bit devices with a WIDE SCSI controller. - 14.4 Possible data corruption during a Memory Write and Invalidate - 14.5 IRQ sharing problems -15. SCSI problem troubleshooting - 15.1 Problem tracking - 15.2 Understanding hardware error reports -16. Synchronous transfer negotiation tables - 16.1 Synchronous timings for 53C875 and 53C860 Ultra-SCSI controllers - 16.2 Synchronous timings for fast SCSI-2 53C8XX controllers -17. Serial NVRAM support (by Richard Waltham) - 17.1 Features - 17.2 Symbios NVRAM layout - 17.3 Tekram NVRAM layout -18. Support for Big Endian - 18.1 Big Endian CPU - 18.2 NCR chip in Big Endian mode of operations -=============================================================================== +.. Contents: + + 1. Introduction + 2. Supported chips and SCSI features + 3. Advantages of the enhanced 896 driver + 3.1 Optimized SCSI SCRIPTS + 3.2 New features of the SYM53C896 (64 bit PCI dual LVD SCSI controller) + 4. Memory mapped I/O versus normal I/O + 5. Tagged command queueing + 6. Parity checking + 7. Profiling information + 8. Control commands + 8.1 Set minimum synchronous period + 8.2 Set wide size + 8.3 Set maximum number of concurrent tagged commands + 8.4 Set order type for tagged command + 8.5 Set debug mode + 8.6 Clear profile counters + 8.7 Set flag (no_disc) + 8.8 Set verbose level + 8.9 Reset all logical units of a target + 8.10 Abort all tasks of all logical units of a target + 9. Configuration parameters + 10. Boot setup commands + 10.1 Syntax + 10.2 Available arguments + 10.2.1 Master parity checking + 10.2.2 Scsi parity checking + 10.2.3 Scsi disconnections + 10.2.4 Special features + 10.2.5 Ultra SCSI support + 10.2.6 Default number of tagged commands + 10.2.7 Default synchronous period factor + 10.2.8 Negotiate synchronous with all devices + 10.2.9 Verbosity level + 10.2.10 Debug mode + 10.2.11 Burst max + 10.2.12 LED support + 10.2.13 Max wide + 10.2.14 Differential mode + 10.2.15 IRQ mode + 10.2.16 Reverse probe + 10.2.17 Fix up PCI configuration space + 10.2.18 Serial NVRAM + 10.2.19 Check SCSI BUS + 10.2.20 Exclude a host from being attached + 10.2.21 Suggest a default SCSI id for hosts + 10.2.22 Enable use of IMMEDIATE ARBITRATION + 10.3 Advised boot setup commands + 10.4 PCI configuration fix-up boot option + 10.5 Serial NVRAM support boot option + 10.6 SCSI BUS checking boot option + 10.7 IMMEDIATE ARBITRATION boot option + 11. Some constants and flags of the ncr53c8xx.h header file + 12. Installation + 13. Architecture dependent features + 14. Known problems + 14.1 Tagged commands with Iomega Jaz device + 14.2 Device names change when another controller is added + 14.3 Using only 8 bit devices with a WIDE SCSI controller. + 14.4 Possible data corruption during a Memory Write and Invalidate + 14.5 IRQ sharing problems + 15. SCSI problem troubleshooting + 15.1 Problem tracking + 15.2 Understanding hardware error reports + 16. Synchronous transfer negotiation tables + 16.1 Synchronous timings for 53C875 and 53C860 Ultra-SCSI controllers + 16.2 Synchronous timings for fast SCSI-2 53C8XX controllers + 17. Serial NVRAM support (by Richard Waltham) + 17.1 Features + 17.2 Symbios NVRAM layout + 17.3 Tekram NVRAM layout + 18. Support for Big Endian + 18.1 Big Endian CPU + 18.2 NCR chip in Big Endian mode of operations 1. Introduction +=============== -The initial Linux ncr53c8xx driver has been a port of the ncr driver from +The initial Linux ncr53c8xx driver has been a port of the ncr driver from FreeBSD that has been achieved in November 1995 by: - Gerard Roudier <groudier@free.fr> + + - Gerard Roudier <groudier@free.fr> The original driver has been written for 386bsd and FreeBSD by: - Wolfgang Stanglmeier <wolf@cologne.de> - Stefan Esser <se@mi.Uni-Koeln.de> + + - Wolfgang Stanglmeier <wolf@cologne.de> + - Stefan Esser <se@mi.Uni-Koeln.de> It is now available as a bundle of 2 drivers: -- ncr53c8xx generic driver that supports all the SYM53C8XX family including +- ncr53c8xx generic driver that supports all the SYM53C8XX family including the earliest 810 rev. 1, the latest 896 (2 channel LVD SCSI controller) and the new 895A (1 channel LVD SCSI controller). -- sym53c8xx enhanced driver (a.k.a. 896 drivers) that drops support of oldest - chips in order to gain advantage of new features, as LOAD/STORE instructions - available since the 810A and hardware phase mismatch available with the +- sym53c8xx enhanced driver (a.k.a. 896 drivers) that drops support of oldest + chips in order to gain advantage of new features, as LOAD/STORE instructions + available since the 810A and hardware phase mismatch available with the 896 and the 895A. You can find technical information about the NCR 8xx family in the @@ -109,119 +117,145 @@ Drew Eckhardt. Information about new chips is available at LSILOGIC web server: - http://www.lsilogic.com/ + - http://www.lsilogic.com/ SCSI standard documentations are available at SYMBIOS ftp server: - ftp://ftp.symbios.com/ + - ftp://ftp.symbios.com/ Useful SCSI tools written by Eric Youngdale are available at tsx-11: - ftp://tsx-11.mit.edu/pub/linux/ALPHA/scsi/scsiinfo-X.Y.tar.gz - ftp://tsx-11.mit.edu/pub/linux/ALPHA/scsi/scsidev-X.Y.tar.gz + - ftp://tsx-11.mit.edu/pub/linux/ALPHA/scsi/scsiinfo-X.Y.tar.gz + - ftp://tsx-11.mit.edu/pub/linux/ALPHA/scsi/scsidev-X.Y.tar.gz These tools are not ALPHA but quite clean and work quite well. It is essential you have the 'scsiinfo' package. This short documentation describes the features of the generic and enhanced -drivers, configuration parameters and control commands available through +drivers, configuration parameters and control commands available through the proc SCSI file system read / write operations. This driver has been tested OK with linux/i386, Linux/Alpha and Linux/PPC. Latest driver version and patches are available at: - ftp://ftp.tux.org/pub/people/gerard-roudier + - ftp://ftp.tux.org/pub/people/gerard-roudier + or - ftp://ftp.symbios.com/mirror/ftp.tux.org/pub/tux/roudier/drivers + + - ftp://ftp.symbios.com/mirror/ftp.tux.org/pub/tux/roudier/drivers I am not a native speaker of English and there are probably lots of mistakes in this README file. Any help will be welcome. 2. Supported chips and SCSI features +==================================== The following features are supported for all chips: - Synchronous negotiation - Disconnection - Tagged command queuing - SCSI parity checking - Master parity checking + - Synchronous negotiation + - Disconnection + - Tagged command queuing + - SCSI parity checking + - Master parity checking "Wide negotiation" is supported for chips that allow it. The -following table shows some characteristics of NCR 8xx family chips +following table shows some characteristics of NCR 8xx family chips and what drivers support them. - Supported by Supported by - On board the generic the enhanced -Chip SDMS BIOS Wide SCSI std. Max. sync driver driver ----- --------- ---- --------- ---------- ------------ ------------- -810 N N FAST10 10 MB/s Y N -810A N N FAST10 10 MB/s Y Y -815 Y N FAST10 10 MB/s Y N -825 Y Y FAST10 20 MB/s Y N -825A Y Y FAST10 20 MB/s Y Y -860 N N FAST20 20 MB/s Y Y -875 Y Y FAST20 40 MB/s Y Y -876 Y Y FAST20 40 MB/s Y Y -895 Y Y FAST40 80 MB/s Y Y -895A Y Y FAST40 80 MB/s Y Y -896 Y Y FAST40 80 MB/s Y Y -897 Y Y FAST40 80 MB/s Y Y -1510D Y Y FAST40 80 MB/s Y Y -1010 Y Y FAST80 160 MB/s N Y -1010_66* Y Y FAST80 160 MB/s N Y - -* Chip supports 33MHz and 66MHz PCI buses. ++--------+-----------+-----+-----------+------------+------------+------------+ +| | | | | |Supported by|Supported by| +| |On board | | | |the generic |the enhanced| +|Chip |SDMS BIOS |Wide |SCSI std. | Max. sync |driver |driver | ++--------+-----------+-----+-----------+------------+------------+------------+ +|810 | N | N | FAST10 | 10 MB/s | Y | N | ++--------+-----------+-----+-----------+------------+------------+------------+ +|810A | N | N | FAST10 | 10 MB/s | Y | Y | ++--------+-----------+-----+-----------+------------+------------+------------+ +|815 | Y | N | FAST10 | 10 MB/s | Y | N | ++--------+-----------+-----+-----------+------------+------------+------------+ +|825 | Y | Y | FAST10 | 20 MB/s | Y | N | ++--------+-----------+-----+-----------+------------+------------+------------+ +|825A | Y | Y | FAST10 | 20 MB/s | Y | Y | ++--------+-----------+-----+-----------+------------+------------+------------+ +|860 | N | N | FAST20 | 20 MB/s | Y | Y | ++--------+-----------+-----+-----------+------------+------------+------------+ +|875 | Y | Y | FAST20 | 40 MB/s | Y | Y | ++--------+-----------+-----+-----------+------------+------------+------------+ +|876 | Y | Y | FAST20 | 40 MB/s | Y | Y | ++--------+-----------+-----+-----------+------------+------------+------------+ +|895 | Y | Y | FAST40 | 80 MB/s | Y | Y | ++--------+-----------+-----+-----------+------------+------------+------------+ +|895A | Y | Y | FAST40 | 80 MB/s | Y | Y | ++--------+-----------+-----+-----------+------------+------------+------------+ +|896 | Y | Y | FAST40 | 80 MB/s | Y | Y | ++--------+-----------+-----+-----------+------------+------------+------------+ +|897 | Y | Y | FAST40 | 80 MB/s | Y | Y | ++--------+-----------+-----+-----------+------------+------------+------------+ +|1510D | Y | Y | FAST40 | 80 MB/s | Y | Y | ++--------+-----------+-----+-----------+------------+------------+------------+ +|1010 | Y | Y | FAST80 |160 MB/s | N | Y | ++--------+-----------+-----+-----------+------------+------------+------------+ +|1010_66 | Y | Y | FAST80 |160 MB/s | N | Y | +|[1]_ | | | | | | | ++--------+-----------+-----+-----------+------------+------------+------------+ + +.. [1] Chip supports 33MHz and 66MHz PCI buses. Summary of other supported features: -Module: allow to load the driver -Memory mapped I/O: increases performance -Profiling information: read operations from the proc SCSI file system -Control commands: write operations to the proc SCSI file system -Debugging information: written to syslog (expert only) -Scatter / gather -Shared interrupt -Boot setup commands -Serial NVRAM: Symbios and Tekram formats +:Module: allow to load the driver +:Memory mapped I/O: increases performance +:Profiling information: read operations from the proc SCSI file system +:Control commands: write operations to the proc SCSI file system +:Debugging information: written to syslog (expert only) +:Serial NVRAM: Symbios and Tekram formats + +- Scatter / gather +- Shared interrupt +- Boot setup commands 3. Advantages of the enhanced 896 driver +======================================== -3.1 Optimized SCSI SCRIPTS. +3.1 Optimized SCSI SCRIPTS +-------------------------- -The 810A, 825A, 875, 895, 896 and 895A support new SCSI SCRIPTS instructions -named LOAD and STORE that allow to move up to 1 DWORD from/to an IO register -to/from memory much faster that the MOVE MEMORY instruction that is supported +The 810A, 825A, 875, 895, 896 and 895A support new SCSI SCRIPTS instructions +named LOAD and STORE that allow to move up to 1 DWORD from/to an IO register +to/from memory much faster that the MOVE MEMORY instruction that is supported by the 53c7xx and 53c8xx family. -The LOAD/STORE instructions support absolute and DSA relative addressing -modes. The SCSI SCRIPTS had been entirely rewritten using LOAD/STORE instead +The LOAD/STORE instructions support absolute and DSA relative addressing +modes. The SCSI SCRIPTS had been entirely rewritten using LOAD/STORE instead of MOVE MEMORY instructions. 3.2 New features of the SYM53C896 (64 bit PCI dual LVD SCSI controller) +----------------------------------------------------------------------- -The 896 and the 895A allows handling of the phase mismatch context from -SCRIPTS (avoids the phase mismatch interrupt that stops the SCSI processor +The 896 and the 895A allows handling of the phase mismatch context from +SCRIPTS (avoids the phase mismatch interrupt that stops the SCSI processor until the C code has saved the context of the transfer). -Implementing this without using LOAD/STORE instructions would be painful +Implementing this without using LOAD/STORE instructions would be painful and I didn't even want to try it. -The 896 chip supports 64 bit PCI transactions and addressing, while the +The 896 chip supports 64 bit PCI transactions and addressing, while the 895A supports 32 bit PCI transactions and 64 bit addressing. -The SCRIPTS processor of these chips is not true 64 bit, but uses segment -registers for bit 32-63. Another interesting feature is that LOAD/STORE +The SCRIPTS processor of these chips is not true 64 bit, but uses segment +registers for bit 32-63. Another interesting feature is that LOAD/STORE instructions that address the on-chip RAM (8k) remain internal to the chip. -Due to the use of LOAD/STORE SCRIPTS instructions, this driver does not +Due to the use of LOAD/STORE SCRIPTS instructions, this driver does not support the following chips: + - SYM53C810 revision < 0x10 (16) - SYM53C815 all revisions - SYM53C825 revision < 0x10 (16) 4. Memory mapped I/O versus normal I/O +====================================== Memory mapped I/O has less latency than normal I/O. Since linux-1.3.x, memory mapped I/O is used rather than normal I/O. Memory @@ -233,17 +267,18 @@ driver to use normal I/O in all cases. 5. Tagged command queueing +========================== -Queuing more than 1 command at a time to a device allows it to perform -optimizations based on actual head positions and its mechanical +Queuing more than 1 command at a time to a device allows it to perform +optimizations based on actual head positions and its mechanical characteristics. This feature may also reduce average command latency. -In order to really gain advantage of this feature, devices must have -a reasonable cache size (No miracle is to be expected for a low-end +In order to really gain advantage of this feature, devices must have +a reasonable cache size (No miracle is to be expected for a low-end hard disk with 128 KB or less). Some known SCSI devices do not properly support tagged command queuing. -Generally, firmware revisions that fix this kind of problems are available +Generally, firmware revisions that fix this kind of problems are available at respective vendor web/ftp sites. -All I can say is that the hard disks I use on my machines behave well with +All I can say is that the hard disks I use on my machines behave well with this driver with tagged command queuing enabled: - IBM S12 0662 @@ -251,9 +286,9 @@ this driver with tagged command queuing enabled: - Quantum Atlas I - Quantum Atlas II -If your controller has NVRAM, you can configure this feature per target -from the user setup tool. The Tekram Setup program allows to tune the -maximum number of queued commands up to 32. The Symbios Setup only allows +If your controller has NVRAM, you can configure this feature per target +from the user setup tool. The Tekram Setup program allows to tune the +maximum number of queued commands up to 32. The Symbios Setup only allows to enable or disable this feature. The maximum number of simultaneous tagged commands queued to a device @@ -261,16 +296,16 @@ is currently set to 8 by default. This value is suitable for most SCSI disks. With large SCSI disks (>= 2GB, cache >= 512KB, average seek time <= 10 ms), using a larger value may give better performances. -The sym53c8xx driver supports up to 255 commands per device, and the -generic ncr53c8xx driver supports up to 64, but using more than 32 is -generally not worth-while, unless you are using a very large disk or disk -array. It is noticeable that most of recent hard disks seem not to accept -more than 64 simultaneous commands. So, using more than 64 queued commands +The sym53c8xx driver supports up to 255 commands per device, and the +generic ncr53c8xx driver supports up to 64, but using more than 32 is +generally not worth-while, unless you are using a very large disk or disk +array. It is noticeable that most of recent hard disks seem not to accept +more than 64 simultaneous commands. So, using more than 64 queued commands is probably just resource wasting. -If your controller does not have NVRAM or if it is managed by the SDMS -BIOS/SETUP, you can configure tagged queueing feature and device queue -depths from the boot command-line. For example: +If your controller does not have NVRAM or if it is managed by the SDMS +BIOS/SETUP, you can configure tagged queueing feature and device queue +depths from the boot command-line. For example:: ncr53c8xx=tags:4/t2t3q15-t4q7/t1u0q32 @@ -286,80 +321,85 @@ In some special conditions, some SCSI disk firmwares may return a QUEUE FULL status for a SCSI command. This behaviour is managed by the driver using the following heuristic: -- Each time a QUEUE FULL status is returned, tagged queue depth is reduced - to the actual number of disconnected commands. +- Each time a QUEUE FULL status is returned, tagged queue depth is reduced + to the actual number of disconnected commands. - Every 1000 successfully completed SCSI commands, if allowed by the current limit, the maximum number of queueable commands is incremented. -Since QUEUE FULL status reception and handling is resource wasting, the -driver notifies by default this problem to user by indicating the actual -number of commands used and their status, as well as its decision on the +Since QUEUE FULL status reception and handling is resource wasting, the +driver notifies by default this problem to user by indicating the actual +number of commands used and their status, as well as its decision on the device queue depth change. -The heuristic used by the driver in handling QUEUE FULL ensures that the -impact on performances is not too bad. You can get rid of the messages by +The heuristic used by the driver in handling QUEUE FULL ensures that the +impact on performances is not too bad. You can get rid of the messages by setting verbose level to zero, as follow: -1st method: boot your system using 'ncr53c8xx=verb:0' option. -2nd method: apply "setverbose 0" control command to the proc fs entry +1st method: + boot your system using 'ncr53c8xx=verb:0' option. + +2nd method: + apply "setverbose 0" control command to the proc fs entry corresponding to your controller after boot-up. 6. Parity checking +================== The driver supports SCSI parity checking and PCI bus master parity checking. These features must be enabled in order to ensure safe data transfers. However, some flawed devices or mother boards will have -problems with parity. You can disable either PCI parity or SCSI parity +problems with parity. You can disable either PCI parity or SCSI parity checking by entering appropriate options from the boot command line. (See 10: Boot setup commands). 7. Profiling information +======================== Profiling information is available through the proc SCSI file system. -Since gathering profiling information may impact performances, this -feature is disabled by default and requires a compilation configuration +Since gathering profiling information may impact performances, this +feature is disabled by default and requires a compilation configuration option to be set to Y. -The device associated with a host has the following pathname: +The device associated with a host has the following pathname:: /proc/scsi/ncr53c8xx/N (N=0,1,2 ....) -Generally, only 1 board is used on hardware configuration, and that device is: +Generally, only 1 board is used on hardware configuration, and that device is:: + /proc/scsi/ncr53c8xx/0 However, if the driver has been made as module, the number of the hosts is incremented each time the driver is loaded. -In order to display profiling information, just enter: +In order to display profiling information, just enter:: cat /proc/scsi/ncr53c8xx/0 -and you will get something like the following text: - -------------------------------------------------------- -General information: - Chip NCR53C810, device id 0x1, revision id 0x2 - IO port address 0x6000, IRQ number 10 - Using memory mapped IO at virtual address 0x282c000 - Synchronous transfer period 25, max commands per lun 4 -Profiling information: - num_trans = 18014 - num_kbytes = 671314 - num_disc = 25763 - num_break = 1673 - num_int = 1685 - num_fly = 18038 - ms_setup = 4940 - ms_data = 369940 - ms_disc = 183090 - ms_post = 1320 -------------------------------------------------------- +and you will get something like the following text:: + + General information: + Chip NCR53C810, device id 0x1, revision id 0x2 + IO port address 0x6000, IRQ number 10 + Using memory mapped IO at virtual address 0x282c000 + Synchronous transfer period 25, max commands per lun 4 + Profiling information: + num_trans = 18014 + num_kbytes = 671314 + num_disc = 25763 + num_break = 1673 + num_int = 1685 + num_fly = 18038 + ms_setup = 4940 + ms_data = 369940 + ms_disc = 183090 + ms_post = 1320 General information is easy to understand. The device ID and the revision ID identify the SCSI chip as follows: +======= ============= =========== Chip Device id Revision Id ----- --------- ----------- +======= ============= =========== 810 0x1 < 0x10 810A 0x1 >= 0x10 815 0x4 @@ -368,6 +408,7 @@ Chip Device id Revision Id 825A 0x3 >= 0x10 875 0xf 895 0xc +======= ============= =========== The profiling information is updated upon completion of SCSI commands. A data structure is allocated and zeroed when the host adapter is @@ -425,15 +466,16 @@ Due to the 1/100 second tick of the system clock, "ms_post" time may be wrong. In the example above, we got 18038 interrupts "on the fly" and only -1673 script breaks generally due to disconnections inside a segment +1673 script breaks generally due to disconnections inside a segment of the scatter list. 8. Control commands +=================== Control commands can be sent to the driver with write operations to the proc SCSI file system. The generic command syntax is the -following: +following:: echo "<verb> <parameters>" >/proc/scsi/ncr53c8xx/0 (assumes controller number is 0) @@ -444,66 +486,81 @@ apply to all targets of the SCSI chain (except the controller). Available commands: 8.1 Set minimum synchronous period factor +----------------------------------------- setsync <target> <period factor> - target: target number - period: minimum synchronous period. + :target: target number + :period: minimum synchronous period. Maximum speed = 1000/(4*period factor) except for special cases below. Specify a period of 255, to force asynchronous transfer mode. - 10 means 25 nano-seconds synchronous period - 11 means 30 nano-seconds synchronous period - 12 means 50 nano-seconds synchronous period + - 10 means 25 nano-seconds synchronous period + - 11 means 30 nano-seconds synchronous period + - 12 means 50 nano-seconds synchronous period 8.2 Set wide size +----------------- setwide <target> <size> - target: target number - size: 0=8 bits, 1=16bits + :target: target number + :size: 0=8 bits, 1=16bits 8.3 Set maximum number of concurrent tagged commands - +---------------------------------------------------- + settags <target> <tags> - target: target number - tags: number of concurrent tagged commands + :target: target number + :tags: number of concurrent tagged commands must not be greater than SCSI_NCR_MAX_TAGS (default: 8) 8.4 Set order type for tagged command +------------------------------------- setorder <order> - order: 3 possible values: - simple: use SIMPLE TAG for all operations (read and write) - ordered: use ORDERED TAG for all operations - default: use default tag type, + :order: 3 possible values: + + simple: + use SIMPLE TAG for all operations (read and write) + + ordered: + use ORDERED TAG for all operations + + default: + use default tag type, SIMPLE TAG for read operations ORDERED TAG for write operations 8.5 Set debug mode +------------------ setdebug <list of debug flags> Available debug flags: - alloc: print info about memory allocations (ccb, lcb) - queue: print info about insertions into the command start queue - result: print sense data on CHECK CONDITION status - scatter: print info about the scatter process - scripts: print info about the script binding process - tiny: print minimal debugging information - timing: print timing information of the NCR chip - nego: print information about SCSI negotiations - phase: print information on script interruptions + + ======== ======================================================== + alloc print info about memory allocations (ccb, lcb) + queue print info about insertions into the command start queue + result print sense data on CHECK CONDITION status + scatter print info about the scatter process + scripts print info about the script binding process + tiny print minimal debugging information + timing print timing information of the NCR chip + nego print information about SCSI negotiations + phase print information on script interruptions + ======== ======================================================== Use "setdebug" with no argument to reset debug flags. 8.6 Clear profile counters +-------------------------- clearprof @@ -513,7 +570,8 @@ Available commands: 8.7 Set flag (no_disc) - +---------------------- + setflag <target> <flag> target: target number @@ -523,38 +581,47 @@ Available commands: no_disc: not allow target to disconnect. Do not specify any flag in order to reset the flag. For example: - - setflag 4 + + setflag 4 will reset no_disc flag for target 4, so will allow it disconnections. - - setflag all + + setflag all will allow disconnection for all devices on the SCSI bus. 8.8 Set verbose level +--------------------- setverbose #level - The driver default verbose level is 1. This command allows to change + The driver default verbose level is 1. This command allows to change th driver verbose level after boot-up. 8.9 Reset all logical units of a target +--------------------------------------- resetdev <target> - target: target number + :target: target number + The driver will try to send a BUS DEVICE RESET message to the target. (Only supported by the SYM53C8XX driver and provided for test purpose) 8.10 Abort all tasks of all logical units of a target +----------------------------------------------------- cleardev <target> - target: target number - The driver will try to send a ABORT message to all the logical units + :target: target number + + The driver will try to send a ABORT message to all the logical units of the target. + (Only supported by the SYM53C8XX driver and provided for test purpose) 9. Configuration parameters +=========================== If the firmware of all your devices is perfect enough, all the features supported by the driver can be enabled at start-up. However, @@ -564,6 +631,7 @@ this feature after boot-up only for devices that support it safely. CONFIG_SCSI_NCR53C8XX_IOMAPPED (default answer: n) Answer "y" if you suspect your mother board to not allow memory mapped I/O. + May slow down performance a little. This option is required by Linux/PPC and is used no matter what you select here. Linux/PPC suffers no performance loss with this option since all IO is memory @@ -573,35 +641,37 @@ CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS (default answer: 8) Default tagged command queue depth. CONFIG_SCSI_NCR53C8XX_MAX_TAGS (default answer: 8) - This option allows you to specify the maximum number of tagged commands + This option allows you to specify the maximum number of tagged commands that can be queued to a device. The maximum supported value is 32. CONFIG_SCSI_NCR53C8XX_SYNC (default answer: 5) - This option allows you to specify the frequency in MHz the driver + This option allows you to specify the frequency in MHz the driver will use at boot time for synchronous data transfer negotiations. This frequency can be changed later with the "setsync" control command. 0 means "asynchronous data transfers". CONFIG_SCSI_NCR53C8XX_FORCE_SYNC_NEGO (default answer: n) Force synchronous negotiation for all SCSI-2 devices. - Some SCSI-2 devices do not report this feature in byte 7 of inquiry + + Some SCSI-2 devices do not report this feature in byte 7 of inquiry response but do support it properly (TAMARACK scanners for example). CONFIG_SCSI_NCR53C8XX_NO_DISCONNECT (default and only reasonable answer: n) If you suspect a device of yours does not properly support disconnections, - you can answer "y". Then, all SCSI devices will never disconnect the bus + you can answer "y". Then, all SCSI devices will never disconnect the bus even while performing long SCSI operations. CONFIG_SCSI_NCR53C8XX_SYMBIOS_COMPAT - Genuine SYMBIOS boards use GPIO0 in output for controller LED and GPIO3 + Genuine SYMBIOS boards use GPIO0 in output for controller LED and GPIO3 bit as a flag indicating singled-ended/differential interface. If all the boards of your system are genuine SYMBIOS boards or use BIOS and drivers from SYMBIOS, you would want to enable this option. - This option must NOT be enabled if your system has at least one 53C8XX + + This option must NOT be enabled if your system has at least one 53C8XX based scsi board with a vendor-specific BIOS. - For example, Tekram DC-390/U, DC-390/W and DC-390/F scsi controllers - use a vendor-specific BIOS and are known to not use SYMBIOS compatible - GPIO wiring. So, this option must not be enabled if your system has + For example, Tekram DC-390/U, DC-390/W and DC-390/F scsi controllers + use a vendor-specific BIOS and are known to not use SYMBIOS compatible + GPIO wiring. So, this option must not be enabled if your system has such a board installed. CONFIG_SCSI_NCR53C8XX_NVRAM_DETECT @@ -610,7 +680,7 @@ CONFIG_SCSI_NCR53C8XX_NVRAM_DETECT systems with more than one Symbios compatible controller where at least one has a serial NVRAM, or for a system with a mixture of Symbios and Tekram cards. Enables setting the boot order of host adaptors - to something other than the default order or "reverse probe" order. + to something other than the default order or "reverse probe" order. Also enables Symbios and Tekram cards to be distinguished so CONFIG_SCSI_NCR53C8XX_SYMBIOS_COMPAT may be set in a system with a mixture of Symbios and Tekram cards so the Symbios cards can make use of @@ -618,243 +688,364 @@ CONFIG_SCSI_NCR53C8XX_NVRAM_DETECT causing problems for the Tekram card(s). 10. Boot setup commands +======================= 10.1 Syntax +----------- -Setup commands can be passed to the driver either at boot time or as a +Setup commands can be passed to the driver either at boot time or as a string variable using 'insmod'. -A boot setup command for the ncr53c8xx (sym53c8xx) driver begins with the -driver name "ncr53c8xx="(sym53c8xx). The kernel syntax parser then expects -an optional list of integers separated with comma followed by an optional -list of comma-separated strings. Example of boot setup command under lilo -prompt: +A boot setup command for the ncr53c8xx (sym53c8xx) driver begins with the +driver name "ncr53c8xx="(sym53c8xx). The kernel syntax parser then expects +an optional list of integers separated with comma followed by an optional +list of comma-separated strings. Example of boot setup command under lilo +prompt:: -lilo: linux root=/dev/hda2 ncr53c8xx=tags:4,sync:10,debug:0x200 + lilo: linux root=/dev/hda2 ncr53c8xx=tags:4,sync:10,debug:0x200 - enable tagged commands, up to 4 tagged commands queued. - set synchronous negotiation speed to 10 Mega-transfers / second. - set DEBUG_NEGO flag. -Since comma seems not to be allowed when defining a string variable using -'insmod', the driver also accepts <space> as option separator. -The following command will install driver module with the same options as -above. +Since comma seems not to be allowed when defining a string variable using +'insmod', the driver also accepts <space> as option separator. +The following command will install driver module with the same options as +above:: insmod ncr53c8xx.o ncr53c8xx="tags:4 sync:10 debug:0x200" -For the moment, the integer list of arguments is discarded by the driver. +For the moment, the integer list of arguments is discarded by the driver. It will be used in the future in order to allow a per controller setup. -Each string argument must be specified as "keyword:value". Only lower-case +Each string argument must be specified as "keyword:value". Only lower-case characters and digits are allowed. -In a system that contains multiple 53C8xx adapters insmod will install the +In a system that contains multiple 53C8xx adapters insmod will install the specified driver on each adapter. To exclude a chip use the 'excl' keyword. -The sequence of commands, +The sequence of commands:: insmod sym53c8xx sym53c8xx=excl:0x1400 insmod ncr53c8xx -installs the sym53c8xx driver on all adapters except the one at IO port -address 0x1400 and then installs the ncr53c8xx driver to the adapter at IO +installs the sym53c8xx driver on all adapters except the one at IO port +address 0x1400 and then installs the ncr53c8xx driver to the adapter at IO port address 0x1400. 10.2 Available arguments +------------------------ 10.2.1 Master parity checking +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + ====== ======== mpar:y enabled mpar:n disabled + ====== ======== 10.2.2 Scsi parity checking +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + ====== ======== spar:y enabled spar:n disabled + ====== ======== 10.2.3 Scsi disconnections +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + ====== ======== disc:y enabled disc:n disabled - + ====== ======== + 10.2.4 Special features +^^^^^^^^^^^^^^^^^^^^^^^^ + Only apply to 810A, 825A, 860, 875 and 895 controllers. Have no effect with other ones. + + ======= ================================================= specf:y (or 1) enabled specf:n (or 0) disabled specf:3 enabled except Memory Write And Invalidate - The default driver setup is 'specf:3'. As a consequence, option 'specf:y' - must be specified in the boot setup command to enable Memory Write And + ======= ================================================= + + The default driver setup is 'specf:3'. As a consequence, option 'specf:y' + must be specified in the boot setup command to enable Memory Write And Invalidate. 10.2.5 Ultra SCSI support +^^^^^^^^^^^^^^^^^^^^^^^^^^ + Only apply to 860, 875, 895, 895a, 896, 1010 and 1010_66 controllers. Have no effect with other ones. + + ======= ======================== ultra:n All ultra speeds enabled ultra:2 Ultra2 enabled ultra:1 Ultra enabled ultra:0 Ultra speeds disabled + ======= ======================== 10.2.6 Default number of tagged commands +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + ======================= =============================== tags:0 (or tags:1 ) tagged command queuing disabled tags:#tags (#tags > 1) tagged command queuing enabled + ======================= =============================== + #tags will be truncated to the max queued commands configuration parameter. - This option also allows to specify a command queue depth for each device + This option also allows to specify a command queue depth for each device that support tagged command queueing. - Example: + + Example:: + ncr53c8xx=tags:10/t2t3q16-t5q24/t1u2q32 - will set devices queue depth as follow: + + will set devices queue depth as follow: + - controller #0 target #2 and target #3 -> 16 commands, - controller #0 target #5 -> 24 commands, - controller #1 target #1 logical unit #2 -> 32 commands, - all other logical units (all targets, all controllers) -> 10 commands. 10.2.7 Default synchronous period factor - sync:255 disabled (asynchronous transfer mode) - sync:#factor - #factor = 10 Ultra-2 SCSI 40 Mega-transfers / second - #factor = 11 Ultra-2 SCSI 33 Mega-transfers / second - #factor < 25 Ultra SCSI 20 Mega-transfers / second - #factor < 50 Fast SCSI-2 - - In all cases, the driver will use the minimum transfer period supported by +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +============ ======================================================== +sync:255 disabled (asynchronous transfer mode) +sync:#factor + ============ ======================================= + #factor = 10 Ultra-2 SCSI 40 Mega-transfers / second + #factor = 11 Ultra-2 SCSI 33 Mega-transfers / second + #factor < 25 Ultra SCSI 20 Mega-transfers / second + #factor < 50 Fast SCSI-2 + ============ ======================================= +============ ======================================================== + + In all cases, the driver will use the minimum transfer period supported by controllers according to NCR53C8XX chip type. 10.2.8 Negotiate synchronous with all devices +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ (force sync nego) + + ===== ========= fsn:y enabled fsn:n disabled + ===== ========= 10.2.9 Verbosity level +^^^^^^^^^^^^^^^^^^^^^^^ + + ====== ========= verb:0 minimal verb:1 normal verb:2 too much + ====== ========= 10.2.10 Debug mode - debug:0 clear debug flags - debug:#x set debug flags - #x is an integer value combining the following power-of-2 values: - DEBUG_ALLOC 0x1 - DEBUG_PHASE 0x2 - DEBUG_POLL 0x4 - DEBUG_QUEUE 0x8 - DEBUG_RESULT 0x10 - DEBUG_SCATTER 0x20 - DEBUG_SCRIPT 0x40 - DEBUG_TINY 0x80 - DEBUG_TIMING 0x100 - DEBUG_NEGO 0x200 - DEBUG_TAGS 0x400 - DEBUG_FREEZE 0x800 - DEBUG_RESTART 0x1000 - - You can play safely with DEBUG_NEGO. However, some of these flags may - generate bunches of syslog messages. +^^^^^^^^^^^^^^^^^^ + +======== ================================================================== +debug:0 clear debug flags +debug:#x set debug flags + + #x is an integer value combining the following power-of-2 values: + + ============= ====== + DEBUG_ALLOC 0x1 + DEBUG_PHASE 0x2 + DEBUG_POLL 0x4 + DEBUG_QUEUE 0x8 + DEBUG_RESULT 0x10 + DEBUG_SCATTER 0x20 + DEBUG_SCRIPT 0x40 + DEBUG_TINY 0x80 + DEBUG_TIMING 0x100 + DEBUG_NEGO 0x200 + DEBUG_TAGS 0x400 + DEBUG_FREEZE 0x800 + DEBUG_RESTART 0x1000 + ============= ====== +======== ================================================================== + + You can play safely with DEBUG_NEGO. However, some of these flags may + generate bunches of syslog messages. 10.2.11 Burst max - burst:0 burst disabled - burst:255 get burst length from initial IO register settings. - burst:#x burst enabled (1<<#x burst transfers max) - #x is an integer value which is log base 2 of the burst transfers max. - The NCR53C875 and NCR53C825A support up to 128 burst transfers (#x = 7). - Other chips only support up to 16 (#x = 4). - This is a maximum value. The driver set the burst length according to chip - and revision ids. By default the driver uses the maximum value supported - by the chip. +^^^^^^^^^^^^^^^^^ + +========= ================================================================== +burst:0 burst disabled +burst:255 get burst length from initial IO register settings. +burst:#x burst enabled (1<<#x burst transfers max) + + #x is an integer value which is log base 2 of the burst transfers + max. + + The NCR53C875 and NCR53C825A support up to 128 burst transfers + (#x = 7). + + Other chips only support up to 16 (#x = 4). + + This is a maximum value. The driver set the burst length according + to chip and revision ids. By default the driver uses the maximum + value supported by the chip. +========= ================================================================== 10.2.12 LED support +^^^^^^^^^^^^^^^^^^^ + + ===== =================== led:1 enable LED support led:0 disable LED support + ===== =================== + Donnot enable LED support if your scsi board does not use SDMS BIOS. (See 'Configuration parameters') 10.2.13 Max wide +^^^^^^^^^^^^^^^^ + + ====== =================== wide:1 wide scsi enabled wide:0 wide scsi disabled + ====== =================== + Some scsi boards use a 875 (ultra wide) and only supply narrow connectors. - If you have connected a wide device with a 50 pins to 68 pins cable + If you have connected a wide device with a 50 pins to 68 pins cable converter, any accepted wide negotiation will break further data transfers. - In such a case, using "wide:0" in the bootup command will be helpful. + In such a case, using "wide:0" in the bootup command will be helpful. 10.2.14 Differential mode +^^^^^^^^^^^^^^^^^^^^^^^^^ + + ====== ================================= diff:0 never set up diff mode diff:1 set up diff mode if BIOS set it diff:2 always set up diff mode diff:3 set diff mode if GPIO3 is not set + ====== ================================= 10.2.15 IRQ mode +^^^^^^^^^^^^^^^^ + + ========= ======================================================== irqm:0 always open drain irqm:1 same as initial settings (assumed BIOS settings) irqm:2 always totem pole irqm:0x10 driver will not use IRQF_SHARED flag when requesting irq + ========= ======================================================== (Bits 0x10 and 0x20 can be combined with hardware irq mode option) 10.2.16 Reverse probe +^^^^^^^^^^^^^^^^^^^^^ + + ========= ======================================================== revprob:n probe chip ids from the PCI configuration in this order: 810, 815, 820, 860, 875, 885, 895, 896 revprob:y probe chip ids in the reverse order. + ========= ======================================================== 10.2.17 Fix up PCI configuration space +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ pcifix:<option bits> Available option bits: - 0x0: No attempt to fix PCI configuration space registers values. - 0x1: Set PCI cache-line size register if not set. - 0x2: Set write and invalidate bit in PCI command register. - 0x4: Increase if necessary PCI latency timer according to burst max. + + === =============================================================== + 0x0 No attempt to fix PCI configuration space registers values. + 0x1 Set PCI cache-line size register if not set. + 0x2 Set write and invalidate bit in PCI command register. + 0x4 Increase if necessary PCI latency timer according to burst max. + === =============================================================== Use 'pcifix:7' in order to allow the driver to fix up all PCI features. 10.2.18 Serial NVRAM +^^^^^^^^^^^^^^^^^^^^ + + ======= ========================================= nvram:n do not look for serial NVRAM nvram:y test controllers for onboard serial NVRAM + ======= ========================================= + (alternate binary form) mvram=<bits options> + + ==== ================================================================= 0x01 look for NVRAM (equivalent to nvram=y) 0x02 ignore NVRAM "Synchronous negotiation" parameters for all devices 0x04 ignore NVRAM "Wide negotiation" parameter for all devices 0x08 ignore NVRAM "Scan at boot time" parameter for all devices 0x80 also attach controllers set to OFF in the NVRAM (sym53c8xx only) + ==== ================================================================= + +10.2.19 Check SCSI BUS +^^^^^^^^^^^^^^^^^^^^^^ -10.2.19 Check SCSI BUS buschk:<option bits> Available option bits: + + ==== ================================================ 0x0: No check. - 0x1: Check and do not attach the controller on error. + 0x1: Check and do not attach the controller on error. 0x2: Check and just warn on error. 0x4: Disable SCSI bus integrity checking. + ==== ================================================ 10.2.20 Exclude a host from being attached +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + excl=<io_address> Prevent host at a given io address from being attached. - For example 'ncr53c8xx=excl:0xb400,excl:0xc000' indicate to the + For example 'ncr53c8xx=excl:0xb400,excl:0xc000' indicate to the ncr53c8xx driver not to attach hosts at address 0xb400 and 0xc000. 10.2.21 Suggest a default SCSI id for hosts +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + ========== ========================================== hostid:255 no id suggested. - hostid:#x (0 < x < 7) x suggested for hosts SCSI id. + hostid:#x (0 < x < 7) x suggested for hosts SCSI id. + ========== ========================================== - If a host SCSI id is available from the NVRAM, the driver will ignore - any value suggested as boot option. Otherwise, if a suggested value - different from 255 has been supplied, it will use it. Otherwise, it will - try to deduce the value previously set in the hardware and use value + If a host SCSI id is available from the NVRAM, the driver will ignore + any value suggested as boot option. Otherwise, if a suggested value + different from 255 has been supplied, it will use it. Otherwise, it will + try to deduce the value previously set in the hardware and use value 7 if the hardware value is zero. 10.2.22 Enable use of IMMEDIATE ARBITRATION +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + (only supported by the sym53c8xx driver. See 10.7 for more details) - iarb:0 do not use this feature. - iarb:#x use this feature according to bit fields as follow: - bit 0 (1) : enable IARB each time the initiator has been reselected - when it arbitrated for the SCSI BUS. - (#x >> 4) : maximum number of successive settings of IARB if the initiator - win arbitration and it has other commands to send to a device. +======= ================================================================= +iarb:0 do not use this feature. +iarb:#x use this feature according to bit fields as follow: + + ========= ======================================================= + bit 0 (1) enable IARB each time the initiator has been reselected + when it arbitrated for the SCSI BUS. + (#x >> 4) maximum number of successive settings of IARB if the + initiator win arbitration and it has other commands + to send to a device. + ========= ======================================================= +======= ================================================================= Boot fail safe safe:y load the following assumed fail safe initial setup + ======================== ====================== ========== master parity disabled mpar:n scsi parity enabled spar:y disconnections not allowed disc:n @@ -876,189 +1067,222 @@ Boot fail safe irq mode from BIOS settings irqm:1 SCSI BUS check do not attach on error buschk:1 immediate arbitration disabled iarb:0 + ======================== ====================== ========== 10.3 Advised boot setup commands +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -If the driver has been configured with default options, the equivalent -boot setup is: +If the driver has been configured with default options, the equivalent +boot setup is:: ncr53c8xx=mpar:y,spar:y,disc:y,specf:3,fsn:n,ultra:2,fsn:n,revprob:n,verb:1\ tags:0,sync:50,debug:0,burst:7,led:0,wide:1,settle:2,diff:0,irqm:0 For an installation diskette or a safe but not fast system, -boot setup can be: +boot setup can be:: ncr53c8xx=safe:y,mpar:y,disc:y ncr53c8xx=safe:y,disc:y ncr53c8xx=safe:y,mpar:y ncr53c8xx=safe:y -My personal system works flawlessly with the following equivalent setup: +My personal system works flawlessly with the following equivalent setup:: ncr53c8xx=mpar:y,spar:y,disc:y,specf:1,fsn:n,ultra:2,fsn:n,revprob:n,verb:1\ tags:32,sync:12,debug:0,burst:7,led:1,wide:1,settle:2,diff:0,irqm:0 -The driver prints its actual setup when verbosity level is 2. You can try -"ncr53c8xx=verb:2" to get the "static" setup of the driver, or add "verb:2" -to your boot setup command in order to check the actual setup the driver is +The driver prints its actual setup when verbosity level is 2. You can try +"ncr53c8xx=verb:2" to get the "static" setup of the driver, or add "verb:2" +to your boot setup command in order to check the actual setup the driver is using. 10.4 PCI configuration fix-up boot option +----------------------------------------- pcifix:<option bits> Available option bits: - 0x1: Set PCI cache-line size register if not set. - 0x2: Set write and invalidate bit in PCI command register. + + === ===================================================== + 0x1 Set PCI cache-line size register if not set. + 0x2 Set write and invalidate bit in PCI command register. + === ===================================================== Use 'pcifix:3' in order to allow the driver to fix both PCI features. -These options only apply to new SYMBIOS chips 810A, 825A, 860, 875 +These options only apply to new SYMBIOS chips 810A, 825A, 860, 875 and 895 and are only supported for Pentium and 486 class processors. -Recent SYMBIOS 53C8XX scsi processors are able to use PCI read multiple -and PCI write and invalidate commands. These features require the -cache line size register to be properly set in the PCI configuration -space of the chips. On the other hand, chips will use PCI write and -invalidate commands only if the corresponding bit is set to 1 in the +Recent SYMBIOS 53C8XX scsi processors are able to use PCI read multiple +and PCI write and invalidate commands. These features require the +cache line size register to be properly set in the PCI configuration +space of the chips. On the other hand, chips will use PCI write and +invalidate commands only if the corresponding bit is set to 1 in the PCI command register. -Not all PCI bioses set the PCI cache line register and the PCI write and +Not all PCI bioses set the PCI cache line register and the PCI write and invalidate bit in the PCI configuration space of 53C8XX chips. -Optimized PCI accesses may be broken for some PCI/memory controllers or +Optimized PCI accesses may be broken for some PCI/memory controllers or make problems with some PCI boards. This fix-up worked flawlessly on my previous system. (MB Triton HX / 53C875 / 53C810A) -I use these options at my own risks as you will do if you decide to +I use these options at my own risks as you will do if you decide to use them too. 10.5 Serial NVRAM support boot option +------------------------------------- +======= ========================================= nvram:n do not look for serial NVRAM nvram:y test controllers for onboard serial NVRAM +======= ========================================= -This option can also been entered as an hexadecimal value that allows -to control what information the driver will get from the NVRAM and what +This option can also been entered as an hexadecimal value that allows +to control what information the driver will get from the NVRAM and what information it will ignore. For details see '17. Serial NVRAM support'. -When this option is enabled, the driver tries to detect all boards using +When this option is enabled, the driver tries to detect all boards using a Serial NVRAM. This memory is used to hold user set up parameters. -The parameters the driver is able to get from the NVRAM depend on the +The parameters the driver is able to get from the NVRAM depend on the data format used, as follow: - Tekram format Symbios format -General and host parameters - Boot order N Y - Host SCSI ID Y Y - SCSI parity checking Y Y - Verbose boot messages N Y -SCSI devices parameters - Synchronous transfer speed Y Y - Wide 16 / Narrow Y Y - Tagged Command Queuing enabled Y Y - Disconnections enabled Y Y - Scan at boot time N Y - -In order to speed up the system boot, for each device configured without -the "scan at boot time" option, the driver forces an error on the ++-------------------------------+------------------+--------------+ +| |Tekram format |Symbios format| ++-------------------------------+------------------+--------------+ +|General and host parameters | | | ++-------------------------------+------------------+--------------+ +| * Boot order | N | Y | ++-------------------------------+------------------+--------------+ +| * Host SCSI ID | Y | Y | ++-------------------------------+------------------+--------------+ +| * SCSI parity checking | Y | Y | ++-------------------------------+------------------+--------------+ +| * Verbose boot messages | N | Y | ++-------------------------------+------------------+--------------+ +|SCSI devices parameters | ++-------------------------------+------------------+--------------+ +| * Synchronous transfer speed | Y | Y | ++-------------------------------+------------------+--------------+ +| * Wide 16 / Narrow | Y | Y | ++-------------------------------+------------------+--------------+ +| * Tagged Command Queuing | Y | Y | +| enabled | | | ++-------------------------------+------------------+--------------+ +| * Disconnections enabled | Y | Y | ++-------------------------------+------------------+--------------+ +| * Scan at boot time | N | Y | ++-------------------------------+------------------+--------------+ + +In order to speed up the system boot, for each device configured without +the "scan at boot time" option, the driver forces an error on the first TEST UNIT READY command received for this device. -Some SDMS BIOS revisions seem to be unable to boot cleanly with very fast -hard disks. In such a situation you cannot configure the NVRAM with +Some SDMS BIOS revisions seem to be unable to boot cleanly with very fast +hard disks. In such a situation you cannot configure the NVRAM with optimized parameters value. -The 'nvram' boot option can be entered in hexadecimal form in order +The 'nvram' boot option can be entered in hexadecimal form in order to ignore some options configured in the NVRAM, as follow: mvram=<bits options> + + ==== ================================================================= 0x01 look for NVRAM (equivalent to nvram=y) 0x02 ignore NVRAM "Synchronous negotiation" parameters for all devices 0x04 ignore NVRAM "Wide negotiation" parameter for all devices 0x08 ignore NVRAM "Scan at boot time" parameter for all devices 0x80 also attach controllers set to OFF in the NVRAM (sym53c8xx only) + ==== ================================================================= -Option 0x80 is only supported by the sym53c8xx driver and is disabled by -default. Result is that, by default (option not set), the sym53c8xx driver +Option 0x80 is only supported by the sym53c8xx driver and is disabled by +default. Result is that, by default (option not set), the sym53c8xx driver will not attach controllers set to OFF in the NVRAM. -The ncr53c8xx always tries to attach all the controllers. Option 0x80 has -not been added to the ncr53c8xx driver, since it has been reported to -confuse users who use this driver since a long time. If you desire a -controller not to be attached by the ncr53c8xx driver at Linux boot, you +The ncr53c8xx always tries to attach all the controllers. Option 0x80 has +not been added to the ncr53c8xx driver, since it has been reported to +confuse users who use this driver since a long time. If you desire a +controller not to be attached by the ncr53c8xx driver at Linux boot, you must use the 'excl' driver boot option. 10.6 SCSI BUS checking boot option. +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -When this option is set to a non-zero value, the driver checks SCSI lines +When this option is set to a non-zero value, the driver checks SCSI lines logic state, 100 micro-seconds after having asserted the SCSI RESET line. The driver just reads SCSI lines and checks all lines read FALSE except RESET. -Since SCSI devices shall release the BUS at most 800 nano-seconds after SCSI +Since SCSI devices shall release the BUS at most 800 nano-seconds after SCSI RESET has been asserted, any signal to TRUE may indicate a SCSI BUS problem. Unfortunately, the following common SCSI BUS problems are not detected: + - Only 1 terminator installed. - Misplaced terminators. - Bad quality terminators. -On the other hand, either bad cabling, broken devices, not conformant + +On the other hand, either bad cabling, broken devices, not conformant devices, ... may cause a SCSI signal to be wrong when te driver reads it. 10.7 IMMEDIATE ARBITRATION boot option +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This option is only supported by the SYM53C8XX driver (not by the NCR53C8XX). -SYMBIOS 53C8XX chips are able to arbitrate for the SCSI BUS as soon as they -have detected an expected disconnection (BUS FREE PHASE). For this process -to be started, bit 1 of SCNTL1 IO register must be set when the chip is +SYMBIOS 53C8XX chips are able to arbitrate for the SCSI BUS as soon as they +have detected an expected disconnection (BUS FREE PHASE). For this process +to be started, bit 1 of SCNTL1 IO register must be set when the chip is connected to the SCSI BUS. -When this feature has been enabled for the current connection, the chip has -every chance to win arbitration if only devices with lower priority are -competing for the SCSI BUS. By the way, when the chip is using SCSI id 7, +When this feature has been enabled for the current connection, the chip has +every chance to win arbitration if only devices with lower priority are +competing for the SCSI BUS. By the way, when the chip is using SCSI id 7, then it will for sure win the next SCSI BUS arbitration. -Since, there is no way to know what devices are trying to arbitrate for the +Since, there is no way to know what devices are trying to arbitrate for the BUS, using this feature can be extremely unfair. So, you are not advised -to enable it, or at most enable this feature for the case the chip lost +to enable it, or at most enable this feature for the case the chip lost the previous arbitration (boot option 'iarb:1'). This feature has the following advantages: a) Allow the initiator with ID 7 to win arbitration when it wants so. -b) Overlap at least 4 micro-seconds of arbitration time with the execution - of SCRIPTS that deal with the end of the current connection and that +b) Overlap at least 4 micro-seconds of arbitration time with the execution + of SCRIPTS that deal with the end of the current connection and that starts the next job. -Hmmm... But (a) may just prevent other devices from reselecting the initiator, -and delay data transfers or status/completions, and (b) may just waste +Hmmm... But (a) may just prevent other devices from reselecting the initiator, +and delay data transfers or status/completions, and (b) may just waste SCSI BUS bandwidth if the SCRIPTS execution lasts more than 4 micro-seconds. -The use of IARB needs the SCSI_NCR_IARB_SUPPORT option to have been defined -at compile time and the 'iarb' boot option to have been set to a non zero -value at boot time. It is not that useful for real work, but can be used -to stress SCSI devices or for some applications that can gain advantage of -it. By the way, if you experience badnesses like 'unexpected disconnections', -'bad reselections', etc... when using IARB on heavy IO load, you should not -be surprised, because force-feeding anything and blocking its arse at the +The use of IARB needs the SCSI_NCR_IARB_SUPPORT option to have been defined +at compile time and the 'iarb' boot option to have been set to a non zero +value at boot time. It is not that useful for real work, but can be used +to stress SCSI devices or for some applications that can gain advantage of +it. By the way, if you experience badnesses like 'unexpected disconnections', +'bad reselections', etc... when using IARB on heavy IO load, you should not +be surprised, because force-feeding anything and blocking its arse at the same time cannot work for a long time. :-)) 11. Some constants and flags of the ncr53c8xx.h header file +=========================================================== Some of these are defined from the configuration parameters. To change other "defines", you must edit the header file. Do that only if you know what you are doing. SCSI_NCR_SETUP_SPECIAL_FEATURES (default: defined) - If defined, the driver will enable some special features according + If defined, the driver will enable some special features according to chip and revision id. - For 810A, 860, 825A, 875 and 895 scsi chips, this option enables - support of features that reduce load of PCI bus and memory accesses - during scsi transfer processing: burst op-code fetch, read multiple, - read line, prefetch, cache line, write and invalidate, + + For 810A, 860, 825A, 875 and 895 scsi chips, this option enables + support of features that reduce load of PCI bus and memory accesses + during scsi transfer processing: burst op-code fetch, read multiple, + read line, prefetch, cache line, write and invalidate, burst 128 (875 only), large dma fifo (875 only), offset 16 (875 only). - Can be changed by the following boot setup command: + Can be changed by the following boot setup command:: + ncr53c8xx=specf:n SCSI_NCR_IOMAPPED (default: not defined) @@ -1066,22 +1290,26 @@ SCSI_NCR_IOMAPPED (default: not defined) SCSI_NCR_SHARE_IRQ (default: defined) If defined, request shared IRQ. - + SCSI_NCR_MAX_TAGS (default: 8) Maximum number of simultaneous tagged commands to a device. + Can be changed by "settags <target> <maxtags>" SCSI_NCR_SETUP_DEFAULT_SYNC (default: 50) - Transfer period factor the driver will use at boot time for synchronous + Transfer period factor the driver will use at boot time for synchronous negotiation. 0 means asynchronous. + Can be changed by "setsync <target> <period factor>" SCSI_NCR_SETUP_DEFAULT_TAGS (default: 8) Default number of simultaneous tagged commands to a device. + < 1 means tagged command queuing disabled at start-up. SCSI_NCR_ALWAYS_SIMPLE_TAG (default: defined) Use SIMPLE TAG for read and write commands. + Can be changed by "setorder <ordered|simple|default>" SCSI_NCR_SETUP_DISCONNECTION (default: defined) @@ -1089,6 +1317,7 @@ SCSI_NCR_SETUP_DISCONNECTION (default: defined) SCSI_NCR_SETUP_FORCE_SYNC_NEGO (default: not defined) If defined, synchronous negotiation is tried for all SCSI-2 devices. + Can be changed by "setsync <target> <period>" SCSI_NCR_SETUP_MASTER_PARITY (default: defined) @@ -1115,6 +1344,7 @@ SCSI_NCR_SETTLE_TIME (default: 2) SCSI_NCR_TIMEOUT_ALERT (default: 3) If a pending command will time out after this amount of seconds, an ordered tag is used for the next command. + Avoids timeouts for unordered tagged commands. SCSI_NCR_CAN_QUEUE (default: 7*SCSI_NCR_MAX_TAGS) @@ -1131,34 +1361,38 @@ SCSI_NCR_MAX_LUN (default: 8) 12. Installation +================ This driver is part of the linux kernel distribution. -Driver files are located in the sub-directory "drivers/scsi" of the +Driver files are located in the sub-directory "drivers/scsi" of the kernel source tree. -Driver files: +Driver files:: README.ncr53c8xx : this file ChangeLog.ncr53c8xx : change log ncr53c8xx.h : definitions ncr53c8xx.c : the driver code -New driver versions are made available separately in order to allow testing -changes and new features prior to including them into the linux kernel -distribution. The following URL provides information on latest available -patches: +New driver versions are made available separately in order to allow testing +changes and new features prior to including them into the linux kernel +distribution. The following URL provides information on latest available +patches: ftp://ftp.tux.org/pub/people/gerard-roudier/README -13. Architecture dependent features. +13. Architecture dependent features +=================================== <Not yet written> 14. Known problems +================== 14.1 Tagged commands with Iomega Jaz device +------------------------------------------- I have not tried this device, however it has been reported to me the following: This device is capable of Tagged command queuing. However @@ -1170,14 +1404,15 @@ other problem that may appear is timeouts. The only way to avoid timeouts seems to edit linux/drivers/scsi/sd.c and to increase the current timeout values. -14.2 Device names change when another controller is added. +14.2 Device names change when another controller is added +--------------------------------------------------------- -When you add a new NCR53C8XX chip based controller to a system that already -has one or more controllers of this family, it may happen that the order -the driver registers them to the kernel causes problems due to device +When you add a new NCR53C8XX chip based controller to a system that already +has one or more controllers of this family, it may happen that the order +the driver registers them to the kernel causes problems due to device name changes. -When at least one controller uses NvRAM, SDMS BIOS version 4 allows you to -define the order the BIOS will scan the scsi boards. The driver attaches +When at least one controller uses NvRAM, SDMS BIOS version 4 allows you to +define the order the BIOS will scan the scsi boards. The driver attaches controllers according to BIOS information if NvRAM detect option is set. If your controllers do not have NvRAM, you can: @@ -1187,52 +1422,58 @@ If your controllers do not have NvRAM, you can: - Make appropriate changes in the fstab. - Use the 'scsidev' tool from Eric Youngdale. -14.3 Using only 8 bit devices with a WIDE SCSI controller. +14.3 Using only 8 bit devices with a WIDE SCSI controller +--------------------------------------------------------- -When only 8 bit NARROW devices are connected to a 16 bit WIDE SCSI controller, +When only 8 bit NARROW devices are connected to a 16 bit WIDE SCSI controller, you must ensure that lines of the wide part of the SCSI BUS are pulled-up. -This can be achieved by ENABLING the WIDE TERMINATOR portion of the SCSI +This can be achieved by ENABLING the WIDE TERMINATOR portion of the SCSI controller card. + The TYAN 1365 documentation revision 1.2 is not correct about such settings. (page 10, figure 3.3). 14.4 Possible data corruption during a Memory Write and Invalidate +------------------------------------------------------------------ This problem is described in SYMBIOS DEL 397, Part Number 69-039241, ITEM 4. -In some complex situations, 53C875 chips revision <= 3 may start a PCI +In some complex situations, 53C875 chips revision <= 3 may start a PCI Write and Invalidate Command at a not cache-line-aligned 4 DWORDS boundary. This is only possible when Cache Line Size is 8 DWORDS or greater. -Pentium systems use a 8 DWORDS cache line size and so are concerned by +Pentium systems use a 8 DWORDS cache line size and so are concerned by this chip bug, unlike i486 systems that use a 4 DWORDS cache line size. -When this situation occurs, the chip may complete the Write and Invalidate -command after having only filled part of the last cache line involved in +When this situation occurs, the chip may complete the Write and Invalidate +command after having only filled part of the last cache line involved in the transfer, leaving to data corruption the remainder of this cache line. -Not using Write And Invalidate obviously gets rid of this chip bug, and so +Not using Write And Invalidate obviously gets rid of this chip bug, and so it is now the default setting of the driver. -However, for people like me who want to enable this feature, I have added -part of a work-around suggested by SYMBIOS. This work-around resets the -addressing logic when the DATA IN phase is entered and so prevents the bug -from being triggered for the first SCSI MOVE of the phase. This work-around +However, for people like me who want to enable this feature, I have added +part of a work-around suggested by SYMBIOS. This work-around resets the +addressing logic when the DATA IN phase is entered and so prevents the bug +from being triggered for the first SCSI MOVE of the phase. This work-around should be enough according to the following: -The only driver internal data structure that is greater than 8 DWORDS and -that is moved by the SCRIPTS processor is the 'CCB header' that contains -the context of the SCSI transfer. This data structure is aligned on 8 DWORDS -boundary (Pentium Cache Line Size), and so is immune to this chip bug, at +The only driver internal data structure that is greater than 8 DWORDS and +that is moved by the SCRIPTS processor is the 'CCB header' that contains +the context of the SCSI transfer. This data structure is aligned on 8 DWORDS +boundary (Pentium Cache Line Size), and so is immune to this chip bug, at least on Pentium systems. -But the conditions of this bug can be met when a SCSI read command is + +But the conditions of this bug can be met when a SCSI read command is performed using a buffer that is 4 DWORDS but not cache-line aligned. -This cannot happen under Linux when scatter/gather lists are used since -they only refer to system buffers that are well aligned. So, a work around -may only be needed under Linux when a scatter/gather list is not used and +This cannot happen under Linux when scatter/gather lists are used since +they only refer to system buffers that are well aligned. So, a work around +may only be needed under Linux when a scatter/gather list is not used and when the SCSI DATA IN phase is reentered after a phase mismatch. 15. SCSI problem troubleshooting +================================ 15.1 Problem tracking +--------------------- Most SCSI problems are due to a non conformant SCSI bus or to buggy devices. If unfortunately you have SCSI problems, you can check the @@ -1267,193 +1508,286 @@ tagged commands queuing. Try to enable one feature at a time with control commands. For example: -- echo "setsync all 25" >/proc/scsi/ncr53c8xx/0 - Will enable fast synchronous data transfer negotiation for all targets. +:: + + echo "setsync all 25" >/proc/scsi/ncr53c8xx/0 + +Will enable fast synchronous data transfer negotiation for all targets. + +:: -- echo "setflag 3" >/proc/scsi/ncr53c8xx/0 - Will reset flags (no_disc) for target 3, and so will allow it to disconnect - the SCSI Bus. + echo "setflag 3" >/proc/scsi/ncr53c8xx/0 -- echo "settags 3 8" >/proc/scsi/ncr53c8xx/0 - Will enable tagged command queuing for target 3 if that device supports it. +Will reset flags (no_disc) for target 3, and so will allow it to disconnect +the SCSI Bus. -Once you have found the device and the feature that cause problems, just +:: + + echo "settags 3 8" >/proc/scsi/ncr53c8xx/0 + +Will enable tagged command queuing for target 3 if that device supports it. + +Once you have found the device and the feature that cause problems, just disable that feature for that device. 15.2 Understanding hardware error reports +----------------------------------------- -When the driver detects an unexpected error condition, it may display a -message of the following pattern. +When the driver detects an unexpected error condition, it may display a +message of the following pattern:: -sym53c876-0:1: ERROR (0:48) (1-21-65) (f/95) @ (script 7c0:19000000). -sym53c876-0: script cmd = 19000000 -sym53c876-0: regdump: da 10 80 95 47 0f 01 07 75 01 81 21 80 01 09 00. + sym53c876-0:1: ERROR (0:48) (1-21-65) (f/95) @ (script 7c0:19000000). + sym53c876-0: script cmd = 19000000 + sym53c876-0: regdump: da 10 80 95 47 0f 01 07 75 01 81 21 80 01 09 00. -Some fields in such a message may help you understand the cause of the -problem, as follows: +Some fields in such a message may help you understand the cause of the +problem, as follows:: -sym53c876-0:1: ERROR (0:48) (1-21-65) (f/95) @ (script 7c0:19000000). -............A.........B.C....D.E..F....G.H.......I.....J...K....... + sym53c876-0:1: ERROR (0:48) (1-21-65) (f/95) @ (script 7c0:19000000). + ............A.........B.C....D.E..F....G.H.......I.....J...K....... Field A : target number. - SCSI ID of the device the controller was talking with at the moment the + SCSI ID of the device the controller was talking with at the moment the error occurs. Field B : DSTAT io register (DMA STATUS) - Bit 0x40 : MDPE Master Data Parity Error + ======== ============================================================= + Bit 0x40 MDPE Master Data Parity Error Data parity error detected on the PCI BUS. - Bit 0x20 : BF Bus Fault + Bit 0x20 BF Bus Fault PCI bus fault condition detected - Bit 0x01 : IID Illegal Instruction Detected - Set by the chip when it detects an Illegal Instruction format + Bit 0x01 IID Illegal Instruction Detected + Set by the chip when it detects an Illegal Instruction format on some condition that makes an instruction illegal. - Bit 0x80 : DFE Dma Fifo Empty + Bit 0x80 DFE Dma Fifo Empty Pure status bit that does not indicate an error. - If the reported DSTAT value contains a combination of MDPE (0x40), + ======== ============================================================= + + If the reported DSTAT value contains a combination of MDPE (0x40), BF (0x20), then the cause may be likely due to a PCI BUS problem. Field C : SIST io register (SCSI Interrupt Status) - Bit 0x08 : SGE SCSI GROSS ERROR - Indicates that the chip detected a severe error condition + ======== ================================================================== + Bit 0x08 SGE SCSI GROSS ERROR + Indicates that the chip detected a severe error condition on the SCSI BUS that prevents the SCSI protocol from functioning properly. - Bit 0x04 : UDC Unexpected Disconnection - Indicates that the device released the SCSI BUS when the chip - was not expecting this to happen. A device may behave so to - indicate the SCSI initiator that an error condition not reportable using the SCSI protocol has occurred. - Bit 0x02 : RST SCSI BUS Reset - Generally SCSI targets do not reset the SCSI BUS, although any + Bit 0x04 UDC Unexpected Disconnection + Indicates that the device released the SCSI BUS when the chip + was not expecting this to happen. A device may behave so to + indicate the SCSI initiator that an error condition not reportable + using the SCSI protocol has occurred. + Bit 0x02 RST SCSI BUS Reset + Generally SCSI targets do not reset the SCSI BUS, although any device on the BUS can reset it at any time. - Bit 0x01 : PAR Parity + Bit 0x01 PAR Parity SCSI parity error detected. - On a faulty SCSI BUS, any error condition among SGE (0x08), UDC (0x04) and - PAR (0x01) may be detected by the chip. If your SCSI system sometimes - encounters such error conditions, especially SCSI GROSS ERROR, then a SCSI + ======== ================================================================== + + On a faulty SCSI BUS, any error condition among SGE (0x08), UDC (0x04) and + PAR (0x01) may be detected by the chip. If your SCSI system sometimes + encounters such error conditions, especially SCSI GROSS ERROR, then a SCSI BUS problem is likely the cause of these errors. -For fields D,E,F,G and H, you may look into the sym53c8xx_defs.h file +For fields D,E,F,G and H, you may look into the sym53c8xx_defs.h file that contains some minimal comments on IO register bits. + Field D : SOCL Scsi Output Control Latch - This register reflects the state of the SCSI control lines the + This register reflects the state of the SCSI control lines the chip want to drive or compare against. + Field E : SBCL Scsi Bus Control Lines Actual value of control lines on the SCSI BUS. + Field F : SBDL Scsi Bus Data Lines Actual value of data lines on the SCSI BUS. + Field G : SXFER SCSI Transfer - Contains the setting of the Synchronous Period for output and + Contains the setting of the Synchronous Period for output and the current Synchronous offset (offset 0 means asynchronous). + Field H : SCNTL3 Scsi Control Register 3 - Contains the setting of timing values for both asynchronous and - synchronous data transfers. + Contains the setting of timing values for both asynchronous and + synchronous data transfers. -Understanding Fields I, J, K and dumps requires to have good knowledge of +Understanding Fields I, J, K and dumps requires to have good knowledge of SCSI standards, chip cores functionnals and internal driver data structures. -You are not required to decode and understand them, unless you want to help +You are not required to decode and understand them, unless you want to help maintain the driver code. 16. Synchronous transfer negotiation tables +=========================================== Tables below have been created by calling the routine the driver uses for synchronisation negotiation timing calculation and chip setting. -The first table corresponds to Ultra chips 53875 and 53C860 with 80 MHz +The first table corresponds to Ultra chips 53875 and 53C860 with 80 MHz clock and 5 clock divisors. -The second one has been calculated by setting the scsi clock to 40 Mhz -and using 4 clock divisors and so applies to all NCR53C8XX chips in fast +The second one has been calculated by setting the scsi clock to 40 Mhz +and using 4 clock divisors and so applies to all NCR53C8XX chips in fast SCSI-2 mode. Periods are in nano-seconds and speeds are in Mega-transfers per second. -1 Mega-transfers/second means 1 MB/s with 8 bits SCSI and 2 MB/s with +1 Mega-transfers/second means 1 MB/s with 8 bits SCSI and 2 MB/s with Wide16 SCSI. 16.1 Synchronous timings for 53C895, 53C875 and 53C860 SCSI controllers - ---------------------------------------------- - Negotiated NCR settings - Factor Period Speed Period Speed - ------ ------ ------ ------ ------ - 10 25 40.000 25 40.000 (53C895 only) - 11 30.2 33.112 31.25 32.000 (53C895 only) - 12 50 20.000 50 20.000 - 13 52 19.230 62 16.000 - 14 56 17.857 62 16.000 - 15 60 16.666 62 16.000 - 16 64 15.625 75 13.333 - 17 68 14.705 75 13.333 - 18 72 13.888 75 13.333 - 19 76 13.157 87 11.428 - 20 80 12.500 87 11.428 - 21 84 11.904 87 11.428 - 22 88 11.363 93 10.666 - 23 92 10.869 93 10.666 - 24 96 10.416 100 10.000 - 25 100 10.000 100 10.000 - 26 104 9.615 112 8.888 - 27 108 9.259 112 8.888 - 28 112 8.928 112 8.888 - 29 116 8.620 125 8.000 - 30 120 8.333 125 8.000 - 31 124 8.064 125 8.000 - 32 128 7.812 131 7.619 - 33 132 7.575 150 6.666 - 34 136 7.352 150 6.666 - 35 140 7.142 150 6.666 - 36 144 6.944 150 6.666 - 37 148 6.756 150 6.666 - 38 152 6.578 175 5.714 - 39 156 6.410 175 5.714 - 40 160 6.250 175 5.714 - 41 164 6.097 175 5.714 - 42 168 5.952 175 5.714 - 43 172 5.813 175 5.714 - 44 176 5.681 187 5.333 - 45 180 5.555 187 5.333 - 46 184 5.434 187 5.333 - 47 188 5.319 200 5.000 - 48 192 5.208 200 5.000 - 49 196 5.102 200 5.000 - ++-----------------------------+--------+-------+--------------+ +|Negotiated |NCR settings | | ++-------+--------+------------+--------+-------+ | +|Factor |Period |Speed |Period |Speed | | ++-------+--------+------------+--------+-------+--------------+ +|10 | 25 |40.000 | 25 |40.000 | (53C895 only)| ++-------+--------+------------+--------+-------+--------------+ +|11 | 30.2 |33.112 | 31.25 |32.000 | (53C895 only)| ++-------+--------+------------+--------+-------+--------------+ +|12 | 50 |20.000 | 50 |20.000 | | ++-------+--------+------------+--------+-------+--------------+ +|13 | 52 |19.230 | 62 |16.000 | | ++-------+--------+------------+--------+-------+--------------+ +|14 | 56 |17.857 | 62 |16.000 | | ++-------+--------+------------+--------+-------+--------------+ +|15 | 60 |16.666 | 62 |16.000 | | ++-------+--------+------------+--------+-------+--------------+ +|16 | 64 |15.625 | 75 |13.333 | | ++-------+--------+------------+--------+-------+--------------+ +|17 | 68 |14.705 | 75 |13.333 | | ++-------+--------+------------+--------+-------+--------------+ +|18 | 72 |13.888 | 75 |13.333 | | ++-------+--------+------------+--------+-------+--------------+ +|19 | 76 |13.157 | 87 |11.428 | | ++-------+--------+------------+--------+-------+--------------+ +|20 | 80 |12.500 | 87 |11.428 | | ++-------+--------+------------+--------+-------+--------------+ +|21 | 84 |11.904 | 87 |11.428 | | ++-------+--------+------------+--------+-------+--------------+ +|22 | 88 |11.363 | 93 |10.666 | | ++-------+--------+------------+--------+-------+--------------+ +|23 | 92 |10.869 | 93 |10.666 | | ++-------+--------+------------+--------+-------+--------------+ +|24 | 96 |10.416 |100 |10.000 | | ++-------+--------+------------+--------+-------+--------------+ +|25 |100 |10.000 |100 |10.000 | | ++-------+--------+------------+--------+-------+--------------+ +|26 |104 | 9.615 |112 | 8.888 | | ++-------+--------+------------+--------+-------+--------------+ +|27 |108 | 9.259 |112 | 8.888 | | ++-------+--------+------------+--------+-------+--------------+ +|28 |112 | 8.928 |112 | 8.888 | | ++-------+--------+------------+--------+-------+--------------+ +|29 |116 | 8.620 |125 | 8.000 | | ++-------+--------+------------+--------+-------+--------------+ +|30 |120 | 8.333 |125 | 8.000 | | ++-------+--------+------------+--------+-------+--------------+ +|31 |124 | 8.064 |125 | 8.000 | | ++-------+--------+------------+--------+-------+--------------+ +|32 |128 | 7.812 |131 | 7.619 | | ++-------+--------+------------+--------+-------+--------------+ +|33 |132 | 7.575 |150 | 6.666 | | ++-------+--------+------------+--------+-------+--------------+ +|34 |136 | 7.352 |150 | 6.666 | | ++-------+--------+------------+--------+-------+--------------+ +|35 |140 | 7.142 |150 | 6.666 | | ++-------+--------+------------+--------+-------+--------------+ +|36 |144 | 6.944 |150 | 6.666 | | ++-------+--------+------------+--------+-------+--------------+ +|37 |148 | 6.756 |150 | 6.666 | | ++-------+--------+------------+--------+-------+--------------+ +|38 |152 | 6.578 |175 | 5.714 | | ++-------+--------+------------+--------+-------+--------------+ +|39 |156 | 6.410 |175 | 5.714 | | ++-------+--------+------------+--------+-------+--------------+ +|40 |160 | 6.250 |175 | 5.714 | | ++-------+--------+------------+--------+-------+--------------+ +|41 |164 | 6.097 |175 | 5.714 | | ++-------+--------+------------+--------+-------+--------------+ +|42 |168 | 5.952 |175 | 5.714 | | ++-------+--------+------------+--------+-------+--------------+ +|43 |172 | 5.813 |175 | 5.714 | | ++-------+--------+------------+--------+-------+--------------+ +|44 |176 | 5.681 |187 | 5.333 | | ++-------+--------+------------+--------+-------+--------------+ +|45 |180 | 5.555 |187 | 5.333 | | ++-------+--------+------------+--------+-------+--------------+ +|46 |184 | 5.434 |187 | 5.333 | | ++-------+--------+------------+--------+-------+--------------+ +|47 |188 | 5.319 |200 | 5.000 | | ++-------+--------+------------+--------+-------+--------------+ +|48 |192 | 5.208 |200 | 5.000 | | ++-------+--------+------------+--------+-------+--------------+ +|49 |196 | 5.102 |200 | 5.000 | | ++-------+--------+------------+--------+-------+--------------+ 16.2 Synchronous timings for fast SCSI-2 53C8XX controllers - ---------------------------------------------- - Negotiated NCR settings - Factor Period Speed Period Speed - ------ ------ ------ ------ ------ - 25 100 10.000 100 10.000 - 26 104 9.615 125 8.000 - 27 108 9.259 125 8.000 - 28 112 8.928 125 8.000 - 29 116 8.620 125 8.000 - 30 120 8.333 125 8.000 - 31 124 8.064 125 8.000 - 32 128 7.812 131 7.619 - 33 132 7.575 150 6.666 - 34 136 7.352 150 6.666 - 35 140 7.142 150 6.666 - 36 144 6.944 150 6.666 - 37 148 6.756 150 6.666 - 38 152 6.578 175 5.714 - 39 156 6.410 175 5.714 - 40 160 6.250 175 5.714 - 41 164 6.097 175 5.714 - 42 168 5.952 175 5.714 - 43 172 5.813 175 5.714 - 44 176 5.681 187 5.333 - 45 180 5.555 187 5.333 - 46 184 5.434 187 5.333 - 47 188 5.319 200 5.000 - 48 192 5.208 200 5.000 - 49 196 5.102 200 5.000 - - -17. Serial NVRAM (added by Richard Waltham: dormouse@farsrobt.demon.co.uk) ++-----------------------------+----------------+ +|Negotiated |NCR settings | ++-------+--------+------------+--------+-------+ +|Factor |Period |Speed |Period |Speed | ++-------+--------+------------+--------+-------+ +|25 |100 |10.000 |100 |10.000 | ++-------+--------+------------+--------+-------+ +|26 |104 |9.615 |125 | 8.000 | ++-------+--------+------------+--------+-------+ +|27 |108 |9.259 |125 | 8.000 | ++-------+--------+------------+--------+-------+ +|28 |112 |8.928 |125 | 8.000 | ++-------+--------+------------+--------+-------+ +|29 |116 |8.620 |125 | 8.000 | ++-------+--------+------------+--------+-------+ +|30 |120 |8.333 |125 | 8.000 | ++-------+--------+------------+--------+-------+ +|31 |124 |8.064 |125 | 8.000 | ++-------+--------+------------+--------+-------+ +|32 |128 |7.812 |131 | 7.619 | ++-------+--------+------------+--------+-------+ +|33 |132 |7.575 |150 | 6.666 | ++-------+--------+------------+--------+-------+ +|34 |136 |7.352 |150 | 6.666 | ++-------+--------+------------+--------+-------+ +|35 |140 |7.142 |150 | 6.666 | ++-------+--------+------------+--------+-------+ +|36 |144 |6.944 |150 | 6.666 | ++-------+--------+------------+--------+-------+ +|37 |148 |6.756 |150 | 6.666 | ++-------+--------+------------+--------+-------+ +|38 |152 |6.578 |175 | 5.714 | ++-------+--------+------------+--------+-------+ +|39 |156 |6.410 |175 | 5.714 | ++-------+--------+------------+--------+-------+ +|40 |160 |6.250 |175 | 5.714 | ++-------+--------+------------+--------+-------+ +|41 |164 |6.097 |175 | 5.714 | ++-------+--------+------------+--------+-------+ +|42 |168 |5.952 |175 | 5.714 | ++-------+--------+------------+--------+-------+ +|43 |172 |5.813 |175 | 5.714 | ++-------+--------+------------+--------+-------+ +|44 |176 |5.681 |187 | 5.333 | ++-------+--------+------------+--------+-------+ +|45 |180 |5.555 |187 | 5.333 | ++-------+--------+------------+--------+-------+ +|46 |184 |5.434 |187 | 5.333 | ++-------+--------+------------+--------+-------+ +|47 |188 |5.319 |200 | 5.000 | ++-------+--------+------------+--------+-------+ +|48 |192 |5.208 |200 | 5.000 | ++-------+--------+------------+--------+-------+ +|49 |196 |5.102 |200 | 5.000 | ++-------+--------+------------+--------+-------+ + + +17. Serial NVRAM +================ + +(added by Richard Waltham: dormouse@farsrobt.demon.co.uk) 17.1 Features +------------- Enabling serial NVRAM support enables detection of the serial NVRAM included -on Symbios and some Symbios compatible host adaptors, and Tekram boards. The -serial NVRAM is used by Symbios and Tekram to hold set up parameters for the +on Symbios and some Symbios compatible host adaptors, and Tekram boards. The +serial NVRAM is used by Symbios and Tekram to hold set up parameters for the host adaptor and its attached drives. The Symbios NVRAM also holds data on the boot order of host adaptors in a @@ -1467,10 +1801,10 @@ NVRAM boot order settings can do this as well as change the order the same types of cards are scanned in, something "reverse probe" cannot do. Tekram boards using Symbios chips, DC390W/F/U, which have NVRAM are detected -and this is used to distinguish between Symbios compatible and Tekram host +and this is used to distinguish between Symbios compatible and Tekram host adaptors. This is used to disable the Symbios compatible "diff" setting -incorrectly set on Tekram boards if the CONFIG_SCSI_53C8XX_SYMBIOS_COMPAT -configuration parameter is set enabling both Symbios and Tekram boards to be +incorrectly set on Tekram boards if the CONFIG_SCSI_53C8XX_SYMBIOS_COMPAT +configuration parameter is set enabling both Symbios and Tekram boards to be used together with the Symbios cards using all their features, including "diff" support. ("led pin" support for Symbios compatible cards can remain enabled when using Tekram cards. It does nothing useful for Tekram host @@ -1478,71 +1812,76 @@ adaptors but does not cause problems either.) 17.2 Symbios NVRAM layout +------------------------- + +typical data at NVRAM address 0x100 (53c810a NVRAM):: + + 00 00 + 64 01 + 8e 0b + + 00 30 00 00 00 00 07 00 00 00 00 00 00 00 07 04 10 04 00 00 + + 04 00 0f 00 00 10 00 50 00 00 01 00 00 62 + 04 00 03 00 00 10 00 58 00 00 01 00 00 63 + 04 00 01 00 00 10 00 48 00 00 01 00 00 61 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + + fe fe + 00 00 + 00 00 -typical data at NVRAM address 0x100 (53c810a NVRAM) ------------------------------------------------------------ -00 00 -64 01 -8e 0b - -00 30 00 00 00 00 07 00 00 00 00 00 00 00 07 04 10 04 00 00 - -04 00 0f 00 00 10 00 50 00 00 01 00 00 62 -04 00 03 00 00 10 00 58 00 00 01 00 00 63 -04 00 01 00 00 10 00 48 00 00 01 00 00 61 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 - -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 - -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 - -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 - -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 - -fe fe -00 00 -00 00 ------------------------------------------------------------ NVRAM layout details -NVRAM Address 0x000-0x0ff not used - 0x100-0x26f initialised data - 0x270-0x7ff not used +============= ================ +NVRAM Address +============= ================ +0x000-0x0ff not used +0x100-0x26f initialised data +0x270-0x7ff not used +============= ================ -general layout +general layout:: header - 6 bytes, data - 356 bytes (checksum is byte sum of this data) @@ -1550,7 +1889,7 @@ general layout --- total 368 bytes -data area layout +data area layout:: controller set up - 20 bytes boot configuration - 56 bytes (4x14 bytes) @@ -1559,121 +1898,126 @@ data area layout --- total 356 bytes ------------------------------------------------------------ -header - -00 00 - ?? start marker -64 01 - byte count (lsb/msb excludes header/trailer) -8e 0b - checksum (lsb/msb excludes header/trailer) ------------------------------------------------------------ -controller set up - -00 30 00 00 00 00 07 00 00 00 00 00 00 00 07 04 10 04 00 00 - | | | | - | | | -- host ID - | | | - | | --Removable Media Support - | | 0x00 = none - | | 0x01 = Bootable Device - | | 0x02 = All with Media - | | - | --flag bits 2 - | 0x00000001= scan order hi->low - | (default 0x00 - scan low->hi) - --flag bits 1 - 0x00000001 scam enable - 0x00000010 parity enable - 0x00000100 verbose boot msgs +header:: + + 00 00 - ?? start marker + 64 01 - byte count (lsb/msb excludes header/trailer) + 8e 0b - checksum (lsb/msb excludes header/trailer) + +controller set up:: + + 00 30 00 00 00 00 07 00 00 00 00 00 00 00 07 04 10 04 00 00 + | | | | + | | | -- host ID + | | | + | | --Removable Media Support + | | 0x00 = none + | | 0x01 = Bootable Device + | | 0x02 = All with Media + | | + | --flag bits 2 + | 0x00000001= scan order hi->low + | (default 0x00 - scan low->hi) + --flag bits 1 + 0x00000001 scam enable + 0x00000010 parity enable + 0x00000100 verbose boot msgs remaining bytes unknown - they do not appear to change in my current set up for any of the controllers. default set up is identical for 53c810a and 53c875 NVRAM (Removable Media added Symbios BIOS version 4.09) ------------------------------------------------------------ + boot configuration -boot order set by order of the devices in this table +boot order set by order of the devices in this table:: -04 00 0f 00 00 10 00 50 00 00 01 00 00 62 -- 1st controller -04 00 03 00 00 10 00 58 00 00 01 00 00 63 2nd controller -04 00 01 00 00 10 00 48 00 00 01 00 00 61 3rd controller -00 00 00 00 00 00 00 00 00 00 00 00 00 00 4th controller - | | | | | | | | - | | | | | | ---- PCI io port adr - | | | | | --0x01 init/scan at boot time - | | | | --PCI device/function number (0xdddddfff) - | | ----- ?? PCI vendor ID (lsb/msb) - ----PCI device ID (lsb/msb) + 04 00 0f 00 00 10 00 50 00 00 01 00 00 62 -- 1st controller + 04 00 03 00 00 10 00 58 00 00 01 00 00 63 2nd controller + 04 00 01 00 00 10 00 48 00 00 01 00 00 61 3rd controller + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4th controller + | | | | | | | | + | | | | | | ---- PCI io port adr + | | | | | --0x01 init/scan at boot time + | | | | --PCI device/function number (0xdddddfff) + | | ----- ?? PCI vendor ID (lsb/msb) + ----PCI device ID (lsb/msb) -?? use of this data is a guess but seems reasonable + ?? use of this data is a guess but seems reasonable remaining bytes unknown - they do not appear to change in my current set up default set up is identical for 53c810a and 53c875 NVRAM ------------------------------------------------------------ -device set up (up to 16 devices - includes controller) - -0f 00 08 08 64 00 0a 00 - id 0 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 - -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 - id 15 - | | | | | | - | | | | ----timeout (lsb/msb) - | | | --synch period (0x?? 40 Mtrans/sec- fast 40) (probably 0x28) - | | | (0x30 20 Mtrans/sec- fast 20) - | | | (0x64 10 Mtrans/sec- fast ) - | | | (0xc8 5 Mtrans/sec) - | | | (0x00 asynchronous) - | | -- ?? max sync offset (0x08 in NVRAM on 53c810a) - | | (0x10 in NVRAM on 53c875) - | --device bus width (0x08 narrow) - | (0x10 16 bit wide) - --flag bits - 0x00000001 - disconnect enabled - 0x00000010 - scan at boot time - 0x00000100 - scan luns - 0x00001000 - queue tags enabled +-------------------------------------------------------- + +device set up (up to 16 devices - includes controller):: + + 0f 00 08 08 64 00 0a 00 - id 0 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 - id 15 + | | | | | | + | | | | ----timeout (lsb/msb) + | | | --synch period (0x?? 40 Mtrans/sec- fast 40) (probably 0x28) + | | | (0x30 20 Mtrans/sec- fast 20) + | | | (0x64 10 Mtrans/sec- fast ) + | | | (0xc8 5 Mtrans/sec) + | | | (0x00 asynchronous) + | | -- ?? max sync offset (0x08 in NVRAM on 53c810a) + | | (0x10 in NVRAM on 53c875) + | --device bus width (0x08 narrow) + | (0x10 16 bit wide) + --flag bits + 0x00000001 - disconnect enabled + 0x00000010 - scan at boot time + 0x00000100 - scan luns + 0x00001000 - queue tags enabled remaining bytes unknown - they do not appear to change in my current set up -?? use of this data is a guess but seems reasonable +?? use of this data is a guess but seems reasonable (but it could be max bus width) default set up for 53c810a NVRAM -default set up for 53c875 NVRAM - bus width - 0x10 +default set up for 53c875 NVRAM + + - bus width - 0x10 - sync offset ? - 0x10 - sync period - 0x30 ------------------------------------------------------------ + ?? spare device space (32 bit bus ??) -00 00 00 00 00 00 00 00 (19x8bytes) -. -. -00 00 00 00 00 00 00 00 +:: + + 00 00 00 00 00 00 00 00 (19x8bytes) + . + . + 00 00 00 00 00 00 00 00 default set up is identical for 53c810a and 53c875 NVRAM ------------------------------------------------------------ -trailer +-------------------------------------------------------- -fe fe - ? end marker ? -00 00 -00 00 +trailer:: + + fe fe - ? end marker ? + 00 00 + 00 00 default set up is identical for 53c810a and 53c875 NVRAM ----------------------------------------------------------- @@ -1681,51 +2025,52 @@ default set up is identical for 53c810a and 53c875 NVRAM 17.3 Tekram NVRAM layout +------------------------ nvram 64x16 (1024 bit) -Drive settings - -Drive ID 0-15 (addr 0x0yyyy0 = device setup, yyyy = ID) - (addr 0x0yyyy1 = 0x0000) - - x x x x x x x x x x x x x x x x - | | | | | | | | | - | | | | | | | | ----- parity check 0 - off - | | | | | | | | 1 - on - | | | | | | | | - | | | | | | | ------- sync neg 0 - off - | | | | | | | 1 - on - | | | | | | | - | | | | | | --------- disconnect 0 - off - | | | | | | 1 - on - | | | | | | - | | | | | ----------- start cmd 0 - off - | | | | | 1 - on - | | | | | - | | | | -------------- tagged cmds 0 - off - | | | | 1 - on - | | | | - | | | ---------------- wide neg 0 - off - | | | 1 - on - | | | - --------------------------- sync rate 0 - 10.0 Mtrans/sec - 1 - 8.0 - 2 - 6.6 - 3 - 5.7 - 4 - 5.0 - 5 - 4.0 - 6 - 3.0 - 7 - 2.0 - 7 - 2.0 - 8 - 20.0 - 9 - 16.7 - a - 13.9 - b - 11.9 +Drive settings:: + + Drive ID 0-15 (addr 0x0yyyy0 = device setup, yyyy = ID) + (addr 0x0yyyy1 = 0x0000) + + x x x x x x x x x x x x x x x x + | | | | | | | | | + | | | | | | | | ----- parity check 0 - off + | | | | | | | | 1 - on + | | | | | | | | + | | | | | | | ------- sync neg 0 - off + | | | | | | | 1 - on + | | | | | | | + | | | | | | --------- disconnect 0 - off + | | | | | | 1 - on + | | | | | | + | | | | | ----------- start cmd 0 - off + | | | | | 1 - on + | | | | | + | | | | -------------- tagged cmds 0 - off + | | | | 1 - on + | | | | + | | | ---------------- wide neg 0 - off + | | | 1 - on + | | | + --------------------------- sync rate 0 - 10.0 Mtrans/sec + 1 - 8.0 + 2 - 6.6 + 3 - 5.7 + 4 - 5.0 + 5 - 4.0 + 6 - 3.0 + 7 - 2.0 + 7 - 2.0 + 8 - 20.0 + 9 - 16.7 + a - 13.9 + b - 11.9 Global settings -Host flags 0 (addr 0x100000, 32) +Host flags 0 (addr 0x100000, 32):: x x x x x x x x x x x x x x x x | | | | | | | | | | | | @@ -1733,7 +2078,7 @@ Host flags 0 (addr 0x100000, 32) | | | | | | | | | | | | | | | ----------------------- support for 0 - off | | | | | | | > 2 drives 1 - on - | | | | | | | + | | | | | | | | | | | | | ------------------------- support drives 0 - off | | | | | | > 1Gbytes 1 - on | | | | | | @@ -1753,10 +2098,10 @@ Host flags 0 (addr 0x100000, 32) as BIOS dev 1 - boot device 2 - all -Host flags 1 (addr 0x100001, 33) +Host flags 1 (addr 0x100001, 33):: x x x x x x x x x x x x x x x x - | | | | | | + | | | | | | | | | --------- boot delay 0 - 3 sec | | | 1 - 5 | | | 2 - 10 @@ -1771,7 +2116,7 @@ Host flags 1 (addr 0x100001, 33) 3 - 16 4 - 32 -Host flags 2 (addr 0x100010, 34) +Host flags 2 (addr 0x100010, 34):: x x x x x x x x x x x x x x x x | @@ -1784,41 +2129,41 @@ checksum = 0x1234 - (sum addr 0-63) ---------------------------------------------------------------------------- -default nvram data: +default nvram data:: -0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 -0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 -0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 -0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 + 0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 + 0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 + 0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 + 0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 -0x0f07 0x0400 0x0001 0x0000 0x0000 0x0000 0x0000 0x0000 -0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 -0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 -0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0xfbbc + 0x0f07 0x0400 0x0001 0x0000 0x0000 0x0000 0x0000 0x0000 + 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 + 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 + 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0xfbbc 18. Support for Big Endian +========================== The PCI local bus has been primarily designed for x86 architecture. -As a consequence, PCI devices generally expect DWORDS using little endian +As a consequence, PCI devices generally expect DWORDS using little endian byte ordering. 18.1 Big Endian CPU +------------------- -In order to support NCR chips on a Big Endian architecture the driver has to -perform byte reordering each time it is needed. This feature has been -added to the driver by Cort <cort@cs.nmt.edu> and is available in driver -version 2.5 and later ones. For the moment Big Endian support has only +In order to support NCR chips on a Big Endian architecture the driver has to +perform byte reordering each time it is needed. This feature has been +added to the driver by Cort <cort@cs.nmt.edu> and is available in driver +version 2.5 and later ones. For the moment Big Endian support has only been tested on Linux/PPC (PowerPC). 18.2 NCR chip in Big Endian mode of operations +---------------------------------------------- -It can be read in SYMBIOS documentation that some chips support a special +It can be read in SYMBIOS documentation that some chips support a special Big Endian mode, on paper: 53C815, 53C825A, 53C875, 53C875N, 53C895. -This mode of operations is not software-selectable, but needs pin named -BigLit to be pulled-up. Using this mode, most of byte reorderings should +This mode of operations is not software-selectable, but needs pin named +BigLit to be pulled-up. Using this mode, most of byte reorderings should be avoided when the driver is running on a Big Endian CPU. Driver version 2.5 is also, in theory, ready for this feature. - -=============================================================================== -End of NCR53C8XX driver README file diff --git a/Documentation/scsi/ppa.rst b/Documentation/scsi/ppa.rst new file mode 100644 index 000000000000..5fe3859a6892 --- /dev/null +++ b/Documentation/scsi/ppa.rst @@ -0,0 +1,18 @@ +.. SPDX-License-Identifier: GPL-2.0 + +====================================== +Terse where to get ZIP Drive help info +====================================== + +General Iomega ZIP drive page for Linux: +http://web.archive.org/web/%2E/http://www.torque.net/~campbell/ + +Driver archive for old drivers: +http://web.archive.org/web/%2E/http://www.torque.net/~campbell/ppa + +Linux Parport page (parallel port) +http://web.archive.org/web/%2E/http://www.torque.net/parport/ + +Email list for Linux Parport +linux-parport@torque.net + diff --git a/Documentation/scsi/ppa.txt b/Documentation/scsi/ppa.txt deleted file mode 100644 index 05ff47dbe8d1..000000000000 --- a/Documentation/scsi/ppa.txt +++ /dev/null @@ -1,14 +0,0 @@ --------- Terse where to get ZIP Drive help info -------- - -General Iomega ZIP drive page for Linux: -http://web.archive.org/web/*/http://www.torque.net/~campbell/ - -Driver archive for old drivers: -http://web.archive.org/web/*/http://www.torque.net/~campbell/ppa - -Linux Parport page (parallel port) -http://web.archive.org/web/*/http://www.torque.net/parport/ - -Email list for Linux Parport -linux-parport@torque.net - diff --git a/Documentation/scsi/qlogicfas.txt b/Documentation/scsi/qlogicfas.rst index c211d827fef2..b17f1b3676c3 100644 --- a/Documentation/scsi/qlogicfas.txt +++ b/Documentation/scsi/qlogicfas.rst @@ -1,3 +1,8 @@ +.. SPDX-License-Identifier: GPL-2.0 + +================================= +Qlogic FASXXX Family Driver Notes +================================= This driver supports the Qlogic FASXXX family of chips. This driver only works with the ISA, VLB, and PCMCIA versions of the Qlogic @@ -16,7 +21,8 @@ is provided by the qla1280 driver. Nor does it support the PCI-Basic, which is supported by the 'am53c974' driver. -PCMCIA SUPPORT +PCMCIA Support +============== This currently only works if the card is enabled first from DOS. This means you will have to load your socket and card services, and @@ -31,7 +37,8 @@ it from configuring the card. I am working with the PCMCIA group to make it more flexible, but that may take a while. -ALL CARDS +All Cards +========= The top of the qlogic.c file has a number of defines that controls configuration. As shipped, it provides a balance between speed and @@ -46,7 +53,8 @@ command or something. It comes up faster if this is set to zero, and if you have reliable hardware and connections it may be more useful to not reset things. -SOME TROUBLESHOOTING TIPS +Some Troubleshooting Tips +========================= Make sure it works properly under DOS. You should also do an initial FDISK on a new drive if you want partitions. @@ -54,7 +62,8 @@ on a new drive if you want partitions. Don't enable all the speedups first. If anything is wrong, they will make any problem worse. -IMPORTANT +Important +========= The best way to test if your cables, termination, etc. are good is to copy a very big file (e.g. a doublespace container file, or a very diff --git a/Documentation/scsi/scsi-changer.txt b/Documentation/scsi/scsi-changer.rst index ade046ea7c17..ab60e7e61a6c 100644 --- a/Documentation/scsi/scsi-changer.txt +++ b/Documentation/scsi/scsi-changer.rst @@ -1,4 +1,6 @@ +.. SPDX-License-Identifier: GPL-2.0 +======================================== README for the SCSI media changer driver ======================================== @@ -28,15 +30,17 @@ The SCSI changer model is complex, compared to - for example - IDE-CD changers. But it allows to handle nearly all possible cases. It knows 4 different types of changer elements: - media transport - this one shuffles around the media, i.e. the + =============== ================================================== + media transport this one shuffles around the media, i.e. the transport arm. Also known as "picker". - storage - a slot which can hold a media. - import/export - the same as above, but is accessible from outside, + storage a slot which can hold a media. + import/export the same as above, but is accessible from outside, i.e. there the operator (you !) can use this to fill in and remove media from the changer. Sometimes named "mailslot". - data transfer - this is the device which reads/writes, i.e. the + data transfer this is the device which reads/writes, i.e. the CD-ROM / Tape / whatever drive. + =============== ================================================== None of these is limited to one: A huge Jukebox could have slots for 123 CD-ROM's, 5 CD-ROM readers (and therefore 6 SCSI ID's: the changer @@ -131,24 +135,23 @@ timeout_init=<seconds> timeout_move=<seconds> timeout for all other commands (default: 120). -dt_id=<id1>,<id2>,... -dt_lun=<lun1>,<lun2>,... +dt_id=<id1>,<id2>,... / dt_lun=<lun1>,<lun2>,... These two allow to specify the SCSI ID and LUN for the data transfer elements. You likely don't need this as the jukebox should provide this information. But some devices don't ... -vendor_firsts= -vendor_counts= -vendor_labels= +vendor_firsts=, vendor_counts=, vendor_labels= These insmod options can be used to tell the driver that there are some vendor-specific element types. Grundig for example does this. Some jukeboxes have a printer to label fresh burned CDs, which is addressed as element 0xc000 (type 5). To tell the - driver about this vendor-specific element, use this: + driver about this vendor-specific element, use this:: + $ insmod ch \ vendor_firsts=0xc000 \ vendor_counts=1 \ vendor_labels=printer + All three insmod options accept up to four comma-separated values, this way you can configure the element types 5-8. You likely need the SCSI specs for the device in question to @@ -162,13 +165,15 @@ Credits I wrote this driver using the famous mailing-patches-around-the-world method. With (more or less) help from: - Daniel Moehwald <moehwald@hdg.de> - Dane Jasper <dane@sonic.net> - R. Scott Bailey <sbailey@dsddi.eds.com> - Jonathan Corbet <corbet@lwn.net> + - Daniel Moehwald <moehwald@hdg.de> + - Dane Jasper <dane@sonic.net> + - R. Scott Bailey <sbailey@dsddi.eds.com> + - Jonathan Corbet <corbet@lwn.net> Special thanks go to - Martin Kuehne <martin.kuehne@bnbt.de> + + - Martin Kuehne <martin.kuehne@bnbt.de> + for a old, second-hand (but full functional) cdrom jukebox which I use to develop/test driver and tools now. @@ -176,5 +181,4 @@ Have fun, Gerd --- Gerd Knorr <kraxel@bytesex.org> diff --git a/Documentation/scsi/scsi-generic.txt b/Documentation/scsi/scsi-generic.rst index 51be20a6a14d..258505e557a6 100644 --- a/Documentation/scsi/scsi-generic.txt +++ b/Documentation/scsi/scsi-generic.rst @@ -1,6 +1,11 @@ - Notes on Linux SCSI Generic (sg) driver - --------------------------------------- +.. SPDX-License-Identifier: GPL-2.0 + +======================================= +Notes on Linux SCSI Generic (sg) driver +======================================= + 20020126 + Introduction ============ The SCSI Generic driver (sg) is one of the four "high level" SCSI device @@ -18,7 +23,7 @@ and examples. Major versions of the sg driver =============================== There are three major versions of sg found in the linux kernel (lk): - - sg version 1 (original) from 1992 to early 1999 (lk 2.2.5) . + - sg version 1 (original) from 1992 to early 1999 (lk 2.2.5) . It is based in the sg_header interface structure. - sg version 2 from lk 2.2.6 in the 2.2 series. It is based on an extended version of the sg_header interface structure. @@ -29,12 +34,16 @@ There are three major versions of sg found in the linux kernel (lk): Sg driver documentation ======================= The most recent documentation of the sg driver is kept at the Linux -Documentation Project's (LDP) site: -http://www.tldp.org/HOWTO/SCSI-Generic-HOWTO +Documentation Project's (LDP) site: + +- http://www.tldp.org/HOWTO/SCSI-Generic-HOWTO + This describes the sg version 3 driver found in the lk 2.4 series. + The LDP renders documents in single and multiple page HTML, postscript and pdf. This document can also be found at: -http://sg.danny.cz/sg/p/sg_v3_ho.html + +- http://sg.danny.cz/sg/p/sg_v3_ho.html Documentation for the version 2 sg driver found in the lk 2.2 series can be found at http://sg.danny.cz/sg/. A larger version @@ -45,23 +54,27 @@ found at http://www.torque.net/sg/p/original/SCSI-Programming-HOWTO.txt and in the LDP archives. A changelog with brief notes can be found in the -/usr/src/linux/include/scsi/sg.h file. Note that the glibc maintainers copy -and edit this file (removing its changelog for example) before placing it -in /usr/include/scsi/sg.h . Driver debugging information and other notes +/usr/src/linux/include/scsi/sg.h file. Note that the glibc maintainers copy +and edit this file (removing its changelog for example) before placing it +in /usr/include/scsi/sg.h . Driver debugging information and other notes can be found at the top of the /usr/src/linux/drivers/scsi/sg.c file. -A more general description of the Linux SCSI subsystem of which sg is a +A more general description of the Linux SCSI subsystem of which sg is a part can be found at http://www.tldp.org/HOWTO/SCSI-2.4-HOWTO . Example code and utilities ========================== There are two packages of sg utilities: - - sg3_utils for the sg version 3 driver found in lk 2.4 - - sg_utils for the sg version 2 (and original) driver found in lk 2.2 + + ========= ========================================================== + sg3_utils for the sg version 3 driver found in lk 2.4 + sg_utils for the sg version 2 (and original) driver found in lk 2.2 and earlier + ========= ========================================================== + Both packages will work in the lk 2.4 series however sg3_utils offers more -capabilities. They can be found at: http://sg.danny.cz/sg/sg3_utils.html and +capabilities. They can be found at: http://sg.danny.cz/sg/sg3_utils.html and freecode.com Another approach is to look at the applications that use the sg driver. @@ -72,30 +85,34 @@ Mapping of Linux kernel versions to sg driver versions ====================================================== Here is a list of linux kernels in the 2.4 series that had new version of the sg driver: - lk 2.4.0 : sg version 3.1.17 - lk 2.4.7 : sg version 3.1.19 - lk 2.4.10 : sg version 3.1.20 ** - lk 2.4.17 : sg version 3.1.22 -** There were 3 changes to sg version 3.1.20 by third parties in the - next six linux kernel versions. + - lk 2.4.0 : sg version 3.1.17 + - lk 2.4.7 : sg version 3.1.19 + - lk 2.4.10 : sg version 3.1.20 [#]_ + - lk 2.4.17 : sg version 3.1.22 + +.. [#] There were 3 changes to sg version 3.1.20 by third parties in the + next six linux kernel versions. -For reference here is a list of linux kernels in the 2.2 series that had +For reference here is a list of linux kernels in the 2.2 series that had new version of the sg driver: - lk 2.2.0 : original sg version [with no version number] - lk 2.2.6 : sg version 2.1.31 - lk 2.2.8 : sg version 2.1.32 - lk 2.2.10 : sg version 2.1.34 [SG_GET_VERSION_NUM ioctl first appeared] - lk 2.2.14 : sg version 2.1.36 - lk 2.2.16 : sg version 2.1.38 - lk 2.2.17 : sg version 2.1.39 - lk 2.2.20 : sg version 2.1.40 + + - lk 2.2.0 : original sg version [with no version number] + - lk 2.2.6 : sg version 2.1.31 + - lk 2.2.8 : sg version 2.1.32 + - lk 2.2.10 : sg version 2.1.34 [SG_GET_VERSION_NUM ioctl first appeared] + - lk 2.2.14 : sg version 2.1.36 + - lk 2.2.16 : sg version 2.1.38 + - lk 2.2.17 : sg version 2.1.39 + - lk 2.2.20 : sg version 2.1.40 The lk 2.5 development series has recently commenced and it currently contains sg version 3.5.23 which is functionally equivalent to sg -version 3.1.22 found in lk 2.4.17 . +version 3.1.22 found in lk 2.4.17. Douglas Gilbert + 26th January 2002 + dgilbert@interlog.com diff --git a/Documentation/scsi/scsi-parameters.txt b/Documentation/scsi/scsi-parameters.rst index 25a4b4cf04a6..9aba897c97ac 100644 --- a/Documentation/scsi/scsi-parameters.txt +++ b/Documentation/scsi/scsi-parameters.rst @@ -1,31 +1,35 @@ - SCSI Kernel Parameters - ~~~~~~~~~~~~~~~~~~~~~~ +.. SPDX-License-Identifier: GPL-2.0 + +====================== +SCSI Kernel Parameters +====================== See Documentation/admin-guide/kernel-parameters.rst for general information on specifying module parameters. This document may not be entirely up to date and comprehensive. The command -"modinfo -p ${modulename}" shows a current list of all parameters of a loadable +``modinfo -p ${modulename}`` shows a current list of all parameters of a loadable module. Loadable modules, after being loaded into the running kernel, also reveal their parameters in /sys/module/${modulename}/parameters/. Some of these parameters may be changed at runtime by the command -"echo -n ${value} > /sys/module/${modulename}/parameters/${parm}". +``echo -n ${value} > /sys/module/${modulename}/parameters/${parm}``. +:: advansys= [HW,SCSI] See header of drivers/scsi/advansys.c. aha152x= [HW,SCSI] - See Documentation/scsi/aha152x.txt. + See Documentation/scsi/aha152x.rst. aha1542= [HW,SCSI] Format: <portbase>[,<buson>,<busoff>[,<dmaspeed>]] aic7xxx= [HW,SCSI] - See Documentation/scsi/aic7xxx.txt. + See Documentation/scsi/aic7xxx.rst. aic79xx= [HW,SCSI] - See Documentation/scsi/aic79xx.txt. + See Documentation/scsi/aic79xx.rst. atascsi= [HW,SCSI] See drivers/scsi/atari_scsi.c. @@ -57,19 +61,19 @@ parameters may be changed at runtime by the command See header of drivers/scsi/NCR_D700.c. ncr5380= [HW,SCSI] - See Documentation/scsi/g_NCR5380.txt. + See Documentation/scsi/g_NCR5380.rst. ncr53c400= [HW,SCSI] - See Documentation/scsi/g_NCR5380.txt. + See Documentation/scsi/g_NCR5380.rst. ncr53c400a= [HW,SCSI] - See Documentation/scsi/g_NCR5380.txt. + See Documentation/scsi/g_NCR5380.rst. ncr53c8xx= [HW,SCSI] osst= [HW,SCSI] SCSI Tape Driver Format: <buffer_size>,<write_threshold> - See also Documentation/scsi/st.txt. + See also Documentation/scsi/st.rst. scsi_debug_*= [SCSI] See drivers/scsi/scsi_debug.c. @@ -101,7 +105,7 @@ parameters may be changed at runtime by the command See header of drivers/scsi/sim710.c. st= [HW,SCSI] SCSI tape parameters (buffers, etc.) - See Documentation/scsi/st.txt. + See Documentation/scsi/st.rst. wd33c93= [HW,SCSI] See header of drivers/scsi/wd33c93.c. diff --git a/Documentation/scsi/scsi.txt b/Documentation/scsi/scsi.rst index 3d99d38cb62a..276918eb4d74 100644 --- a/Documentation/scsi/scsi.txt +++ b/Documentation/scsi/scsi.rst @@ -1,44 +1,47 @@ +.. SPDX-License-Identifier: GPL-2.0 + +============================ SCSI subsystem documentation ============================ + The Linux Documentation Project (LDP) maintains a document describing the SCSI subsystem in the Linux kernel (lk) 2.4 series. See: http://www.tldp.org/HOWTO/SCSI-2.4-HOWTO . The LDP has single and multiple page HTML renderings as well as postscript and pdf. It can also be found at: -http://web.archive.org/web/*/http://www.torque.net/scsi/SCSI-2.4-HOWTO +http://web.archive.org/web/%2E/http://www.torque.net/scsi/SCSI-2.4-HOWTO Notes on using modules in the SCSI subsystem ============================================ -The scsi support in the linux kernel can be modularized in a number of +The scsi support in the linux kernel can be modularized in a number of different ways depending upon the needs of the end user. To understand your options, we should first define a few terms. -The scsi-core (also known as the "mid level") contains the core of scsi +The scsi-core (also known as the "mid level") contains the core of scsi support. Without it you can do nothing with any of the other scsi drivers. The scsi core support can be a module (scsi_mod.o), or it can be built into -the kernel. If the core is a module, it must be the first scsi module -loaded, and if you unload the modules, it will have to be the last one +the kernel. If the core is a module, it must be the first scsi module +loaded, and if you unload the modules, it will have to be the last one unloaded. In practice the modprobe and rmmod commands (and "autoclean") will enforce the correct ordering of loading and unloading modules in the SCSI subsystem. -The individual upper and lower level drivers can be loaded in any order +The individual upper and lower level drivers can be loaded in any order once the scsi core is present in the kernel (either compiled in or loaded as a module). The disk driver (sd_mod.o), cdrom driver (sr_mod.o), -tape driver ** (st.o) and scsi generics driver (sg.o) represent the upper -level drivers to support the various assorted devices which can be -controlled. You can for example load the tape driver to use the tape drive, +tape driver [1]_ (st.o) and scsi generics driver (sg.o) represent the upper +level drivers to support the various assorted devices which can be +controlled. You can for example load the tape driver to use the tape drive, and then unload it once you have no further need for the driver (and release the associated memory). The lower level drivers are the ones that support the individual cards that are supported for the hardware platform that you are running under. Those individual cards are often called Host Bus Adapters (HBAs). For example the -aic7xxx.o driver is used to control all recent SCSI controller cards from -Adaptec. Almost all lower level drivers can be built either as modules or +aic7xxx.o driver is used to control all recent SCSI controller cards from +Adaptec. Almost all lower level drivers can be built either as modules or built into the kernel. - -** There is a variant of the st driver for controlling OnStream tape - devices. Its module name is osst.o . +.. [1] There is a variant of the st driver for controlling OnStream tape + devices. Its module name is osst.o . diff --git a/Documentation/scsi/scsi_eh.txt b/Documentation/scsi/scsi_eh.rst index 1b7436932a2b..7d78c2475615 100644 --- a/Documentation/scsi/scsi_eh.txt +++ b/Documentation/scsi/scsi_eh.rst @@ -1,35 +1,39 @@ +.. SPDX-License-Identifier: GPL-2.0 +======= SCSI EH -====================================== +======= - This document describes SCSI midlayer error handling infrastructure. -Please refer to Documentation/scsi/scsi_mid_low_api.txt for more +This document describes SCSI midlayer error handling infrastructure. +Please refer to Documentation/scsi/scsi_mid_low_api.rst for more information regarding SCSI midlayer. -TABLE OF CONTENTS +.. TABLE OF CONTENTS -[1] How SCSI commands travel through the midlayer and to EH - [1-1] struct scsi_cmnd - [1-2] How do scmd's get completed? - [1-2-1] Completing a scmd w/ scsi_done - [1-2-2] Completing a scmd w/ timeout - [1-3] How EH takes over -[2] How SCSI EH works - [2-1] EH through fine-grained callbacks - [2-1-1] Overview - [2-1-2] Flow of scmds through EH - [2-1-3] Flow of control - [2-2] EH through transportt->eh_strategy_handler() - [2-2-1] Pre transportt->eh_strategy_handler() SCSI midlayer conditions - [2-2-2] Post transportt->eh_strategy_handler() SCSI midlayer conditions - [2-2-3] Things to consider + [1] How SCSI commands travel through the midlayer and to EH + [1-1] struct scsi_cmnd + [1-2] How do scmd's get completed? + [1-2-1] Completing a scmd w/ scsi_done + [1-2-2] Completing a scmd w/ timeout + [1-3] How EH takes over + [2] How SCSI EH works + [2-1] EH through fine-grained callbacks + [2-1-1] Overview + [2-1-2] Flow of scmds through EH + [2-1-3] Flow of control + [2-2] EH through transportt->eh_strategy_handler() + [2-2-1] Pre transportt->eh_strategy_handler() SCSI midlayer conditions + [2-2-2] Post transportt->eh_strategy_handler() SCSI midlayer conditions + [2-2-3] Things to consider -[1] How SCSI commands travel through the midlayer and to EH +1. How SCSI commands travel through the midlayer and to EH +========================================================== -[1-1] struct scsi_cmnd +1.1 struct scsi_cmnd +-------------------- - Each SCSI command is represented with struct scsi_cmnd (== scmd). A +Each SCSI command is represented with struct scsi_cmnd (== scmd). A scmd has two list_head's to link itself into lists. The two are scmd->list and scmd->eh_entry. The former is used for free list or per-device allocated scmd list and not of much interest to this EH @@ -38,25 +42,28 @@ otherwise stated scmds are always linked using scmd->eh_entry in this discussion. -[1-2] How do scmd's get completed? +1.2 How do scmd's get completed? +-------------------------------- - Once LLDD gets hold of a scmd, either the LLDD will complete the +Once LLDD gets hold of a scmd, either the LLDD will complete the command by calling scsi_done callback passed from midlayer when invoking hostt->queuecommand() or the block layer will time it out. -[1-2-1] Completing a scmd w/ scsi_done +1.2.1 Completing a scmd w/ scsi_done +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - For all non-EH commands, scsi_done() is the completion callback. It +For all non-EH commands, scsi_done() is the completion callback. It just calls blk_complete_request() to delete the block layer timer and raise SCSI_SOFTIRQ - SCSI_SOFTIRQ handler scsi_softirq calls scsi_decide_disposition() to +SCSI_SOFTIRQ handler scsi_softirq calls scsi_decide_disposition() to determine what to do with the command. scsi_decide_disposition() looks at the scmd->result value and sense data to determine what to do with the command. - SUCCESS + scsi_finish_command() is invoked for the command. The function does some maintenance chores and then calls scsi_io_completion() to finish the I/O. @@ -66,17 +73,21 @@ with the command. of the data in case of an error. - NEEDS_RETRY + - ADD_TO_MLQUEUE + scmd is requeued to blk queue. - otherwise + scsi_eh_scmd_add(scmd) is invoked for the command. See [1-3] for details of this function. -[1-2-2] Completing a scmd w/ timeout +1.2.2 Completing a scmd w/ timeout +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - The timeout handler is scsi_times_out(). When a timeout occurs, this +The timeout handler is scsi_times_out(). When a timeout occurs, this function 1. invokes optional hostt->eh_timed_out() callback. Return value can @@ -101,18 +112,21 @@ function 3. scsi_eh_scmd_add(scmd, SCSI_EH_CANCEL_CMD) is invoked for the command. See [1-4] for more information. -[1-3] Asynchronous command aborts +1.3 Asynchronous command aborts +------------------------------- After a timeout occurs a command abort is scheduled from scsi_abort_command(). If the abort is successful the command will either be retried (if the number of retries is not exhausted) or terminated with DID_TIME_OUT. + Otherwise scsi_eh_scmd_add() is invoked for the command. See [1-4] for more information. -[1-4] How EH takes over +1.4 How EH takes over +--------------------- - scmds enter EH via scsi_eh_scmd_add(), which does the following. +scmds enter EH via scsi_eh_scmd_add(), which does the following. 1. Links scmd->eh_entry to shost->eh_cmd_q @@ -122,19 +136,19 @@ function 4. Wakes up SCSI EH thread if shost->host_busy == shost->host_failed - As can be seen above, once any scmd is added to shost->eh_cmd_q, +As can be seen above, once any scmd is added to shost->eh_cmd_q, SHOST_RECOVERY shost_state bit is turned on. This prevents any new scmd to be issued from blk queue to the host; eventually, all scmds on the host either complete normally, fail and get added to eh_cmd_q, or time out and get added to shost->eh_cmd_q. - If all scmds either complete or fail, the number of in-flight scmds +If all scmds either complete or fail, the number of in-flight scmds becomes equal to the number of failed scmds - i.e. shost->host_busy == shost->host_failed. This wakes up SCSI EH thread. So, once woken up, SCSI EH thread can expect that all in-flight commands have failed and are linked on shost->eh_cmd_q. - Note that this does not mean lower layers are quiescent. If a LLDD +Note that this does not mean lower layers are quiescent. If a LLDD completed a scmd with error status, the LLDD and lower layers are assumed to forget about the scmd at that point. However, if a scmd has timed out, unless hostt->eh_timed_out() made lower layers forget @@ -143,13 +157,14 @@ active as long as lower layers are concerned and completion could occur at any time. Of course, all such completions are ignored as the timer has already expired. - We'll talk about how SCSI EH takes actions to abort - make LLDD +We'll talk about how SCSI EH takes actions to abort - make LLDD forget about - timed out scmds later. -[2] How SCSI EH works +2. How SCSI EH works +==================== - LLDD's can implement SCSI EH actions in one of the following two +LLDD's can implement SCSI EH actions in one of the following two ways. - Fine-grained EH callbacks @@ -162,7 +177,7 @@ ways. handling. As such, it should do all chores the SCSI midlayer performs during recovery. This will be discussed in [2-2]. - Once recovery is complete, SCSI EH resumes normal operation by +Once recovery is complete, SCSI EH resumes normal operation by calling scsi_restart_operations(), which 1. Checks if door locking is needed and locks door. @@ -177,34 +192,38 @@ calling scsi_restart_operations(), which 4. Kicks queues in all devices on the host in the asses -[2-1] EH through fine-grained callbacks +2.1 EH through fine-grained callbacks +------------------------------------- -[2-1-1] Overview +2.1.1 Overview +^^^^^^^^^^^^^^ - If eh_strategy_handler() is not present, SCSI midlayer takes charge +If eh_strategy_handler() is not present, SCSI midlayer takes charge of driving error handling. EH's goals are two - make LLDD, host and device forget about timed out scmds and make them ready for new commands. A scmd is said to be recovered if the scmd is forgotten by lower layers and lower layers are ready to process or fail the scmd again. - To achieve these goals, EH performs recovery actions with increasing +To achieve these goals, EH performs recovery actions with increasing severity. Some actions are performed by issuing SCSI commands and others are performed by invoking one of the following fine-grained hostt EH callbacks. Callbacks may be omitted and omitted ones are considered to fail always. -int (* eh_abort_handler)(struct scsi_cmnd *); -int (* eh_device_reset_handler)(struct scsi_cmnd *); -int (* eh_bus_reset_handler)(struct scsi_cmnd *); -int (* eh_host_reset_handler)(struct scsi_cmnd *); +:: - Higher-severity actions are taken only when lower-severity actions + int (* eh_abort_handler)(struct scsi_cmnd *); + int (* eh_device_reset_handler)(struct scsi_cmnd *); + int (* eh_bus_reset_handler)(struct scsi_cmnd *); + int (* eh_host_reset_handler)(struct scsi_cmnd *); + +Higher-severity actions are taken only when lower-severity actions cannot recover some of failed scmds. Also, note that failure of the highest-severity action means EH failure and results in offlining of all unrecovered devices. - During recovery, the following rules are followed +During recovery, the following rules are followed - Recovery actions are performed on failed scmds on the to do list, eh_work_q. If a recovery action succeeds for a scmd, recovered @@ -221,58 +240,72 @@ all unrecovered devices. timed-out scmds, SCSI EH ensures that LLDD forgets about a scmd before reusing it for EH commands. - When a scmd is recovered, the scmd is moved from eh_work_q to EH +When a scmd is recovered, the scmd is moved from eh_work_q to EH local eh_done_q using scsi_eh_finish_cmd(). After all scmds are recovered (eh_work_q is empty), scsi_eh_flush_done_q() is invoked to either retry or error-finish (notify upper layer of failure) recovered scmds. - scmds are retried iff its sdev is still online (not offlined during +scmds are retried iff its sdev is still online (not offlined during EH), REQ_FAILFAST is not set and ++scmd->retries is less than scmd->allowed. -[2-1-2] Flow of scmds through EH +2.1.2 Flow of scmds through EH +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1. Error completion / time out - ACTION: scsi_eh_scmd_add() is invoked for scmd + + :ACTION: scsi_eh_scmd_add() is invoked for scmd + - add scmd to shost->eh_cmd_q - set SHOST_RECOVERY - shost->host_failed++ - LOCKING: shost->host_lock + + :LOCKING: shost->host_lock 2. EH starts - ACTION: move all scmds to EH's local eh_work_q. shost->eh_cmd_q - is cleared. - LOCKING: shost->host_lock (not strictly necessary, just for + + :ACTION: move all scmds to EH's local eh_work_q. shost->eh_cmd_q + is cleared. + + :LOCKING: shost->host_lock (not strictly necessary, just for consistency) 3. scmd recovered - ACTION: scsi_eh_finish_cmd() is invoked to EH-finish scmd + + :ACTION: scsi_eh_finish_cmd() is invoked to EH-finish scmd + - scsi_setup_cmd_retry() - move from local eh_work_q to local eh_done_q - LOCKING: none - CONCURRENCY: at most one thread per separate eh_work_q to - keep queue manipulation lockless + + :LOCKING: none + + :CONCURRENCY: at most one thread per separate eh_work_q to + keep queue manipulation lockless 4. EH completes - ACTION: scsi_eh_flush_done_q() retries scmds or notifies upper - layer of failure. May be called concurrently but must have - a no more than one thread per separate eh_work_q to - manipulate the queue locklessly - - scmd is removed from eh_done_q and scmd->eh_entry is cleared - - if retry is necessary, scmd is requeued using - scsi_queue_insert() - - otherwise, scsi_finish_command() is invoked for scmd - - zero shost->host_failed - LOCKING: queue or finish function performs appropriate locking + :ACTION: scsi_eh_flush_done_q() retries scmds or notifies upper + layer of failure. May be called concurrently but must have + a no more than one thread per separate eh_work_q to + manipulate the queue locklessly -[2-1-3] Flow of control + - scmd is removed from eh_done_q and scmd->eh_entry is cleared + - if retry is necessary, scmd is requeued using + scsi_queue_insert() + - otherwise, scsi_finish_command() is invoked for scmd + - zero shost->host_failed + + :LOCKING: queue or finish function performs appropriate locking + + +2.1.3 Flow of control +^^^^^^^^^^^^^^^^^^^^^^ EH through fine-grained callbacks start from scsi_unjam_host(). -<<scsi_unjam_host>> +``scsi_unjam_host`` 1. Lock shost->host_lock, splice_init shost->eh_cmd_q into local eh_work_q and unlock host_lock. Note that shost->eh_cmd_q is @@ -280,7 +313,7 @@ scmd->allowed. 2. Invoke scsi_eh_get_sense. - <<scsi_eh_get_sense>> + ``scsi_eh_get_sense`` This action is taken for each error-completed (!SCSI_EH_CANCEL_CMD) commands without valid sense data. Most @@ -315,7 +348,7 @@ scmd->allowed. 3. If !list_empty(&eh_work_q), invoke scsi_eh_abort_cmds(). - <<scsi_eh_abort_cmds>> + ``scsi_eh_abort_cmds`` This action is taken for each timed out command when no_async_abort is enabled in the host template. @@ -339,14 +372,14 @@ scmd->allowed. 4. If !list_empty(&eh_work_q), invoke scsi_eh_ready_devs() - <<scsi_eh_ready_devs>> + ``scsi_eh_ready_devs`` This function takes four increasingly more severe measures to make failed sdevs ready for new commands. 1. Invoke scsi_eh_stu() - <<scsi_eh_stu>> + ``scsi_eh_stu`` For each sdev which has failed scmds with valid sense data of which scsi_check_sense()'s verdict is FAILED, @@ -369,7 +402,7 @@ scmd->allowed. 2. If !list_empty(&eh_work_q), invoke scsi_eh_bus_device_reset(). - <<scsi_eh_bus_device_reset>> + ``scsi_eh_bus_device_reset`` This action is very similar to scsi_eh_stu() except that, instead of issuing STU, hostt->eh_device_reset_handler() @@ -379,7 +412,7 @@ scmd->allowed. 3. If !list_empty(&eh_work_q), invoke scsi_eh_bus_reset() - <<scsi_eh_bus_reset>> + ``scsi_eh_bus_reset`` hostt->eh_bus_reset_handler() is invoked for each channel with failed scmds. If bus reset succeeds, all failed @@ -388,7 +421,7 @@ scmd->allowed. 4. If !list_empty(&eh_work_q), invoke scsi_eh_host_reset() - <<scsi_eh_host_reset>> + ``scsi_eh_host_reset`` This is the last resort. hostt->eh_host_reset_handler() is invoked. If host reset succeeds, all failed scmds on @@ -396,14 +429,14 @@ scmd->allowed. 5. If !list_empty(&eh_work_q), invoke scsi_eh_offline_sdevs() - <<scsi_eh_offline_sdevs>> + ``scsi_eh_offline_sdevs`` Take all sdevs which still have unrecovered scmds offline and EH-finish the scmds. 5. Invoke scsi_eh_flush_done_q(). - <<scsi_eh_flush_done_q>> + ``scsi_eh_flush_done_q`` At this point all scmds are recovered (or given up) and put on eh_done_q by scsi_eh_finish_cmd(). This function @@ -411,9 +444,10 @@ scmd->allowed. layer of failure of the scmds. -[2-2] EH through transportt->eh_strategy_handler() +2.2 EH through transportt->eh_strategy_handler() +------------------------------------------------ - transportt->eh_strategy_handler() is invoked in the place of +transportt->eh_strategy_handler() is invoked in the place of scsi_unjam_host() and it is responsible for whole recovery process. On completion, the handler should have made lower layers forget about all failed scmds and either ready for new commands or offline. Also, @@ -422,7 +456,8 @@ SCSI midlayer. IOW, of the steps described in [2-1-2], all steps except for #1 must be implemented by eh_strategy_handler(). -[2-2-1] Pre transportt->eh_strategy_handler() SCSI midlayer conditions +2.2.1 Pre transportt->eh_strategy_handler() SCSI midlayer conditions +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ The following conditions are true on entry to the handler. @@ -435,7 +470,8 @@ except for #1 must be implemented by eh_strategy_handler(). - shost->host_failed == shost->host_busy -[2-2-2] Post transportt->eh_strategy_handler() SCSI midlayer conditions +2.2.2 Post transportt->eh_strategy_handler() SCSI midlayer conditions +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ The following conditions must be true on exit from the handler. @@ -453,7 +489,8 @@ except for #1 must be implemented by eh_strategy_handler(). ->allowed to limit the number of retries. -[2-2-3] Things to consider +2.2.3 Things to consider +^^^^^^^^^^^^^^^^^^^^^^^^ - Know that timed out scmds are still active on lower layers. Make lower layers forget about them before doing anything else with @@ -469,7 +506,7 @@ except for #1 must be implemented by eh_strategy_handler(). offline. --- Tejun Heo htejun@gmail.com + 11th September 2005 diff --git a/Documentation/scsi/scsi_fc_transport.txt b/Documentation/scsi/scsi_fc_transport.rst index f79282fc48d7..176c1862cb9b 100644 --- a/Documentation/scsi/scsi_fc_transport.txt +++ b/Documentation/scsi/scsi_fc_transport.rst @@ -1,8 +1,13 @@ - SCSI FC Tansport - ============================================= +.. SPDX-License-Identifier: GPL-2.0 + +================ +SCSI FC Tansport +================ Date: 11/18/2008 -Kernel Revisions for features: + +Kernel Revisions for features:: + rports : <<TBS>> vports : 2.6.22 bsg support : 2.6.30 (?TBD?) @@ -12,25 +17,27 @@ Introduction ============ This file documents the features and components of the SCSI FC Transport. It also provides documents the API between the transport and FC LLDDs. -The FC transport can be found at: + +The FC transport can be found at:: + drivers/scsi/scsi_transport_fc.c include/scsi/scsi_transport_fc.h include/scsi/scsi_netlink_fc.h include/scsi/scsi_bsg_fc.h -This file is found at Documentation/scsi/scsi_fc_transport.txt +This file is found at Documentation/scsi/scsi_fc_transport.rst FC Remote Ports (rports) -======================================================================== +======================== << To Be Supplied >> FC Virtual Ports (vports) -======================================================================== +========================= -Overview: -------------------------------- +Overview +-------- New FC standards have defined mechanisms which allows for a single physical port to appear on as multiple communication ports. Using the N_Port Id @@ -61,12 +68,14 @@ Overview: Thus, whether a FC port is based on a physical port or on a virtual port, each will appear as a unique scsi_host with its own target and lun space. - Note: At this time, the transport is written to create only NPIV-based + .. Note:: + At this time, the transport is written to create only NPIV-based vports. However, consideration was given to VF-based vports and it should be a minor change to add support if needed. The remaining discussion will concentrate on NPIV. - Note: World Wide Name assignment (and uniqueness guarantees) are left + .. Note:: + World Wide Name assignment (and uniqueness guarantees) are left up to an administrative entity controlling the vport. For example, if vports are to be associated with virtual machines, a XEN mgmt utility would be responsible for creating wwpn/wwnn's for the vport, @@ -91,18 +100,29 @@ Device Trees and Vport Objects: port's scsi_host. Here's what to expect in the device tree : - The typical Physical Port's Scsi_Host: + + The typical Physical Port's Scsi_Host:: + /sys/devices/.../host17/ - and it has the typical descendant tree: + + and it has the typical descendant tree:: + /sys/devices/.../host17/rport-17:0-0/target17:0:0/17:0:0:0: - and then the vport is created on the Physical Port: + + and then the vport is created on the Physical Port:: + /sys/devices/.../host17/vport-17:0-0 - and the vport's Scsi_Host is then created: + + and the vport's Scsi_Host is then created:: + /sys/devices/.../host17/vport-17:0-0/host18 - and then the rest of the tree progresses, such as: + + and then the rest of the tree progresses, such as:: + /sys/devices/.../host17/vport-17:0-0/host18/rport-18:0-0/target18:0:0/18:0:0:0: - Here's what to expect in the sysfs tree : + Here's what to expect in the sysfs tree:: + scsi_hosts: /sys/class/scsi_host/host17 physical port's scsi_host /sys/class/scsi_host/host18 vport's scsi_host @@ -116,8 +136,8 @@ Device Trees and Vport Objects: /sys/class/fc_remote_ports/rport-18:0-0 rport on the vport -Vport Attributes: -------------------------------- +Vport Attributes +---------------- The new fc_vport class object has the following attributes @@ -184,16 +204,18 @@ Vport Attributes: (e.g. 0x, x, etc). -Vport States: -------------------------------- +Vport States +------------ Vport instantiation consists of two parts: + - Creation with the kernel and LLDD. This means all transport and driver data structures are built up, and device objects created. This is equivalent to a driver "attach" on an adapter, which is independent of the adapter's link state. - Instantiation of the vport on the FC link via ELS traffic, etc. This is equivalent to a "link up" and successful link initialization. + Further information can be found in the interfaces section below for Vport Creation. @@ -227,6 +249,7 @@ Vport States: FC_VPORT_NO_FABRIC_SUPP - No Fabric Support The vport is not operational. One of the following conditions were encountered: + - The FC topology is not Point-to-Point - The FC port is not connected to an F_Port - The F_Port has indicated that NPIV is not supported. @@ -251,32 +274,53 @@ Vport States: The following state table indicates the different state transitions: - State Event New State - -------------------------------------------------------------------- - n/a Initialization Unknown - Unknown: Link Down Linkdown - Link Up & Loop No Fabric Support - Link Up & no Fabric No Fabric Support - Link Up & FLOGI response No Fabric Support - indicates no NPIV support - Link Up & FDISC being sent Initializing - Disable request Disable - Linkdown: Link Up Unknown - Initializing: FDISC ACC Active - FDISC LS_RJT w/ no resources No Fabric Resources - FDISC LS_RJT w/ invalid Fabric Rejected WWN - pname or invalid nport_id - FDISC LS_RJT failed for Vport Failed - other reasons - Link Down Linkdown - Disable request Disable - Disable: Enable request Unknown - Active: LOGO received from fabric Fabric Logout - Link Down Linkdown - Disable request Disable - Fabric Logout: Link still up Unknown + +------------------+--------------------------------+---------------------+ + | State | Event | New State | + +==================+================================+=====================+ + | n/a | Initialization | Unknown | + +------------------+--------------------------------+---------------------+ + | Unknown: | Link Down | Linkdown | + | +--------------------------------+---------------------+ + | | Link Up & Loop | No Fabric Support | + | +--------------------------------+---------------------+ + | | Link Up & no Fabric | No Fabric Support | + | +--------------------------------+---------------------+ + | | Link Up & FLOGI response | No Fabric Support | + | | indicates no NPIV support | | + | +--------------------------------+---------------------+ + | | Link Up & FDISC being sent | Initializing | + | +--------------------------------+---------------------+ + | | Disable request | Disable | + +------------------+--------------------------------+---------------------+ + | Linkdown: | Link Up | Unknown | + +------------------+--------------------------------+---------------------+ + | Initializing: | FDISC ACC | Active | + | +--------------------------------+---------------------+ + | | FDISC LS_RJT w/ no resources | No Fabric Resources | + | +--------------------------------+---------------------+ + | | FDISC LS_RJT w/ invalid | Fabric Rejected WWN | + | | pname or invalid nport_id | | + | +--------------------------------+---------------------+ + | | FDISC LS_RJT failed for | Vport Failed | + | | other reasons | | + | +--------------------------------+---------------------+ + | | Link Down | Linkdown | + | +--------------------------------+---------------------+ + | | Disable request | Disable | + +------------------+--------------------------------+---------------------+ + | Disable: | Enable request | Unknown | + +------------------+--------------------------------+---------------------+ + | Active: | LOGO received from fabric | Fabric Logout | + | +--------------------------------+---------------------+ + | | Link Down | Linkdown | + | +--------------------------------+---------------------+ + | | Disable request | Disable | + +------------------+--------------------------------+---------------------+ + | Fabric Logout: | Link still up | Unknown | + +------------------+--------------------------------+---------------------+ + +The following 4 error states all have the same transitions:: - The following 4 error states all have the same transitions: No Fabric Support: No Fabric Resources: Fabric Rejected WWN: @@ -285,8 +329,8 @@ Vport States: Link goes down Linkdown -Transport <-> LLDD Interfaces : -------------------------------- +Transport <-> LLDD Interfaces +----------------------------- Vport support by LLDD: @@ -300,14 +344,17 @@ Vport support by LLDD: Vport Creation: - The LLDD vport_create() syntax is: + The LLDD vport_create() syntax is:: int vport_create(struct fc_vport *vport, bool disable) - where: - vport: Is the newly allocated vport object - disable: If "true", the vport is to be created in a disabled stated. + where: + + ======= =========================================================== + vport Is the newly allocated vport object + disable If "true", the vport is to be created in a disabled stated. If "false", the vport is to be enabled upon creation. + ======= =========================================================== When a request is made to create a new vport (via sgio/netlink, or the vport_create fc_host attribute), the transport will validate that the LLDD @@ -317,6 +364,7 @@ Vport Creation: LLDD's vport_create() function with the newly allocated vport object. As mentioned above, vport creation is divided into two parts: + - Creation with the kernel and LLDD. This means all transport and driver data structures are built up, and device objects created. This is equivalent to a driver "attach" on an adapter, which is @@ -329,6 +377,7 @@ Vport Creation: infrastructure exists to support NPIV, and complete the first part of vport creation (data structure build up) before returning. We do not hinge vport_create() on the link-side operation mainly because: + - The link may be down. It is not a failure if it is. It simply means the vport is in an inoperable state until the link comes up. This is consistent with the link bouncing post vport creation. @@ -337,11 +386,15 @@ Vport Creation: FC adapter. The vport_create is synonymous with driver attachment to the adapter, which is independent of link state. - Note: special error codes have been defined to delineate infrastructure + .. Note:: + + special error codes have been defined to delineate infrastructure failure cases for quicker resolution. The expected behavior for the LLDD's vport_create() function is: + - Validate Infrastructure: + - If the driver or adapter cannot support another vport, whether due to improper firmware, (a lie about) max_npiv, or a lack of some other resource - return VPCERR_UNSUPPORTED. @@ -349,17 +402,21 @@ Vport Creation: the adapter and detects an overlap - return VPCERR_BAD_WWN. - If the driver detects the topology is loop, non-fabric, or the FLOGI did not support NPIV - return VPCERR_NO_FABRIC_SUPP. + - Allocate data structures. If errors are encountered, such as out of memory conditions, return the respective negative Exxx error code. - If the role is FCP Initiator, the LLDD is to : + - Call scsi_host_alloc() to allocate a scsi_host for the vport. - Call scsi_add_host(new_shost, &vport->dev) to start the scsi_host and bind it as a child of the vport device. - Initializes the fc_host attribute values. + - Kick of further vport state transitions based on the disable flag and link state - and return success (zero). LLDD Implementers Notes: + - It is suggested that there be a different fc_function_templates for the physical port and the virtual port. The physical port's template would have the vport_create, vport_delete, and vport_disable functions, @@ -373,14 +430,17 @@ Vport Creation: Vport Disable/Enable: - The LLDD vport_disable() syntax is: + The LLDD vport_disable() syntax is:: int vport_disable(struct fc_vport *vport, bool disable) - where: - vport: Is vport to be enabled or disabled - disable: If "true", the vport is to be disabled. + where: + + ======= ======================================= + vport Is vport to be enabled or disabled + disable If "true", the vport is to be disabled. If "false", the vport is to be enabled. + ======= ======================================= When a request is made to change the disabled state on a vport, the transport will validate the request against the existing vport state. @@ -401,11 +461,12 @@ Vport Disable/Enable: Vport Deletion: - The LLDD vport_delete() syntax is: + The LLDD vport_delete() syntax is:: int vport_delete(struct fc_vport *vport) - where: + where: + vport: Is vport to delete When a request is made to delete a vport (via sgio/netlink, or via the @@ -443,39 +504,42 @@ Transport supplied functions The following functions are supplied by the FC-transport for use by LLDs. - fc_vport_create - create a vport - fc_vport_terminate - detach and remove a vport - -Details: - -/** - * fc_vport_create - Admin App or LLDD requests creation of a vport - * @shost: scsi host the virtual port is connected to. - * @ids: The world wide names, FC4 port roles, etc for - * the virtual port. - * - * Notes: - * This routine assumes no locks are held on entry. - */ -struct fc_vport * -fc_vport_create(struct Scsi_Host *shost, struct fc_vport_identifiers *ids) - -/** - * fc_vport_terminate - Admin App or LLDD requests termination of a vport - * @vport: fc_vport to be terminated - * - * Calls the LLDD vport_delete() function, then deallocates and removes - * the vport from the shost and object tree. - * - * Notes: - * This routine assumes no locks are held on entry. - */ -int -fc_vport_terminate(struct fc_vport *vport) + ================== ========================= + fc_vport_create create a vport + fc_vport_terminate detach and remove a vport + ================== ========================= + +Details:: + + /** + * fc_vport_create - Admin App or LLDD requests creation of a vport + * @shost: scsi host the virtual port is connected to. + * @ids: The world wide names, FC4 port roles, etc for + * the virtual port. + * + * Notes: + * This routine assumes no locks are held on entry. + */ + struct fc_vport * + fc_vport_create(struct Scsi_Host *shost, struct fc_vport_identifiers *ids) + + /** + * fc_vport_terminate - Admin App or LLDD requests termination of a vport + * @vport: fc_vport to be terminated + * + * Calls the LLDD vport_delete() function, then deallocates and removes + * the vport from the shost and object tree. + * + * Notes: + * This routine assumes no locks are held on entry. + */ + int + fc_vport_terminate(struct fc_vport *vport) FC BSG support (CT & ELS passthru, and more) -======================================================================== +============================================ + << To Be Supplied >> diff --git a/Documentation/scsi/scsi_mid_low_api.rst b/Documentation/scsi/scsi_mid_low_api.rst new file mode 100644 index 000000000000..5358bc10689e --- /dev/null +++ b/Documentation/scsi/scsi_mid_low_api.rst @@ -0,0 +1,1313 @@ +.. SPDX-License-Identifier: GPL-2.0 + +============================================= +SCSI mid_level - lower_level driver interface +============================================= + +Introduction +============ +This document outlines the interface between the Linux SCSI mid level and +SCSI lower level drivers. Lower level drivers (LLDs) are variously called +host bus adapter (HBA) drivers and host drivers (HD). A "host" in this +context is a bridge between a computer IO bus (e.g. PCI or ISA) and a +single SCSI initiator port on a SCSI transport. An "initiator" port +(SCSI terminology, see SAM-3 at http://www.t10.org) sends SCSI commands +to "target" SCSI ports (e.g. disks). There can be many LLDs in a running +system, but only one per hardware type. Most LLDs can control one or more +SCSI HBAs. Some HBAs contain multiple hosts. + +In some cases the SCSI transport is an external bus that already has +its own subsystem in Linux (e.g. USB and ieee1394). In such cases the +SCSI subsystem LLD is a software bridge to the other driver subsystem. +Examples are the usb-storage driver (found in the drivers/usb/storage +directory) and the ieee1394/sbp2 driver (found in the drivers/ieee1394 +directory). + +For example, the aic7xxx LLD controls Adaptec SCSI parallel interface +(SPI) controllers based on that company's 7xxx chip series. The aic7xxx +LLD can be built into the kernel or loaded as a module. There can only be +one aic7xxx LLD running in a Linux system but it may be controlling many +HBAs. These HBAs might be either on PCI daughter-boards or built into +the motherboard (or both). Some aic7xxx based HBAs are dual controllers +and thus represent two hosts. Like most modern HBAs, each aic7xxx host +has its own PCI device address. [The one-to-one correspondence between +a SCSI host and a PCI device is common but not required (e.g. with +ISA adapters).] + +The SCSI mid level isolates an LLD from other layers such as the SCSI +upper layer drivers and the block layer. + +This version of the document roughly matches linux kernel version 2.6.8 . + +Documentation +============= +There is a SCSI documentation directory within the kernel source tree, +typically Documentation/scsi . Most documents are in plain +(i.e. ASCII) text. This file is named scsi_mid_low_api.txt and can be +found in that directory. A more recent copy of this document may be found +at http://web.archive.org/web/20070107183357rn_1/sg.torque.net/scsi/. +Many LLDs are documented there (e.g. aic7xxx.txt). The SCSI mid-level is +briefly described in scsi.txt which contains a url to a document +describing the SCSI subsystem in the lk 2.4 series. Two upper level +drivers have documents in that directory: st.txt (SCSI tape driver) and +scsi-generic.txt (for the sg driver). + +Some documentation (or urls) for LLDs may be found in the C source code +or in the same directory as the C source code. For example to find a url +about the USB mass storage driver see the +/usr/src/linux/drivers/usb/storage directory. + +Driver structure +================ +Traditionally an LLD for the SCSI subsystem has been at least two files in +the drivers/scsi directory. For example, a driver called "xyz" has a header +file "xyz.h" and a source file "xyz.c". [Actually there is no good reason +why this couldn't all be in one file; the header file is superfluous.] Some +drivers that have been ported to several operating systems have more than +two files. For example the aic7xxx driver has separate files for generic +and OS-specific code (e.g. FreeBSD and Linux). Such drivers tend to have +their own directory under the drivers/scsi directory. + +When a new LLD is being added to Linux, the following files (found in the +drivers/scsi directory) will need some attention: Makefile and Kconfig . +It is probably best to study how existing LLDs are organized. + +As the 2.5 series development kernels evolve into the 2.6 series +production series, changes are being introduced into this interface. An +example of this is driver initialization code where there are now 2 models +available. The older one, similar to what was found in the lk 2.4 series, +is based on hosts that are detected at HBA driver load time. This will be +referred to the "passive" initialization model. The newer model allows HBAs +to be hot plugged (and unplugged) during the lifetime of the LLD and will +be referred to as the "hotplug" initialization model. The newer model is +preferred as it can handle both traditional SCSI equipment that is +permanently connected as well as modern "SCSI" devices (e.g. USB or +IEEE 1394 connected digital cameras) that are hotplugged. Both +initialization models are discussed in the following sections. + +An LLD interfaces to the SCSI subsystem several ways: + + a) directly invoking functions supplied by the mid level + b) passing a set of function pointers to a registration function + supplied by the mid level. The mid level will then invoke these + functions at some point in the future. The LLD will supply + implementations of these functions. + c) direct access to instances of well known data structures maintained + by the mid level + +Those functions in group a) are listed in a section entitled "Mid level +supplied functions" below. + +Those functions in group b) are listed in a section entitled "Interface +functions" below. Their function pointers are placed in the members of +"struct scsi_host_template", an instance of which is passed to +scsi_host_alloc() [#]_. Those interface functions that the LLD does not +wish to supply should have NULL placed in the corresponding member of +struct scsi_host_template. Defining an instance of struct +scsi_host_template at file scope will cause NULL to be placed in function +pointer members not explicitly initialized. + +Those usages in group c) should be handled with care, especially in a +"hotplug" environment. LLDs should be aware of the lifetime of instances +that are shared with the mid level and other layers. + +All functions defined within an LLD and all data defined at file scope +should be static. For example the slave_alloc() function in an LLD +called "xxx" could be defined as +``static int xxx_slave_alloc(struct scsi_device * sdev) { /* code */ }`` + +.. [#] the scsi_host_alloc() function is a replacement for the rather vaguely + named scsi_register() function in most situations. + + +Hotplug initialization model +============================ +In this model an LLD controls when SCSI hosts are introduced and removed +from the SCSI subsystem. Hosts can be introduced as early as driver +initialization and removed as late as driver shutdown. Typically a driver +will respond to a sysfs probe() callback that indicates an HBA has been +detected. After confirming that the new device is one that the LLD wants +to control, the LLD will initialize the HBA and then register a new host +with the SCSI mid level. + +During LLD initialization the driver should register itself with the +appropriate IO bus on which it expects to find HBA(s) (e.g. the PCI bus). +This can probably be done via sysfs. Any driver parameters (especially +those that are writable after the driver is loaded) could also be +registered with sysfs at this point. The SCSI mid level first becomes +aware of an LLD when that LLD registers its first HBA. + +At some later time, the LLD becomes aware of an HBA and what follows +is a typical sequence of calls between the LLD and the mid level. +This example shows the mid level scanning the newly introduced HBA for 3 +scsi devices of which only the first 2 respond:: + + HBA PROBE: assume 2 SCSI devices found in scan + LLD mid level LLD + ===-------------------=========--------------------===------ + scsi_host_alloc() --> + scsi_add_host() ----> + scsi_scan_host() -------+ + | + slave_alloc() + slave_configure() --> scsi_change_queue_depth() + | + slave_alloc() + slave_configure() + | + slave_alloc() *** + slave_destroy() *** + + + *** For scsi devices that the mid level tries to scan but do not + respond, a slave_alloc(), slave_destroy() pair is called. + +If the LLD wants to adjust the default queue settings, it can invoke +scsi_change_queue_depth() in its slave_configure() routine. + +When an HBA is being removed it could be as part of an orderly shutdown +associated with the LLD module being unloaded (e.g. with the "rmmod" +command) or in response to a "hot unplug" indicated by sysfs()'s +remove() callback being invoked. In either case, the sequence is the +same:: + + HBA REMOVE: assume 2 SCSI devices attached + LLD mid level LLD + ===----------------------=========-----------------===------ + scsi_remove_host() ---------+ + | + slave_destroy() + slave_destroy() + scsi_host_put() + +It may be useful for a LLD to keep track of struct Scsi_Host instances +(a pointer is returned by scsi_host_alloc()). Such instances are "owned" +by the mid-level. struct Scsi_Host instances are freed from +scsi_host_put() when the reference count hits zero. + +Hot unplugging an HBA that controls a disk which is processing SCSI +commands on a mounted file system is an interesting situation. Reference +counting logic is being introduced into the mid level to cope with many +of the issues involved. See the section on reference counting below. + + +The hotplug concept may be extended to SCSI devices. Currently, when an +HBA is added, the scsi_scan_host() function causes a scan for SCSI devices +attached to the HBA's SCSI transport. On newer SCSI transports the HBA +may become aware of a new SCSI device _after_ the scan has completed. +An LLD can use this sequence to make the mid level aware of a SCSI device:: + + SCSI DEVICE hotplug + LLD mid level LLD + ===-------------------=========--------------------===------ + scsi_add_device() ------+ + | + slave_alloc() + slave_configure() [--> scsi_change_queue_depth()] + +In a similar fashion, an LLD may become aware that a SCSI device has been +removed (unplugged) or the connection to it has been interrupted. Some +existing SCSI transports (e.g. SPI) may not become aware that a SCSI +device has been removed until a subsequent SCSI command fails which will +probably cause that device to be set offline by the mid level. An LLD that +detects the removal of a SCSI device can instigate its removal from +upper layers with this sequence:: + + SCSI DEVICE hot unplug + LLD mid level LLD + ===----------------------=========-----------------===------ + scsi_remove_device() -------+ + | + slave_destroy() + +It may be useful for an LLD to keep track of struct scsi_device instances +(a pointer is passed as the parameter to slave_alloc() and +slave_configure() callbacks). Such instances are "owned" by the mid-level. +struct scsi_device instances are freed after slave_destroy(). + + +Reference Counting +================== +The Scsi_Host structure has had reference counting infrastructure added. +This effectively spreads the ownership of struct Scsi_Host instances +across the various SCSI layers which use them. Previously such instances +were exclusively owned by the mid level. LLDs would not usually need to +directly manipulate these reference counts but there may be some cases +where they do. + +There are 3 reference counting functions of interest associated with +struct Scsi_Host: + + - scsi_host_alloc(): + returns a pointer to new instance of struct + Scsi_Host which has its reference count ^^ set to 1 + + - scsi_host_get(): + adds 1 to the reference count of the given instance + + - scsi_host_put(): + decrements 1 from the reference count of the given + instance. If the reference count reaches 0 then the given instance + is freed + +The scsi_device structure has had reference counting infrastructure added. +This effectively spreads the ownership of struct scsi_device instances +across the various SCSI layers which use them. Previously such instances +were exclusively owned by the mid level. See the access functions declared +towards the end of include/scsi/scsi_device.h . If an LLD wants to keep +a copy of a pointer to a scsi_device instance it should use scsi_device_get() +to bump its reference count. When it is finished with the pointer it can +use scsi_device_put() to decrement its reference count (and potentially +delete it). + +.. Note:: + + struct Scsi_Host actually has 2 reference counts which are manipulated + in parallel by these functions. + + +Conventions +=========== +First, Linus Torvalds's thoughts on C coding style can be found in the +Documentation/process/coding-style.rst file. + +Next, there is a movement to "outlaw" typedefs introducing synonyms for +struct tags. Both can be still found in the SCSI subsystem, but +the typedefs have been moved to a single file, scsi_typedefs.h to +make their future removal easier, for example: +"typedef struct scsi_cmnd Scsi_Cmnd;" + +Also, most C99 enhancements are encouraged to the extent they are supported +by the relevant gcc compilers. So C99 style structure and array +initializers are encouraged where appropriate. Don't go too far, +VLAs are not properly supported yet. An exception to this is the use of +``//`` style comments; ``/*...*/`` comments are still preferred in Linux. + +Well written, tested and documented code, need not be re-formatted to +comply with the above conventions. For example, the aic7xxx driver +comes to Linux from FreeBSD and Adaptec's own labs. No doubt FreeBSD +and Adaptec have their own coding conventions. + + +Mid level supplied functions +============================ +These functions are supplied by the SCSI mid level for use by LLDs. +The names (i.e. entry points) of these functions are exported +so an LLD that is a module can access them. The kernel will +arrange for the SCSI mid level to be loaded and initialized before any LLD +is initialized. The functions below are listed alphabetically and their +names all start with ``scsi_``. + +Summary: + + - scsi_add_device - creates new scsi device (lu) instance + - scsi_add_host - perform sysfs registration and set up transport class + - scsi_change_queue_depth - change the queue depth on a SCSI device + - scsi_bios_ptable - return copy of block device's partition table + - scsi_block_requests - prevent further commands being queued to given host + - scsi_host_alloc - return a new scsi_host instance whose refcount==1 + - scsi_host_get - increments Scsi_Host instance's refcount + - scsi_host_put - decrements Scsi_Host instance's refcount (free if 0) + - scsi_register - create and register a scsi host adapter instance. + - scsi_remove_device - detach and remove a SCSI device + - scsi_remove_host - detach and remove all SCSI devices owned by host + - scsi_report_bus_reset - report scsi _bus_ reset observed + - scsi_scan_host - scan SCSI bus + - scsi_track_queue_full - track successive QUEUE_FULL events + - scsi_unblock_requests - allow further commands to be queued to given host + - scsi_unregister - [calls scsi_host_put()] + + +Details:: + + /** + * scsi_add_device - creates new scsi device (lu) instance + * @shost: pointer to scsi host instance + * @channel: channel number (rarely other than 0) + * @id: target id number + * @lun: logical unit number + * + * Returns pointer to new struct scsi_device instance or + * ERR_PTR(-ENODEV) (or some other bent pointer) if something is + * wrong (e.g. no lu responds at given address) + * + * Might block: yes + * + * Notes: This call is usually performed internally during a scsi + * bus scan when an HBA is added (i.e. scsi_scan_host()). So it + * should only be called if the HBA becomes aware of a new scsi + * device (lu) after scsi_scan_host() has completed. If successful + * this call can lead to slave_alloc() and slave_configure() callbacks + * into the LLD. + * + * Defined in: drivers/scsi/scsi_scan.c + **/ + struct scsi_device * scsi_add_device(struct Scsi_Host *shost, + unsigned int channel, + unsigned int id, unsigned int lun) + + + /** + * scsi_add_host - perform sysfs registration and set up transport class + * @shost: pointer to scsi host instance + * @dev: pointer to struct device of type scsi class + * + * Returns 0 on success, negative errno of failure (e.g. -ENOMEM) + * + * Might block: no + * + * Notes: Only required in "hotplug initialization model" after a + * successful call to scsi_host_alloc(). This function does not + * scan the bus; this can be done by calling scsi_scan_host() or + * in some other transport-specific way. The LLD must set up + * the transport template before calling this function and may only + * access the transport class data after this function has been called. + * + * Defined in: drivers/scsi/hosts.c + **/ + int scsi_add_host(struct Scsi_Host *shost, struct device * dev) + + + /** + * scsi_change_queue_depth - allow LLD to change queue depth on a SCSI device + * @sdev: pointer to SCSI device to change queue depth on + * @tags Number of tags allowed if tagged queuing enabled, + * or number of commands the LLD can queue up + * in non-tagged mode (as per cmd_per_lun). + * + * Returns nothing + * + * Might block: no + * + * Notes: Can be invoked any time on a SCSI device controlled by this + * LLD. [Specifically during and after slave_configure() and prior to + * slave_destroy().] Can safely be invoked from interrupt code. + * + * Defined in: drivers/scsi/scsi.c [see source code for more notes] + * + **/ + int scsi_change_queue_depth(struct scsi_device *sdev, int tags) + + + /** + * scsi_bios_ptable - return copy of block device's partition table + * @dev: pointer to block device + * + * Returns pointer to partition table, or NULL for failure + * + * Might block: yes + * + * Notes: Caller owns memory returned (free with kfree() ) + * + * Defined in: drivers/scsi/scsicam.c + **/ + unsigned char *scsi_bios_ptable(struct block_device *dev) + + + /** + * scsi_block_requests - prevent further commands being queued to given host + * + * @shost: pointer to host to block commands on + * + * Returns nothing + * + * Might block: no + * + * Notes: There is no timer nor any other means by which the requests + * get unblocked other than the LLD calling scsi_unblock_requests(). + * + * Defined in: drivers/scsi/scsi_lib.c + **/ + void scsi_block_requests(struct Scsi_Host * shost) + + + /** + * scsi_host_alloc - create a scsi host adapter instance and perform basic + * initialization. + * @sht: pointer to scsi host template + * @privsize: extra bytes to allocate in hostdata array (which is the + * last member of the returned Scsi_Host instance) + * + * Returns pointer to new Scsi_Host instance or NULL on failure + * + * Might block: yes + * + * Notes: When this call returns to the LLD, the SCSI bus scan on + * this host has _not_ yet been done. + * The hostdata array (by default zero length) is a per host scratch + * area for the LLD's exclusive use. + * Both associated refcounting objects have their refcount set to 1. + * Full registration (in sysfs) and a bus scan are performed later when + * scsi_add_host() and scsi_scan_host() are called. + * + * Defined in: drivers/scsi/hosts.c . + **/ + struct Scsi_Host * scsi_host_alloc(struct scsi_host_template * sht, + int privsize) + + + /** + * scsi_host_get - increment Scsi_Host instance refcount + * @shost: pointer to struct Scsi_Host instance + * + * Returns nothing + * + * Might block: currently may block but may be changed to not block + * + * Notes: Actually increments the counts in two sub-objects + * + * Defined in: drivers/scsi/hosts.c + **/ + void scsi_host_get(struct Scsi_Host *shost) + + + /** + * scsi_host_put - decrement Scsi_Host instance refcount, free if 0 + * @shost: pointer to struct Scsi_Host instance + * + * Returns nothing + * + * Might block: currently may block but may be changed to not block + * + * Notes: Actually decrements the counts in two sub-objects. If the + * latter refcount reaches 0, the Scsi_Host instance is freed. + * The LLD need not worry exactly when the Scsi_Host instance is + * freed, it just shouldn't access the instance after it has balanced + * out its refcount usage. + * + * Defined in: drivers/scsi/hosts.c + **/ + void scsi_host_put(struct Scsi_Host *shost) + + + /** + * scsi_register - create and register a scsi host adapter instance. + * @sht: pointer to scsi host template + * @privsize: extra bytes to allocate in hostdata array (which is the + * last member of the returned Scsi_Host instance) + * + * Returns pointer to new Scsi_Host instance or NULL on failure + * + * Might block: yes + * + * Notes: When this call returns to the LLD, the SCSI bus scan on + * this host has _not_ yet been done. + * The hostdata array (by default zero length) is a per host scratch + * area for the LLD. + * + * Defined in: drivers/scsi/hosts.c . + **/ + struct Scsi_Host * scsi_register(struct scsi_host_template * sht, + int privsize) + + + /** + * scsi_remove_device - detach and remove a SCSI device + * @sdev: a pointer to a scsi device instance + * + * Returns value: 0 on success, -EINVAL if device not attached + * + * Might block: yes + * + * Notes: If an LLD becomes aware that a scsi device (lu) has + * been removed but its host is still present then it can request + * the removal of that scsi device. If successful this call will + * lead to the slave_destroy() callback being invoked. sdev is an + * invalid pointer after this call. + * + * Defined in: drivers/scsi/scsi_sysfs.c . + **/ + int scsi_remove_device(struct scsi_device *sdev) + + + /** + * scsi_remove_host - detach and remove all SCSI devices owned by host + * @shost: a pointer to a scsi host instance + * + * Returns value: 0 on success, 1 on failure (e.g. LLD busy ??) + * + * Might block: yes + * + * Notes: Should only be invoked if the "hotplug initialization + * model" is being used. It should be called _prior_ to + * scsi_unregister(). + * + * Defined in: drivers/scsi/hosts.c . + **/ + int scsi_remove_host(struct Scsi_Host *shost) + + + /** + * scsi_report_bus_reset - report scsi _bus_ reset observed + * @shost: a pointer to a scsi host involved + * @channel: channel (within) host on which scsi bus reset occurred + * + * Returns nothing + * + * Might block: no + * + * Notes: This only needs to be called if the reset is one which + * originates from an unknown location. Resets originated by the + * mid level itself don't need to call this, but there should be + * no harm. The main purpose of this is to make sure that a + * CHECK_CONDITION is properly treated. + * + * Defined in: drivers/scsi/scsi_error.c . + **/ + void scsi_report_bus_reset(struct Scsi_Host * shost, int channel) + + + /** + * scsi_scan_host - scan SCSI bus + * @shost: a pointer to a scsi host instance + * + * Might block: yes + * + * Notes: Should be called after scsi_add_host() + * + * Defined in: drivers/scsi/scsi_scan.c + **/ + void scsi_scan_host(struct Scsi_Host *shost) + + + /** + * scsi_track_queue_full - track successive QUEUE_FULL events on given + * device to determine if and when there is a need + * to adjust the queue depth on the device. + * @sdev: pointer to SCSI device instance + * @depth: Current number of outstanding SCSI commands on this device, + * not counting the one returned as QUEUE_FULL. + * + * Returns 0 - no change needed + * >0 - adjust queue depth to this new depth + * -1 - drop back to untagged operation using host->cmd_per_lun + * as the untagged command depth + * + * Might block: no + * + * Notes: LLDs may call this at any time and we will do "The Right + * Thing"; interrupt context safe. + * + * Defined in: drivers/scsi/scsi.c . + **/ + int scsi_track_queue_full(struct scsi_device *sdev, int depth) + + + /** + * scsi_unblock_requests - allow further commands to be queued to given host + * + * @shost: pointer to host to unblock commands on + * + * Returns nothing + * + * Might block: no + * + * Defined in: drivers/scsi/scsi_lib.c . + **/ + void scsi_unblock_requests(struct Scsi_Host * shost) + + + /** + * scsi_unregister - unregister and free memory used by host instance + * @shp: pointer to scsi host instance to unregister. + * + * Returns nothing + * + * Might block: no + * + * Notes: Should not be invoked if the "hotplug initialization + * model" is being used. Called internally by exit_this_scsi_driver() + * in the "passive initialization model". Hence a LLD has no need to + * call this function directly. + * + * Defined in: drivers/scsi/hosts.c . + **/ + void scsi_unregister(struct Scsi_Host * shp) + + + + +Interface Functions +=================== +Interface functions are supplied (defined) by LLDs and their function +pointers are placed in an instance of struct scsi_host_template which +is passed to scsi_host_alloc() [or scsi_register() / init_this_scsi_driver()]. +Some are mandatory. Interface functions should be declared static. The +accepted convention is that driver "xyz" will declare its slave_configure() +function as:: + + static int xyz_slave_configure(struct scsi_device * sdev); + +and so forth for all interface functions listed below. + +A pointer to this function should be placed in the 'slave_configure' member +of a "struct scsi_host_template" instance. A pointer to such an instance +should be passed to the mid level's scsi_host_alloc() [or scsi_register() / +init_this_scsi_driver()]. + +The interface functions are also described in the include/scsi/scsi_host.h +file immediately above their definition point in "struct scsi_host_template". +In some cases more detail is given in scsi_host.h than below. + +The interface functions are listed below in alphabetical order. + +Summary: + + - bios_param - fetch head, sector, cylinder info for a disk + - eh_timed_out - notify the host that a command timer expired + - eh_abort_handler - abort given command + - eh_bus_reset_handler - issue SCSI bus reset + - eh_device_reset_handler - issue SCSI device reset + - eh_host_reset_handler - reset host (host bus adapter) + - info - supply information about given host + - ioctl - driver can respond to ioctls + - proc_info - supports /proc/scsi/{driver_name}/{host_no} + - queuecommand - queue scsi command, invoke 'done' on completion + - slave_alloc - prior to any commands being sent to a new device + - slave_configure - driver fine tuning for given device after attach + - slave_destroy - given device is about to be shut down + + +Details:: + + /** + * bios_param - fetch head, sector, cylinder info for a disk + * @sdev: pointer to scsi device context (defined in + * include/scsi/scsi_device.h) + * @bdev: pointer to block device context (defined in fs.h) + * @capacity: device size (in 512 byte sectors) + * @params: three element array to place output: + * params[0] number of heads (max 255) + * params[1] number of sectors (max 63) + * params[2] number of cylinders + * + * Return value is ignored + * + * Locks: none + * + * Calling context: process (sd) + * + * Notes: an arbitrary geometry (based on READ CAPACITY) is used + * if this function is not provided. The params array is + * pre-initialized with made up values just in case this function + * doesn't output anything. + * + * Optionally defined in: LLD + **/ + int bios_param(struct scsi_device * sdev, struct block_device *bdev, + sector_t capacity, int params[3]) + + + /** + * eh_timed_out - The timer for the command has just fired + * @scp: identifies command timing out + * + * Returns: + * + * EH_HANDLED: I fixed the error, please complete the command + * EH_RESET_TIMER: I need more time, reset the timer and + * begin counting again + * EH_NOT_HANDLED Begin normal error recovery + * + * + * Locks: None held + * + * Calling context: interrupt + * + * Notes: This is to give the LLD an opportunity to do local recovery. + * This recovery is limited to determining if the outstanding command + * will ever complete. You may not abort and restart the command from + * this callback. + * + * Optionally defined in: LLD + **/ + int eh_timed_out(struct scsi_cmnd * scp) + + + /** + * eh_abort_handler - abort command associated with scp + * @scp: identifies command to be aborted + * + * Returns SUCCESS if command aborted else FAILED + * + * Locks: None held + * + * Calling context: kernel thread + * + * Notes: If 'no_async_abort' is defined this callback + * will be invoked from scsi_eh thread. No other commands + * will then be queued on current host during eh. + * Otherwise it will be called whenever scsi_times_out() + * is called due to a command timeout. + * + * Optionally defined in: LLD + **/ + int eh_abort_handler(struct scsi_cmnd * scp) + + + /** + * eh_bus_reset_handler - issue SCSI bus reset + * @scp: SCSI bus that contains this device should be reset + * + * Returns SUCCESS if command aborted else FAILED + * + * Locks: None held + * + * Calling context: kernel thread + * + * Notes: Invoked from scsi_eh thread. No other commands will be + * queued on current host during eh. + * + * Optionally defined in: LLD + **/ + int eh_bus_reset_handler(struct scsi_cmnd * scp) + + + /** + * eh_device_reset_handler - issue SCSI device reset + * @scp: identifies SCSI device to be reset + * + * Returns SUCCESS if command aborted else FAILED + * + * Locks: None held + * + * Calling context: kernel thread + * + * Notes: Invoked from scsi_eh thread. No other commands will be + * queued on current host during eh. + * + * Optionally defined in: LLD + **/ + int eh_device_reset_handler(struct scsi_cmnd * scp) + + + /** + * eh_host_reset_handler - reset host (host bus adapter) + * @scp: SCSI host that contains this device should be reset + * + * Returns SUCCESS if command aborted else FAILED + * + * Locks: None held + * + * Calling context: kernel thread + * + * Notes: Invoked from scsi_eh thread. No other commands will be + * queued on current host during eh. + * With the default eh_strategy in place, if none of the _abort_, + * _device_reset_, _bus_reset_ or this eh handler function are + * defined (or they all return FAILED) then the device in question + * will be set offline whenever eh is invoked. + * + * Optionally defined in: LLD + **/ + int eh_host_reset_handler(struct scsi_cmnd * scp) + + + /** + * info - supply information about given host: driver name plus data + * to distinguish given host + * @shp: host to supply information about + * + * Return ASCII null terminated string. [This driver is assumed to + * manage the memory pointed to and maintain it, typically for the + * lifetime of this host.] + * + * Locks: none + * + * Calling context: process + * + * Notes: Often supplies PCI or ISA information such as IO addresses + * and interrupt numbers. If not supplied struct Scsi_Host::name used + * instead. It is assumed the returned information fits on one line + * (i.e. does not included embedded newlines). + * The SCSI_IOCTL_PROBE_HOST ioctl yields the string returned by this + * function (or struct Scsi_Host::name if this function is not + * available). + * In a similar manner, init_this_scsi_driver() outputs to the console + * each host's "info" (or name) for the driver it is registering. + * Also if proc_info() is not supplied, the output of this function + * is used instead. + * + * Optionally defined in: LLD + **/ + const char * info(struct Scsi_Host * shp) + + + /** + * ioctl - driver can respond to ioctls + * @sdp: device that ioctl was issued for + * @cmd: ioctl number + * @arg: pointer to read or write data from. Since it points to + * user space, should use appropriate kernel functions + * (e.g. copy_from_user() ). In the Unix style this argument + * can also be viewed as an unsigned long. + * + * Returns negative "errno" value when there is a problem. 0 or a + * positive value indicates success and is returned to the user space. + * + * Locks: none + * + * Calling context: process + * + * Notes: The SCSI subsystem uses a "trickle down" ioctl model. + * The user issues an ioctl() against an upper level driver + * (e.g. /dev/sdc) and if the upper level driver doesn't recognize + * the 'cmd' then it is passed to the SCSI mid level. If the SCSI + * mid level does not recognize it, then the LLD that controls + * the device receives the ioctl. According to recent Unix standards + * unsupported ioctl() 'cmd' numbers should return -ENOTTY. + * + * Optionally defined in: LLD + **/ + int ioctl(struct scsi_device *sdp, int cmd, void *arg) + + + /** + * proc_info - supports /proc/scsi/{driver_name}/{host_no} + * @buffer: anchor point to output to (0==writeto1_read0) or fetch from + * (1==writeto1_read0). + * @start: where "interesting" data is written to. Ignored when + * 1==writeto1_read0. + * @offset: offset within buffer 0==writeto1_read0 is actually + * interested in. Ignored when 1==writeto1_read0 . + * @length: maximum (or actual) extent of buffer + * @host_no: host number of interest (struct Scsi_Host::host_no) + * @writeto1_read0: 1 -> data coming from user space towards driver + * (e.g. "echo some_string > /proc/scsi/xyz/2") + * 0 -> user what data from this driver + * (e.g. "cat /proc/scsi/xyz/2") + * + * Returns length when 1==writeto1_read0. Otherwise number of chars + * output to buffer past offset. + * + * Locks: none held + * + * Calling context: process + * + * Notes: Driven from scsi_proc.c which interfaces to proc_fs. proc_fs + * support can now be configured out of the scsi subsystem. + * + * Optionally defined in: LLD + **/ + int proc_info(char * buffer, char ** start, off_t offset, + int length, int host_no, int writeto1_read0) + + + /** + * queuecommand - queue scsi command, invoke scp->scsi_done on completion + * @shost: pointer to the scsi host object + * @scp: pointer to scsi command object + * + * Returns 0 on success. + * + * If there's a failure, return either: + * + * SCSI_MLQUEUE_DEVICE_BUSY if the device queue is full, or + * SCSI_MLQUEUE_HOST_BUSY if the entire host queue is full + * + * On both of these returns, the mid-layer will requeue the I/O + * + * - if the return is SCSI_MLQUEUE_DEVICE_BUSY, only that particular + * device will be paused, and it will be unpaused when a command to + * the device returns (or after a brief delay if there are no more + * outstanding commands to it). Commands to other devices continue + * to be processed normally. + * + * - if the return is SCSI_MLQUEUE_HOST_BUSY, all I/O to the host + * is paused and will be unpaused when any command returns from + * the host (or after a brief delay if there are no outstanding + * commands to the host). + * + * For compatibility with earlier versions of queuecommand, any + * other return value is treated the same as + * SCSI_MLQUEUE_HOST_BUSY. + * + * Other types of errors that are detected immediately may be + * flagged by setting scp->result to an appropriate value, + * invoking the scp->scsi_done callback, and then returning 0 + * from this function. If the command is not performed + * immediately (and the LLD is starting (or will start) the given + * command) then this function should place 0 in scp->result and + * return 0. + * + * Command ownership. If the driver returns zero, it owns the + * command and must take responsibility for ensuring the + * scp->scsi_done callback is executed. Note: the driver may + * call scp->scsi_done before returning zero, but after it has + * called scp->scsi_done, it may not return any value other than + * zero. If the driver makes a non-zero return, it must not + * execute the command's scsi_done callback at any time. + * + * Locks: up to and including 2.6.36, struct Scsi_Host::host_lock + * held on entry (with "irqsave") and is expected to be + * held on return. From 2.6.37 onwards, queuecommand is + * called without any locks held. + * + * Calling context: in interrupt (soft irq) or process context + * + * Notes: This function should be relatively fast. Normally it + * will not wait for IO to complete. Hence the scp->scsi_done + * callback is invoked (often directly from an interrupt service + * routine) some time after this function has returned. In some + * cases (e.g. pseudo adapter drivers that manufacture the + * response to a SCSI INQUIRY) the scp->scsi_done callback may be + * invoked before this function returns. If the scp->scsi_done + * callback is not invoked within a certain period the SCSI mid + * level will commence error processing. If a status of CHECK + * CONDITION is placed in "result" when the scp->scsi_done + * callback is invoked, then the LLD driver should perform + * autosense and fill in the struct scsi_cmnd::sense_buffer + * array. The scsi_cmnd::sense_buffer array is zeroed prior to + * the mid level queuing a command to an LLD. + * + * Defined in: LLD + **/ + int queuecommand(struct Scsi_Host *shost, struct scsi_cmnd * scp) + + + /** + * slave_alloc - prior to any commands being sent to a new device + * (i.e. just prior to scan) this call is made + * @sdp: pointer to new device (about to be scanned) + * + * Returns 0 if ok. Any other return is assumed to be an error and + * the device is ignored. + * + * Locks: none + * + * Calling context: process + * + * Notes: Allows the driver to allocate any resources for a device + * prior to its initial scan. The corresponding scsi device may not + * exist but the mid level is just about to scan for it (i.e. send + * and INQUIRY command plus ...). If a device is found then + * slave_configure() will be called while if a device is not found + * slave_destroy() is called. + * For more details see the include/scsi/scsi_host.h file. + * + * Optionally defined in: LLD + **/ + int slave_alloc(struct scsi_device *sdp) + + + /** + * slave_configure - driver fine tuning for given device just after it + * has been first scanned (i.e. it responded to an + * INQUIRY) + * @sdp: device that has just been attached + * + * Returns 0 if ok. Any other return is assumed to be an error and + * the device is taken offline. [offline devices will _not_ have + * slave_destroy() called on them so clean up resources.] + * + * Locks: none + * + * Calling context: process + * + * Notes: Allows the driver to inspect the response to the initial + * INQUIRY done by the scanning code and take appropriate action. + * For more details see the include/scsi/scsi_host.h file. + * + * Optionally defined in: LLD + **/ + int slave_configure(struct scsi_device *sdp) + + + /** + * slave_destroy - given device is about to be shut down. All + * activity has ceased on this device. + * @sdp: device that is about to be shut down + * + * Returns nothing + * + * Locks: none + * + * Calling context: process + * + * Notes: Mid level structures for given device are still in place + * but are about to be torn down. Any per device resources allocated + * by this driver for given device should be freed now. No further + * commands will be sent for this sdp instance. [However the device + * could be re-attached in the future in which case a new instance + * of struct scsi_device would be supplied by future slave_alloc() + * and slave_configure() calls.] + * + * Optionally defined in: LLD + **/ + void slave_destroy(struct scsi_device *sdp) + + + +Data Structures +=============== +struct scsi_host_template +------------------------- +There is one "struct scsi_host_template" instance per LLD [#]_. It is +typically initialized as a file scope static in a driver's header file. That +way members that are not explicitly initialized will be set to 0 or NULL. +Member of interest: + + name + - name of driver (may contain spaces, please limit to + less than 80 characters) + + proc_name + - name used in "/proc/scsi/<proc_name>/<host_no>" and + by sysfs in one of its "drivers" directories. Hence + "proc_name" should only contain characters acceptable + to a Unix file name. + + ``(*queuecommand)()`` + - primary callback that the mid level uses to inject + SCSI commands into an LLD. + +The structure is defined and commented in include/scsi/scsi_host.h + +.. [#] In extreme situations a single driver may have several instances + if it controls several different classes of hardware (e.g. an LLD + that handles both ISA and PCI cards and has a separate instance of + struct scsi_host_template for each class). + +struct Scsi_Host +---------------- +There is one struct Scsi_Host instance per host (HBA) that an LLD +controls. The struct Scsi_Host structure has many members in common +with "struct scsi_host_template". When a new struct Scsi_Host instance +is created (in scsi_host_alloc() in hosts.c) those common members are +initialized from the driver's struct scsi_host_template instance. Members +of interest: + + host_no + - system wide unique number that is used for identifying + this host. Issued in ascending order from 0. + can_queue + - must be greater than 0; do not send more than can_queue + commands to the adapter. + this_id + - scsi id of host (scsi initiator) or -1 if not known + sg_tablesize + - maximum scatter gather elements allowed by host. + Set this to SG_ALL or less to avoid chained SG lists. + Must be at least 1. + max_sectors + - maximum number of sectors (usually 512 bytes) allowed + in a single SCSI command. The default value of 0 leads + to a setting of SCSI_DEFAULT_MAX_SECTORS (defined in + scsi_host.h) which is currently set to 1024. So for a + disk the maximum transfer size is 512 KB when max_sectors + is not defined. Note that this size may not be sufficient + for disk firmware uploads. + cmd_per_lun + - maximum number of commands that can be queued on devices + controlled by the host. Overridden by LLD calls to + scsi_change_queue_depth(). + unchecked_isa_dma + - 1=>only use bottom 16 MB of ram (ISA DMA addressing + restriction), 0=>can use full 32 bit (or better) DMA + address space + no_async_abort + - 1=>Asynchronous aborts are not supported + - 0=>Timed-out commands will be aborted asynchronously + hostt + - pointer to driver's struct scsi_host_template from which + this struct Scsi_Host instance was spawned + hostt->proc_name + - name of LLD. This is the driver name that sysfs uses + transportt + - pointer to driver's struct scsi_transport_template instance + (if any). FC and SPI transports currently supported. + sh_list + - a double linked list of pointers to all struct Scsi_Host + instances (currently ordered by ascending host_no) + my_devices + - a double linked list of pointers to struct scsi_device + instances that belong to this host. + hostdata[0] + - area reserved for LLD at end of struct Scsi_Host. Size + is set by the second argument (named 'xtr_bytes') to + scsi_host_alloc() or scsi_register(). + vendor_id + - a unique value that identifies the vendor supplying + the LLD for the Scsi_Host. Used most often in validating + vendor-specific message requests. Value consists of an + identifier type and a vendor-specific value. + See scsi_netlink.h for a description of valid formats. + +The scsi_host structure is defined in include/scsi/scsi_host.h + +struct scsi_device +------------------ +Generally, there is one instance of this structure for each SCSI logical unit +on a host. Scsi devices connected to a host are uniquely identified by a +channel number, target id and logical unit number (lun). +The structure is defined in include/scsi/scsi_device.h + +struct scsi_cmnd +---------------- +Instances of this structure convey SCSI commands to the LLD and responses +back to the mid level. The SCSI mid level will ensure that no more SCSI +commands become queued against the LLD than are indicated by +scsi_change_queue_depth() (or struct Scsi_Host::cmd_per_lun). There will +be at least one instance of struct scsi_cmnd available for each SCSI device. +Members of interest: + + cmnd + - array containing SCSI command + cmnd_len + - length (in bytes) of SCSI command + sc_data_direction + - direction of data transfer in data phase. See + "enum dma_data_direction" in include/linux/dma-mapping.h + request_bufflen + - number of data bytes to transfer (0 if no data phase) + use_sg + - ==0 -> no scatter gather list, hence transfer data + to/from request_buffer + - >0 -> scatter gather list (actually an array) in + request_buffer with use_sg elements + request_buffer + - either contains data buffer or scatter gather list + depending on the setting of use_sg. Scatter gather + elements are defined by 'struct scatterlist' found + in include/linux/scatterlist.h . + done + - function pointer that should be invoked by LLD when the + SCSI command is completed (successfully or otherwise). + Should only be called by an LLD if the LLD has accepted + the command (i.e. queuecommand() returned or will return + 0). The LLD may invoke 'done' prior to queuecommand() + finishing. + result + - should be set by LLD prior to calling 'done'. A value + of 0 implies a successfully completed command (and all + data (if any) has been transferred to or from the SCSI + target device). 'result' is a 32 bit unsigned integer that + can be viewed as 4 related bytes. The SCSI status value is + in the LSB. See include/scsi/scsi.h status_byte(), + msg_byte(), host_byte() and driver_byte() macros and + related constants. + sense_buffer + - an array (maximum size: SCSI_SENSE_BUFFERSIZE bytes) that + should be written when the SCSI status (LSB of 'result') + is set to CHECK_CONDITION (2). When CHECK_CONDITION is + set, if the top nibble of sense_buffer[0] has the value 7 + then the mid level will assume the sense_buffer array + contains a valid SCSI sense buffer; otherwise the mid + level will issue a REQUEST_SENSE SCSI command to + retrieve the sense buffer. The latter strategy is error + prone in the presence of command queuing so the LLD should + always "auto-sense". + device + - pointer to scsi_device object that this command is + associated with. + resid + - an LLD should set this signed integer to the requested + transfer length (i.e. 'request_bufflen') less the number + of bytes that are actually transferred. 'resid' is + preset to 0 so an LLD can ignore it if it cannot detect + underruns (overruns should be rare). If possible an LLD + should set 'resid' prior to invoking 'done'. The most + interesting case is data transfers from a SCSI target + device (e.g. READs) that underrun. + underflow + - LLD should place (DID_ERROR << 16) in 'result' if + actual number of bytes transferred is less than this + figure. Not many LLDs implement this check and some that + do just output an error message to the log rather than + report a DID_ERROR. Better for an LLD to implement + 'resid'. + +It is recommended that a LLD set 'resid' on data transfers from a SCSI +target device (e.g. READs). It is especially important that 'resid' is set +when such data transfers have sense keys of MEDIUM ERROR and HARDWARE ERROR +(and possibly RECOVERED ERROR). In these cases if a LLD is in doubt how much +data has been received then the safest approach is to indicate no bytes have +been received. For example: to indicate that no valid data has been received +a LLD might use these helpers:: + + scsi_set_resid(SCpnt, scsi_bufflen(SCpnt)); + +where 'SCpnt' is a pointer to a scsi_cmnd object. To indicate only three 512 +bytes blocks has been received 'resid' could be set like this:: + + scsi_set_resid(SCpnt, scsi_bufflen(SCpnt) - (3 * 512)); + +The scsi_cmnd structure is defined in include/scsi/scsi_cmnd.h + + +Locks +===== +Each struct Scsi_Host instance has a spin_lock called struct +Scsi_Host::default_lock which is initialized in scsi_host_alloc() [found in +hosts.c]. Within the same function the struct Scsi_Host::host_lock pointer +is initialized to point at default_lock. Thereafter lock and unlock +operations performed by the mid level use the struct Scsi_Host::host_lock +pointer. Previously drivers could override the host_lock pointer but +this is not allowed anymore. + + +Autosense +========= +Autosense (or auto-sense) is defined in the SAM-2 document as "the +automatic return of sense data to the application client coincident +with the completion of a SCSI command" when a status of CHECK CONDITION +occurs. LLDs should perform autosense. This should be done when the LLD +detects a CHECK CONDITION status by either: + + a) instructing the SCSI protocol (e.g. SCSI Parallel Interface (SPI)) + to perform an extra data in phase on such responses + b) or, the LLD issuing a REQUEST SENSE command itself + +Either way, when a status of CHECK CONDITION is detected, the mid level +decides whether the LLD has performed autosense by checking struct +scsi_cmnd::sense_buffer[0] . If this byte has an upper nibble of 7 (or 0xf) +then autosense is assumed to have taken place. If it has another value (and +this byte is initialized to 0 before each command) then the mid level will +issue a REQUEST SENSE command. + +In the presence of queued commands the "nexus" that maintains sense +buffer data from the command that failed until a following REQUEST SENSE +may get out of synchronization. This is why it is best for the LLD +to perform autosense. + + +Changes since lk 2.4 series +=========================== +io_request_lock has been replaced by several finer grained locks. The lock +relevant to LLDs is struct Scsi_Host::host_lock and there is +one per SCSI host. + +The older error handling mechanism has been removed. This means the +LLD interface functions abort() and reset() have been removed. +The struct scsi_host_template::use_new_eh_code flag has been removed. + +In the 2.4 series the SCSI subsystem configuration descriptions were +aggregated with the configuration descriptions from all other Linux +subsystems in the Documentation/Configure.help file. In the 2.6 series, +the SCSI subsystem now has its own (much smaller) drivers/scsi/Kconfig +file that contains both configuration and help information. + +struct SHT has been renamed to struct scsi_host_template. + +Addition of the "hotplug initialization model" and many extra functions +to support it. + + +Credits +======= +The following people have contributed to this document: + + - Mike Anderson <andmike at us dot ibm dot com> + - James Bottomley <James dot Bottomley at hansenpartnership dot com> + - Patrick Mansfield <patmans at us dot ibm dot com> + - Christoph Hellwig <hch at infradead dot org> + - Doug Ledford <dledford at redhat dot com> + - Andries Brouwer <Andries dot Brouwer at cwi dot nl> + - Randy Dunlap <rdunlap at xenotime dot net> + - Alan Stern <stern at rowland dot harvard dot edu> + + +Douglas Gilbert +dgilbert at interlog dot com + +21st September 2004 diff --git a/Documentation/scsi/scsi_mid_low_api.txt b/Documentation/scsi/scsi_mid_low_api.txt deleted file mode 100644 index 537f04728487..000000000000 --- a/Documentation/scsi/scsi_mid_low_api.txt +++ /dev/null @@ -1,1259 +0,0 @@ - Linux Kernel 2.6 series - SCSI mid_level - lower_level driver interface - ============================================= - -Introduction -============ -This document outlines the interface between the Linux SCSI mid level and -SCSI lower level drivers. Lower level drivers (LLDs) are variously called -host bus adapter (HBA) drivers and host drivers (HD). A "host" in this -context is a bridge between a computer IO bus (e.g. PCI or ISA) and a -single SCSI initiator port on a SCSI transport. An "initiator" port -(SCSI terminology, see SAM-3 at http://www.t10.org) sends SCSI commands -to "target" SCSI ports (e.g. disks). There can be many LLDs in a running -system, but only one per hardware type. Most LLDs can control one or more -SCSI HBAs. Some HBAs contain multiple hosts. - -In some cases the SCSI transport is an external bus that already has -its own subsystem in Linux (e.g. USB and ieee1394). In such cases the -SCSI subsystem LLD is a software bridge to the other driver subsystem. -Examples are the usb-storage driver (found in the drivers/usb/storage -directory) and the ieee1394/sbp2 driver (found in the drivers/ieee1394 -directory). - -For example, the aic7xxx LLD controls Adaptec SCSI parallel interface -(SPI) controllers based on that company's 7xxx chip series. The aic7xxx -LLD can be built into the kernel or loaded as a module. There can only be -one aic7xxx LLD running in a Linux system but it may be controlling many -HBAs. These HBAs might be either on PCI daughter-boards or built into -the motherboard (or both). Some aic7xxx based HBAs are dual controllers -and thus represent two hosts. Like most modern HBAs, each aic7xxx host -has its own PCI device address. [The one-to-one correspondence between -a SCSI host and a PCI device is common but not required (e.g. with -ISA adapters).] - -The SCSI mid level isolates an LLD from other layers such as the SCSI -upper layer drivers and the block layer. - -This version of the document roughly matches linux kernel version 2.6.8 . - -Documentation -============= -There is a SCSI documentation directory within the kernel source tree, -typically Documentation/scsi . Most documents are in plain -(i.e. ASCII) text. This file is named scsi_mid_low_api.txt and can be -found in that directory. A more recent copy of this document may be found -at http://web.archive.org/web/20070107183357rn_1/sg.torque.net/scsi/. -Many LLDs are documented there (e.g. aic7xxx.txt). The SCSI mid-level is -briefly described in scsi.txt which contains a url to a document -describing the SCSI subsystem in the lk 2.4 series. Two upper level -drivers have documents in that directory: st.txt (SCSI tape driver) and -scsi-generic.txt (for the sg driver). - -Some documentation (or urls) for LLDs may be found in the C source code -or in the same directory as the C source code. For example to find a url -about the USB mass storage driver see the -/usr/src/linux/drivers/usb/storage directory. - -Driver structure -================ -Traditionally an LLD for the SCSI subsystem has been at least two files in -the drivers/scsi directory. For example, a driver called "xyz" has a header -file "xyz.h" and a source file "xyz.c". [Actually there is no good reason -why this couldn't all be in one file; the header file is superfluous.] Some -drivers that have been ported to several operating systems have more than -two files. For example the aic7xxx driver has separate files for generic -and OS-specific code (e.g. FreeBSD and Linux). Such drivers tend to have -their own directory under the drivers/scsi directory. - -When a new LLD is being added to Linux, the following files (found in the -drivers/scsi directory) will need some attention: Makefile and Kconfig . -It is probably best to study how existing LLDs are organized. - -As the 2.5 series development kernels evolve into the 2.6 series -production series, changes are being introduced into this interface. An -example of this is driver initialization code where there are now 2 models -available. The older one, similar to what was found in the lk 2.4 series, -is based on hosts that are detected at HBA driver load time. This will be -referred to the "passive" initialization model. The newer model allows HBAs -to be hot plugged (and unplugged) during the lifetime of the LLD and will -be referred to as the "hotplug" initialization model. The newer model is -preferred as it can handle both traditional SCSI equipment that is -permanently connected as well as modern "SCSI" devices (e.g. USB or -IEEE 1394 connected digital cameras) that are hotplugged. Both -initialization models are discussed in the following sections. - -An LLD interfaces to the SCSI subsystem several ways: - a) directly invoking functions supplied by the mid level - b) passing a set of function pointers to a registration function - supplied by the mid level. The mid level will then invoke these - functions at some point in the future. The LLD will supply - implementations of these functions. - c) direct access to instances of well known data structures maintained - by the mid level - -Those functions in group a) are listed in a section entitled "Mid level -supplied functions" below. - -Those functions in group b) are listed in a section entitled "Interface -functions" below. Their function pointers are placed in the members of -"struct scsi_host_template", an instance of which is passed to -scsi_host_alloc() ** . Those interface functions that the LLD does not -wish to supply should have NULL placed in the corresponding member of -struct scsi_host_template. Defining an instance of struct -scsi_host_template at file scope will cause NULL to be placed in function - pointer members not explicitly initialized. - -Those usages in group c) should be handled with care, especially in a -"hotplug" environment. LLDs should be aware of the lifetime of instances -that are shared with the mid level and other layers. - -All functions defined within an LLD and all data defined at file scope -should be static. For example the slave_alloc() function in an LLD -called "xxx" could be defined as -"static int xxx_slave_alloc(struct scsi_device * sdev) { /* code */ }" - -** the scsi_host_alloc() function is a replacement for the rather vaguely -named scsi_register() function in most situations. - - -Hotplug initialization model -============================ -In this model an LLD controls when SCSI hosts are introduced and removed -from the SCSI subsystem. Hosts can be introduced as early as driver -initialization and removed as late as driver shutdown. Typically a driver -will respond to a sysfs probe() callback that indicates an HBA has been -detected. After confirming that the new device is one that the LLD wants -to control, the LLD will initialize the HBA and then register a new host -with the SCSI mid level. - -During LLD initialization the driver should register itself with the -appropriate IO bus on which it expects to find HBA(s) (e.g. the PCI bus). -This can probably be done via sysfs. Any driver parameters (especially -those that are writable after the driver is loaded) could also be -registered with sysfs at this point. The SCSI mid level first becomes -aware of an LLD when that LLD registers its first HBA. - -At some later time, the LLD becomes aware of an HBA and what follows -is a typical sequence of calls between the LLD and the mid level. -This example shows the mid level scanning the newly introduced HBA for 3 -scsi devices of which only the first 2 respond: - - HBA PROBE: assume 2 SCSI devices found in scan -LLD mid level LLD -===-------------------=========--------------------===------ -scsi_host_alloc() --> -scsi_add_host() ----> -scsi_scan_host() -------+ - | - slave_alloc() - slave_configure() --> scsi_change_queue_depth() - | - slave_alloc() - slave_configure() - | - slave_alloc() *** - slave_destroy() *** ------------------------------------------------------------- - -If the LLD wants to adjust the default queue settings, it can invoke -scsi_change_queue_depth() in its slave_configure() routine. - -*** For scsi devices that the mid level tries to scan but do not - respond, a slave_alloc(), slave_destroy() pair is called. - -When an HBA is being removed it could be as part of an orderly shutdown -associated with the LLD module being unloaded (e.g. with the "rmmod" -command) or in response to a "hot unplug" indicated by sysfs()'s -remove() callback being invoked. In either case, the sequence is the -same: - - HBA REMOVE: assume 2 SCSI devices attached -LLD mid level LLD -===----------------------=========-----------------===------ -scsi_remove_host() ---------+ - | - slave_destroy() - slave_destroy() -scsi_host_put() ------------------------------------------------------------- - -It may be useful for a LLD to keep track of struct Scsi_Host instances -(a pointer is returned by scsi_host_alloc()). Such instances are "owned" -by the mid-level. struct Scsi_Host instances are freed from -scsi_host_put() when the reference count hits zero. - -Hot unplugging an HBA that controls a disk which is processing SCSI -commands on a mounted file system is an interesting situation. Reference -counting logic is being introduced into the mid level to cope with many -of the issues involved. See the section on reference counting below. - - -The hotplug concept may be extended to SCSI devices. Currently, when an -HBA is added, the scsi_scan_host() function causes a scan for SCSI devices -attached to the HBA's SCSI transport. On newer SCSI transports the HBA -may become aware of a new SCSI device _after_ the scan has completed. -An LLD can use this sequence to make the mid level aware of a SCSI device: - - SCSI DEVICE hotplug -LLD mid level LLD -===-------------------=========--------------------===------ -scsi_add_device() ------+ - | - slave_alloc() - slave_configure() [--> scsi_change_queue_depth()] ------------------------------------------------------------- - -In a similar fashion, an LLD may become aware that a SCSI device has been -removed (unplugged) or the connection to it has been interrupted. Some -existing SCSI transports (e.g. SPI) may not become aware that a SCSI -device has been removed until a subsequent SCSI command fails which will -probably cause that device to be set offline by the mid level. An LLD that -detects the removal of a SCSI device can instigate its removal from -upper layers with this sequence: - - SCSI DEVICE hot unplug -LLD mid level LLD -===----------------------=========-----------------===------ -scsi_remove_device() -------+ - | - slave_destroy() ------------------------------------------------------------- - -It may be useful for an LLD to keep track of struct scsi_device instances -(a pointer is passed as the parameter to slave_alloc() and -slave_configure() callbacks). Such instances are "owned" by the mid-level. -struct scsi_device instances are freed after slave_destroy(). - - -Reference Counting -================== -The Scsi_Host structure has had reference counting infrastructure added. -This effectively spreads the ownership of struct Scsi_Host instances -across the various SCSI layers which use them. Previously such instances -were exclusively owned by the mid level. LLDs would not usually need to -directly manipulate these reference counts but there may be some cases -where they do. - -There are 3 reference counting functions of interest associated with -struct Scsi_Host: - - scsi_host_alloc(): returns a pointer to new instance of struct - Scsi_Host which has its reference count ^^ set to 1 - - scsi_host_get(): adds 1 to the reference count of the given instance - - scsi_host_put(): decrements 1 from the reference count of the given - instance. If the reference count reaches 0 then the given instance - is freed - -The scsi_device structure has had reference counting infrastructure added. -This effectively spreads the ownership of struct scsi_device instances -across the various SCSI layers which use them. Previously such instances -were exclusively owned by the mid level. See the access functions declared -towards the end of include/scsi/scsi_device.h . If an LLD wants to keep -a copy of a pointer to a scsi_device instance it should use scsi_device_get() -to bump its reference count. When it is finished with the pointer it can -use scsi_device_put() to decrement its reference count (and potentially -delete it). - -^^ struct Scsi_Host actually has 2 reference counts which are manipulated -in parallel by these functions. - - -Conventions -=========== -First, Linus Torvalds's thoughts on C coding style can be found in the -Documentation/process/coding-style.rst file. - -Next, there is a movement to "outlaw" typedefs introducing synonyms for -struct tags. Both can be still found in the SCSI subsystem, but -the typedefs have been moved to a single file, scsi_typedefs.h to -make their future removal easier, for example: -"typedef struct scsi_cmnd Scsi_Cmnd;" - -Also, most C99 enhancements are encouraged to the extent they are supported -by the relevant gcc compilers. So C99 style structure and array -initializers are encouraged where appropriate. Don't go too far, -VLAs are not properly supported yet. An exception to this is the use of -"//" style comments; /*...*/ comments are still preferred in Linux. - -Well written, tested and documented code, need not be re-formatted to -comply with the above conventions. For example, the aic7xxx driver -comes to Linux from FreeBSD and Adaptec's own labs. No doubt FreeBSD -and Adaptec have their own coding conventions. - - -Mid level supplied functions -============================ -These functions are supplied by the SCSI mid level for use by LLDs. -The names (i.e. entry points) of these functions are exported -so an LLD that is a module can access them. The kernel will -arrange for the SCSI mid level to be loaded and initialized before any LLD -is initialized. The functions below are listed alphabetically and their -names all start with "scsi_". - -Summary: - scsi_add_device - creates new scsi device (lu) instance - scsi_add_host - perform sysfs registration and set up transport class - scsi_change_queue_depth - change the queue depth on a SCSI device - scsi_bios_ptable - return copy of block device's partition table - scsi_block_requests - prevent further commands being queued to given host - scsi_host_alloc - return a new scsi_host instance whose refcount==1 - scsi_host_get - increments Scsi_Host instance's refcount - scsi_host_put - decrements Scsi_Host instance's refcount (free if 0) - scsi_register - create and register a scsi host adapter instance. - scsi_remove_device - detach and remove a SCSI device - scsi_remove_host - detach and remove all SCSI devices owned by host - scsi_report_bus_reset - report scsi _bus_ reset observed - scsi_scan_host - scan SCSI bus - scsi_track_queue_full - track successive QUEUE_FULL events - scsi_unblock_requests - allow further commands to be queued to given host - scsi_unregister - [calls scsi_host_put()] - - -Details: - -/** - * scsi_add_device - creates new scsi device (lu) instance - * @shost: pointer to scsi host instance - * @channel: channel number (rarely other than 0) - * @id: target id number - * @lun: logical unit number - * - * Returns pointer to new struct scsi_device instance or - * ERR_PTR(-ENODEV) (or some other bent pointer) if something is - * wrong (e.g. no lu responds at given address) - * - * Might block: yes - * - * Notes: This call is usually performed internally during a scsi - * bus scan when an HBA is added (i.e. scsi_scan_host()). So it - * should only be called if the HBA becomes aware of a new scsi - * device (lu) after scsi_scan_host() has completed. If successful - * this call can lead to slave_alloc() and slave_configure() callbacks - * into the LLD. - * - * Defined in: drivers/scsi/scsi_scan.c - **/ -struct scsi_device * scsi_add_device(struct Scsi_Host *shost, - unsigned int channel, - unsigned int id, unsigned int lun) - - -/** - * scsi_add_host - perform sysfs registration and set up transport class - * @shost: pointer to scsi host instance - * @dev: pointer to struct device of type scsi class - * - * Returns 0 on success, negative errno of failure (e.g. -ENOMEM) - * - * Might block: no - * - * Notes: Only required in "hotplug initialization model" after a - * successful call to scsi_host_alloc(). This function does not - * scan the bus; this can be done by calling scsi_scan_host() or - * in some other transport-specific way. The LLD must set up - * the transport template before calling this function and may only - * access the transport class data after this function has been called. - * - * Defined in: drivers/scsi/hosts.c - **/ -int scsi_add_host(struct Scsi_Host *shost, struct device * dev) - - -/** - * scsi_change_queue_depth - allow LLD to change queue depth on a SCSI device - * @sdev: pointer to SCSI device to change queue depth on - * @tags Number of tags allowed if tagged queuing enabled, - * or number of commands the LLD can queue up - * in non-tagged mode (as per cmd_per_lun). - * - * Returns nothing - * - * Might block: no - * - * Notes: Can be invoked any time on a SCSI device controlled by this - * LLD. [Specifically during and after slave_configure() and prior to - * slave_destroy().] Can safely be invoked from interrupt code. - * - * Defined in: drivers/scsi/scsi.c [see source code for more notes] - * - **/ -int scsi_change_queue_depth(struct scsi_device *sdev, int tags) - - -/** - * scsi_bios_ptable - return copy of block device's partition table - * @dev: pointer to block device - * - * Returns pointer to partition table, or NULL for failure - * - * Might block: yes - * - * Notes: Caller owns memory returned (free with kfree() ) - * - * Defined in: drivers/scsi/scsicam.c - **/ -unsigned char *scsi_bios_ptable(struct block_device *dev) - - -/** - * scsi_block_requests - prevent further commands being queued to given host - * - * @shost: pointer to host to block commands on - * - * Returns nothing - * - * Might block: no - * - * Notes: There is no timer nor any other means by which the requests - * get unblocked other than the LLD calling scsi_unblock_requests(). - * - * Defined in: drivers/scsi/scsi_lib.c -**/ -void scsi_block_requests(struct Scsi_Host * shost) - - -/** - * scsi_host_alloc - create a scsi host adapter instance and perform basic - * initialization. - * @sht: pointer to scsi host template - * @privsize: extra bytes to allocate in hostdata array (which is the - * last member of the returned Scsi_Host instance) - * - * Returns pointer to new Scsi_Host instance or NULL on failure - * - * Might block: yes - * - * Notes: When this call returns to the LLD, the SCSI bus scan on - * this host has _not_ yet been done. - * The hostdata array (by default zero length) is a per host scratch - * area for the LLD's exclusive use. - * Both associated refcounting objects have their refcount set to 1. - * Full registration (in sysfs) and a bus scan are performed later when - * scsi_add_host() and scsi_scan_host() are called. - * - * Defined in: drivers/scsi/hosts.c . - **/ -struct Scsi_Host * scsi_host_alloc(struct scsi_host_template * sht, - int privsize) - - -/** - * scsi_host_get - increment Scsi_Host instance refcount - * @shost: pointer to struct Scsi_Host instance - * - * Returns nothing - * - * Might block: currently may block but may be changed to not block - * - * Notes: Actually increments the counts in two sub-objects - * - * Defined in: drivers/scsi/hosts.c - **/ -void scsi_host_get(struct Scsi_Host *shost) - - -/** - * scsi_host_put - decrement Scsi_Host instance refcount, free if 0 - * @shost: pointer to struct Scsi_Host instance - * - * Returns nothing - * - * Might block: currently may block but may be changed to not block - * - * Notes: Actually decrements the counts in two sub-objects. If the - * latter refcount reaches 0, the Scsi_Host instance is freed. - * The LLD need not worry exactly when the Scsi_Host instance is - * freed, it just shouldn't access the instance after it has balanced - * out its refcount usage. - * - * Defined in: drivers/scsi/hosts.c - **/ -void scsi_host_put(struct Scsi_Host *shost) - - -/** - * scsi_register - create and register a scsi host adapter instance. - * @sht: pointer to scsi host template - * @privsize: extra bytes to allocate in hostdata array (which is the - * last member of the returned Scsi_Host instance) - * - * Returns pointer to new Scsi_Host instance or NULL on failure - * - * Might block: yes - * - * Notes: When this call returns to the LLD, the SCSI bus scan on - * this host has _not_ yet been done. - * The hostdata array (by default zero length) is a per host scratch - * area for the LLD. - * - * Defined in: drivers/scsi/hosts.c . - **/ -struct Scsi_Host * scsi_register(struct scsi_host_template * sht, - int privsize) - - -/** - * scsi_remove_device - detach and remove a SCSI device - * @sdev: a pointer to a scsi device instance - * - * Returns value: 0 on success, -EINVAL if device not attached - * - * Might block: yes - * - * Notes: If an LLD becomes aware that a scsi device (lu) has - * been removed but its host is still present then it can request - * the removal of that scsi device. If successful this call will - * lead to the slave_destroy() callback being invoked. sdev is an - * invalid pointer after this call. - * - * Defined in: drivers/scsi/scsi_sysfs.c . - **/ -int scsi_remove_device(struct scsi_device *sdev) - - -/** - * scsi_remove_host - detach and remove all SCSI devices owned by host - * @shost: a pointer to a scsi host instance - * - * Returns value: 0 on success, 1 on failure (e.g. LLD busy ??) - * - * Might block: yes - * - * Notes: Should only be invoked if the "hotplug initialization - * model" is being used. It should be called _prior_ to - * scsi_unregister(). - * - * Defined in: drivers/scsi/hosts.c . - **/ -int scsi_remove_host(struct Scsi_Host *shost) - - -/** - * scsi_report_bus_reset - report scsi _bus_ reset observed - * @shost: a pointer to a scsi host involved - * @channel: channel (within) host on which scsi bus reset occurred - * - * Returns nothing - * - * Might block: no - * - * Notes: This only needs to be called if the reset is one which - * originates from an unknown location. Resets originated by the - * mid level itself don't need to call this, but there should be - * no harm. The main purpose of this is to make sure that a - * CHECK_CONDITION is properly treated. - * - * Defined in: drivers/scsi/scsi_error.c . - **/ -void scsi_report_bus_reset(struct Scsi_Host * shost, int channel) - - -/** - * scsi_scan_host - scan SCSI bus - * @shost: a pointer to a scsi host instance - * - * Might block: yes - * - * Notes: Should be called after scsi_add_host() - * - * Defined in: drivers/scsi/scsi_scan.c - **/ -void scsi_scan_host(struct Scsi_Host *shost) - - -/** - * scsi_track_queue_full - track successive QUEUE_FULL events on given - * device to determine if and when there is a need - * to adjust the queue depth on the device. - * @sdev: pointer to SCSI device instance - * @depth: Current number of outstanding SCSI commands on this device, - * not counting the one returned as QUEUE_FULL. - * - * Returns 0 - no change needed - * >0 - adjust queue depth to this new depth - * -1 - drop back to untagged operation using host->cmd_per_lun - * as the untagged command depth - * - * Might block: no - * - * Notes: LLDs may call this at any time and we will do "The Right - * Thing"; interrupt context safe. - * - * Defined in: drivers/scsi/scsi.c . - **/ -int scsi_track_queue_full(struct scsi_device *sdev, int depth) - - -/** - * scsi_unblock_requests - allow further commands to be queued to given host - * - * @shost: pointer to host to unblock commands on - * - * Returns nothing - * - * Might block: no - * - * Defined in: drivers/scsi/scsi_lib.c . -**/ -void scsi_unblock_requests(struct Scsi_Host * shost) - - -/** - * scsi_unregister - unregister and free memory used by host instance - * @shp: pointer to scsi host instance to unregister. - * - * Returns nothing - * - * Might block: no - * - * Notes: Should not be invoked if the "hotplug initialization - * model" is being used. Called internally by exit_this_scsi_driver() - * in the "passive initialization model". Hence a LLD has no need to - * call this function directly. - * - * Defined in: drivers/scsi/hosts.c . - **/ -void scsi_unregister(struct Scsi_Host * shp) - - - - -Interface Functions -=================== -Interface functions are supplied (defined) by LLDs and their function -pointers are placed in an instance of struct scsi_host_template which -is passed to scsi_host_alloc() [or scsi_register() / init_this_scsi_driver()]. -Some are mandatory. Interface functions should be declared static. The -accepted convention is that driver "xyz" will declare its slave_configure() -function as: - static int xyz_slave_configure(struct scsi_device * sdev); -and so forth for all interface functions listed below. - -A pointer to this function should be placed in the 'slave_configure' member -of a "struct scsi_host_template" instance. A pointer to such an instance -should be passed to the mid level's scsi_host_alloc() [or scsi_register() / -init_this_scsi_driver()]. - -The interface functions are also described in the include/scsi/scsi_host.h -file immediately above their definition point in "struct scsi_host_template". -In some cases more detail is given in scsi_host.h than below. - -The interface functions are listed below in alphabetical order. - -Summary: - bios_param - fetch head, sector, cylinder info for a disk - eh_timed_out - notify the host that a command timer expired - eh_abort_handler - abort given command - eh_bus_reset_handler - issue SCSI bus reset - eh_device_reset_handler - issue SCSI device reset - eh_host_reset_handler - reset host (host bus adapter) - info - supply information about given host - ioctl - driver can respond to ioctls - proc_info - supports /proc/scsi/{driver_name}/{host_no} - queuecommand - queue scsi command, invoke 'done' on completion - slave_alloc - prior to any commands being sent to a new device - slave_configure - driver fine tuning for given device after attach - slave_destroy - given device is about to be shut down - - -Details: - -/** - * bios_param - fetch head, sector, cylinder info for a disk - * @sdev: pointer to scsi device context (defined in - * include/scsi/scsi_device.h) - * @bdev: pointer to block device context (defined in fs.h) - * @capacity: device size (in 512 byte sectors) - * @params: three element array to place output: - * params[0] number of heads (max 255) - * params[1] number of sectors (max 63) - * params[2] number of cylinders - * - * Return value is ignored - * - * Locks: none - * - * Calling context: process (sd) - * - * Notes: an arbitrary geometry (based on READ CAPACITY) is used - * if this function is not provided. The params array is - * pre-initialized with made up values just in case this function - * doesn't output anything. - * - * Optionally defined in: LLD - **/ - int bios_param(struct scsi_device * sdev, struct block_device *bdev, - sector_t capacity, int params[3]) - - -/** - * eh_timed_out - The timer for the command has just fired - * @scp: identifies command timing out - * - * Returns: - * - * EH_HANDLED: I fixed the error, please complete the command - * EH_RESET_TIMER: I need more time, reset the timer and - * begin counting again - * EH_NOT_HANDLED Begin normal error recovery - * - * - * Locks: None held - * - * Calling context: interrupt - * - * Notes: This is to give the LLD an opportunity to do local recovery. - * This recovery is limited to determining if the outstanding command - * will ever complete. You may not abort and restart the command from - * this callback. - * - * Optionally defined in: LLD - **/ - int eh_timed_out(struct scsi_cmnd * scp) - - -/** - * eh_abort_handler - abort command associated with scp - * @scp: identifies command to be aborted - * - * Returns SUCCESS if command aborted else FAILED - * - * Locks: None held - * - * Calling context: kernel thread - * - * Notes: If 'no_async_abort' is defined this callback - * will be invoked from scsi_eh thread. No other commands - * will then be queued on current host during eh. - * Otherwise it will be called whenever scsi_times_out() - * is called due to a command timeout. - * - * Optionally defined in: LLD - **/ - int eh_abort_handler(struct scsi_cmnd * scp) - - -/** - * eh_bus_reset_handler - issue SCSI bus reset - * @scp: SCSI bus that contains this device should be reset - * - * Returns SUCCESS if command aborted else FAILED - * - * Locks: None held - * - * Calling context: kernel thread - * - * Notes: Invoked from scsi_eh thread. No other commands will be - * queued on current host during eh. - * - * Optionally defined in: LLD - **/ - int eh_bus_reset_handler(struct scsi_cmnd * scp) - - -/** - * eh_device_reset_handler - issue SCSI device reset - * @scp: identifies SCSI device to be reset - * - * Returns SUCCESS if command aborted else FAILED - * - * Locks: None held - * - * Calling context: kernel thread - * - * Notes: Invoked from scsi_eh thread. No other commands will be - * queued on current host during eh. - * - * Optionally defined in: LLD - **/ - int eh_device_reset_handler(struct scsi_cmnd * scp) - - -/** - * eh_host_reset_handler - reset host (host bus adapter) - * @scp: SCSI host that contains this device should be reset - * - * Returns SUCCESS if command aborted else FAILED - * - * Locks: None held - * - * Calling context: kernel thread - * - * Notes: Invoked from scsi_eh thread. No other commands will be - * queued on current host during eh. - * With the default eh_strategy in place, if none of the _abort_, - * _device_reset_, _bus_reset_ or this eh handler function are - * defined (or they all return FAILED) then the device in question - * will be set offline whenever eh is invoked. - * - * Optionally defined in: LLD - **/ - int eh_host_reset_handler(struct scsi_cmnd * scp) - - -/** - * info - supply information about given host: driver name plus data - * to distinguish given host - * @shp: host to supply information about - * - * Return ASCII null terminated string. [This driver is assumed to - * manage the memory pointed to and maintain it, typically for the - * lifetime of this host.] - * - * Locks: none - * - * Calling context: process - * - * Notes: Often supplies PCI or ISA information such as IO addresses - * and interrupt numbers. If not supplied struct Scsi_Host::name used - * instead. It is assumed the returned information fits on one line - * (i.e. does not included embedded newlines). - * The SCSI_IOCTL_PROBE_HOST ioctl yields the string returned by this - * function (or struct Scsi_Host::name if this function is not - * available). - * In a similar manner, init_this_scsi_driver() outputs to the console - * each host's "info" (or name) for the driver it is registering. - * Also if proc_info() is not supplied, the output of this function - * is used instead. - * - * Optionally defined in: LLD - **/ - const char * info(struct Scsi_Host * shp) - - -/** - * ioctl - driver can respond to ioctls - * @sdp: device that ioctl was issued for - * @cmd: ioctl number - * @arg: pointer to read or write data from. Since it points to - * user space, should use appropriate kernel functions - * (e.g. copy_from_user() ). In the Unix style this argument - * can also be viewed as an unsigned long. - * - * Returns negative "errno" value when there is a problem. 0 or a - * positive value indicates success and is returned to the user space. - * - * Locks: none - * - * Calling context: process - * - * Notes: The SCSI subsystem uses a "trickle down" ioctl model. - * The user issues an ioctl() against an upper level driver - * (e.g. /dev/sdc) and if the upper level driver doesn't recognize - * the 'cmd' then it is passed to the SCSI mid level. If the SCSI - * mid level does not recognize it, then the LLD that controls - * the device receives the ioctl. According to recent Unix standards - * unsupported ioctl() 'cmd' numbers should return -ENOTTY. - * - * Optionally defined in: LLD - **/ - int ioctl(struct scsi_device *sdp, int cmd, void *arg) - - -/** - * proc_info - supports /proc/scsi/{driver_name}/{host_no} - * @buffer: anchor point to output to (0==writeto1_read0) or fetch from - * (1==writeto1_read0). - * @start: where "interesting" data is written to. Ignored when - * 1==writeto1_read0. - * @offset: offset within buffer 0==writeto1_read0 is actually - * interested in. Ignored when 1==writeto1_read0 . - * @length: maximum (or actual) extent of buffer - * @host_no: host number of interest (struct Scsi_Host::host_no) - * @writeto1_read0: 1 -> data coming from user space towards driver - * (e.g. "echo some_string > /proc/scsi/xyz/2") - * 0 -> user what data from this driver - * (e.g. "cat /proc/scsi/xyz/2") - * - * Returns length when 1==writeto1_read0. Otherwise number of chars - * output to buffer past offset. - * - * Locks: none held - * - * Calling context: process - * - * Notes: Driven from scsi_proc.c which interfaces to proc_fs. proc_fs - * support can now be configured out of the scsi subsystem. - * - * Optionally defined in: LLD - **/ - int proc_info(char * buffer, char ** start, off_t offset, - int length, int host_no, int writeto1_read0) - - -/** - * queuecommand - queue scsi command, invoke scp->scsi_done on completion - * @shost: pointer to the scsi host object - * @scp: pointer to scsi command object - * - * Returns 0 on success. - * - * If there's a failure, return either: - * - * SCSI_MLQUEUE_DEVICE_BUSY if the device queue is full, or - * SCSI_MLQUEUE_HOST_BUSY if the entire host queue is full - * - * On both of these returns, the mid-layer will requeue the I/O - * - * - if the return is SCSI_MLQUEUE_DEVICE_BUSY, only that particular - * device will be paused, and it will be unpaused when a command to - * the device returns (or after a brief delay if there are no more - * outstanding commands to it). Commands to other devices continue - * to be processed normally. - * - * - if the return is SCSI_MLQUEUE_HOST_BUSY, all I/O to the host - * is paused and will be unpaused when any command returns from - * the host (or after a brief delay if there are no outstanding - * commands to the host). - * - * For compatibility with earlier versions of queuecommand, any - * other return value is treated the same as - * SCSI_MLQUEUE_HOST_BUSY. - * - * Other types of errors that are detected immediately may be - * flagged by setting scp->result to an appropriate value, - * invoking the scp->scsi_done callback, and then returning 0 - * from this function. If the command is not performed - * immediately (and the LLD is starting (or will start) the given - * command) then this function should place 0 in scp->result and - * return 0. - * - * Command ownership. If the driver returns zero, it owns the - * command and must take responsibility for ensuring the - * scp->scsi_done callback is executed. Note: the driver may - * call scp->scsi_done before returning zero, but after it has - * called scp->scsi_done, it may not return any value other than - * zero. If the driver makes a non-zero return, it must not - * execute the command's scsi_done callback at any time. - * - * Locks: up to and including 2.6.36, struct Scsi_Host::host_lock - * held on entry (with "irqsave") and is expected to be - * held on return. From 2.6.37 onwards, queuecommand is - * called without any locks held. - * - * Calling context: in interrupt (soft irq) or process context - * - * Notes: This function should be relatively fast. Normally it - * will not wait for IO to complete. Hence the scp->scsi_done - * callback is invoked (often directly from an interrupt service - * routine) some time after this function has returned. In some - * cases (e.g. pseudo adapter drivers that manufacture the - * response to a SCSI INQUIRY) the scp->scsi_done callback may be - * invoked before this function returns. If the scp->scsi_done - * callback is not invoked within a certain period the SCSI mid - * level will commence error processing. If a status of CHECK - * CONDITION is placed in "result" when the scp->scsi_done - * callback is invoked, then the LLD driver should perform - * autosense and fill in the struct scsi_cmnd::sense_buffer - * array. The scsi_cmnd::sense_buffer array is zeroed prior to - * the mid level queuing a command to an LLD. - * - * Defined in: LLD - **/ - int queuecommand(struct Scsi_Host *shost, struct scsi_cmnd * scp) - - -/** - * slave_alloc - prior to any commands being sent to a new device - * (i.e. just prior to scan) this call is made - * @sdp: pointer to new device (about to be scanned) - * - * Returns 0 if ok. Any other return is assumed to be an error and - * the device is ignored. - * - * Locks: none - * - * Calling context: process - * - * Notes: Allows the driver to allocate any resources for a device - * prior to its initial scan. The corresponding scsi device may not - * exist but the mid level is just about to scan for it (i.e. send - * and INQUIRY command plus ...). If a device is found then - * slave_configure() will be called while if a device is not found - * slave_destroy() is called. - * For more details see the include/scsi/scsi_host.h file. - * - * Optionally defined in: LLD - **/ - int slave_alloc(struct scsi_device *sdp) - - -/** - * slave_configure - driver fine tuning for given device just after it - * has been first scanned (i.e. it responded to an - * INQUIRY) - * @sdp: device that has just been attached - * - * Returns 0 if ok. Any other return is assumed to be an error and - * the device is taken offline. [offline devices will _not_ have - * slave_destroy() called on them so clean up resources.] - * - * Locks: none - * - * Calling context: process - * - * Notes: Allows the driver to inspect the response to the initial - * INQUIRY done by the scanning code and take appropriate action. - * For more details see the include/scsi/scsi_host.h file. - * - * Optionally defined in: LLD - **/ - int slave_configure(struct scsi_device *sdp) - - -/** - * slave_destroy - given device is about to be shut down. All - * activity has ceased on this device. - * @sdp: device that is about to be shut down - * - * Returns nothing - * - * Locks: none - * - * Calling context: process - * - * Notes: Mid level structures for given device are still in place - * but are about to be torn down. Any per device resources allocated - * by this driver for given device should be freed now. No further - * commands will be sent for this sdp instance. [However the device - * could be re-attached in the future in which case a new instance - * of struct scsi_device would be supplied by future slave_alloc() - * and slave_configure() calls.] - * - * Optionally defined in: LLD - **/ - void slave_destroy(struct scsi_device *sdp) - - - -Data Structures -=============== -struct scsi_host_template -------------------------- -There is one "struct scsi_host_template" instance per LLD ***. It is -typically initialized as a file scope static in a driver's header file. That -way members that are not explicitly initialized will be set to 0 or NULL. -Member of interest: - name - name of driver (may contain spaces, please limit to - less than 80 characters) - proc_name - name used in "/proc/scsi/<proc_name>/<host_no>" and - by sysfs in one of its "drivers" directories. Hence - "proc_name" should only contain characters acceptable - to a Unix file name. - (*queuecommand)() - primary callback that the mid level uses to inject - SCSI commands into an LLD. -The structure is defined and commented in include/scsi/scsi_host.h - -*** In extreme situations a single driver may have several instances - if it controls several different classes of hardware (e.g. an LLD - that handles both ISA and PCI cards and has a separate instance of - struct scsi_host_template for each class). - -struct Scsi_Host ----------------- -There is one struct Scsi_Host instance per host (HBA) that an LLD -controls. The struct Scsi_Host structure has many members in common -with "struct scsi_host_template". When a new struct Scsi_Host instance -is created (in scsi_host_alloc() in hosts.c) those common members are -initialized from the driver's struct scsi_host_template instance. Members -of interest: - host_no - system wide unique number that is used for identifying - this host. Issued in ascending order from 0. - can_queue - must be greater than 0; do not send more than can_queue - commands to the adapter. - this_id - scsi id of host (scsi initiator) or -1 if not known - sg_tablesize - maximum scatter gather elements allowed by host. - Set this to SG_ALL or less to avoid chained SG lists. - Must be at least 1. - max_sectors - maximum number of sectors (usually 512 bytes) allowed - in a single SCSI command. The default value of 0 leads - to a setting of SCSI_DEFAULT_MAX_SECTORS (defined in - scsi_host.h) which is currently set to 1024. So for a - disk the maximum transfer size is 512 KB when max_sectors - is not defined. Note that this size may not be sufficient - for disk firmware uploads. - cmd_per_lun - maximum number of commands that can be queued on devices - controlled by the host. Overridden by LLD calls to - scsi_change_queue_depth(). - unchecked_isa_dma - 1=>only use bottom 16 MB of ram (ISA DMA addressing - restriction), 0=>can use full 32 bit (or better) DMA - address space - no_async_abort - 1=>Asynchronous aborts are not supported - 0=>Timed-out commands will be aborted asynchronously - hostt - pointer to driver's struct scsi_host_template from which - this struct Scsi_Host instance was spawned - hostt->proc_name - name of LLD. This is the driver name that sysfs uses - transportt - pointer to driver's struct scsi_transport_template instance - (if any). FC and SPI transports currently supported. - sh_list - a double linked list of pointers to all struct Scsi_Host - instances (currently ordered by ascending host_no) - my_devices - a double linked list of pointers to struct scsi_device - instances that belong to this host. - hostdata[0] - area reserved for LLD at end of struct Scsi_Host. Size - is set by the second argument (named 'xtr_bytes') to - scsi_host_alloc() or scsi_register(). - vendor_id - a unique value that identifies the vendor supplying - the LLD for the Scsi_Host. Used most often in validating - vendor-specific message requests. Value consists of an - identifier type and a vendor-specific value. - See scsi_netlink.h for a description of valid formats. - -The scsi_host structure is defined in include/scsi/scsi_host.h - -struct scsi_device ------------------- -Generally, there is one instance of this structure for each SCSI logical unit -on a host. Scsi devices connected to a host are uniquely identified by a -channel number, target id and logical unit number (lun). -The structure is defined in include/scsi/scsi_device.h - -struct scsi_cmnd ----------------- -Instances of this structure convey SCSI commands to the LLD and responses -back to the mid level. The SCSI mid level will ensure that no more SCSI -commands become queued against the LLD than are indicated by -scsi_change_queue_depth() (or struct Scsi_Host::cmd_per_lun). There will -be at least one instance of struct scsi_cmnd available for each SCSI device. -Members of interest: - cmnd - array containing SCSI command - cmnd_len - length (in bytes) of SCSI command - sc_data_direction - direction of data transfer in data phase. See - "enum dma_data_direction" in include/linux/dma-mapping.h - request_bufflen - number of data bytes to transfer (0 if no data phase) - use_sg - ==0 -> no scatter gather list, hence transfer data - to/from request_buffer - - >0 -> scatter gather list (actually an array) in - request_buffer with use_sg elements - request_buffer - either contains data buffer or scatter gather list - depending on the setting of use_sg. Scatter gather - elements are defined by 'struct scatterlist' found - in include/linux/scatterlist.h . - done - function pointer that should be invoked by LLD when the - SCSI command is completed (successfully or otherwise). - Should only be called by an LLD if the LLD has accepted - the command (i.e. queuecommand() returned or will return - 0). The LLD may invoke 'done' prior to queuecommand() - finishing. - result - should be set by LLD prior to calling 'done'. A value - of 0 implies a successfully completed command (and all - data (if any) has been transferred to or from the SCSI - target device). 'result' is a 32 bit unsigned integer that - can be viewed as 4 related bytes. The SCSI status value is - in the LSB. See include/scsi/scsi.h status_byte(), - msg_byte(), host_byte() and driver_byte() macros and - related constants. - sense_buffer - an array (maximum size: SCSI_SENSE_BUFFERSIZE bytes) that - should be written when the SCSI status (LSB of 'result') - is set to CHECK_CONDITION (2). When CHECK_CONDITION is - set, if the top nibble of sense_buffer[0] has the value 7 - then the mid level will assume the sense_buffer array - contains a valid SCSI sense buffer; otherwise the mid - level will issue a REQUEST_SENSE SCSI command to - retrieve the sense buffer. The latter strategy is error - prone in the presence of command queuing so the LLD should - always "auto-sense". - device - pointer to scsi_device object that this command is - associated with. - resid - an LLD should set this signed integer to the requested - transfer length (i.e. 'request_bufflen') less the number - of bytes that are actually transferred. 'resid' is - preset to 0 so an LLD can ignore it if it cannot detect - underruns (overruns should be rare). If possible an LLD - should set 'resid' prior to invoking 'done'. The most - interesting case is data transfers from a SCSI target - device (e.g. READs) that underrun. - underflow - LLD should place (DID_ERROR << 16) in 'result' if - actual number of bytes transferred is less than this - figure. Not many LLDs implement this check and some that - do just output an error message to the log rather than - report a DID_ERROR. Better for an LLD to implement - 'resid'. - -It is recommended that a LLD set 'resid' on data transfers from a SCSI -target device (e.g. READs). It is especially important that 'resid' is set -when such data transfers have sense keys of MEDIUM ERROR and HARDWARE ERROR -(and possibly RECOVERED ERROR). In these cases if a LLD is in doubt how much -data has been received then the safest approach is to indicate no bytes have -been received. For example: to indicate that no valid data has been received -a LLD might use these helpers: - scsi_set_resid(SCpnt, scsi_bufflen(SCpnt)); -where 'SCpnt' is a pointer to a scsi_cmnd object. To indicate only three 512 -bytes blocks has been received 'resid' could be set like this: - scsi_set_resid(SCpnt, scsi_bufflen(SCpnt) - (3 * 512)); - -The scsi_cmnd structure is defined in include/scsi/scsi_cmnd.h - - -Locks -===== -Each struct Scsi_Host instance has a spin_lock called struct -Scsi_Host::default_lock which is initialized in scsi_host_alloc() [found in -hosts.c]. Within the same function the struct Scsi_Host::host_lock pointer -is initialized to point at default_lock. Thereafter lock and unlock -operations performed by the mid level use the struct Scsi_Host::host_lock -pointer. Previously drivers could override the host_lock pointer but -this is not allowed anymore. - - -Autosense -========= -Autosense (or auto-sense) is defined in the SAM-2 document as "the -automatic return of sense data to the application client coincident -with the completion of a SCSI command" when a status of CHECK CONDITION -occurs. LLDs should perform autosense. This should be done when the LLD -detects a CHECK CONDITION status by either: - a) instructing the SCSI protocol (e.g. SCSI Parallel Interface (SPI)) - to perform an extra data in phase on such responses - b) or, the LLD issuing a REQUEST SENSE command itself - -Either way, when a status of CHECK CONDITION is detected, the mid level -decides whether the LLD has performed autosense by checking struct -scsi_cmnd::sense_buffer[0] . If this byte has an upper nibble of 7 (or 0xf) -then autosense is assumed to have taken place. If it has another value (and -this byte is initialized to 0 before each command) then the mid level will -issue a REQUEST SENSE command. - -In the presence of queued commands the "nexus" that maintains sense -buffer data from the command that failed until a following REQUEST SENSE -may get out of synchronization. This is why it is best for the LLD -to perform autosense. - - -Changes since lk 2.4 series -=========================== -io_request_lock has been replaced by several finer grained locks. The lock -relevant to LLDs is struct Scsi_Host::host_lock and there is -one per SCSI host. - -The older error handling mechanism has been removed. This means the -LLD interface functions abort() and reset() have been removed. -The struct scsi_host_template::use_new_eh_code flag has been removed. - -In the 2.4 series the SCSI subsystem configuration descriptions were -aggregated with the configuration descriptions from all other Linux -subsystems in the Documentation/Configure.help file. In the 2.6 series, -the SCSI subsystem now has its own (much smaller) drivers/scsi/Kconfig -file that contains both configuration and help information. - -struct SHT has been renamed to struct scsi_host_template. - -Addition of the "hotplug initialization model" and many extra functions -to support it. - - -Credits -======= -The following people have contributed to this document: - Mike Anderson <andmike at us dot ibm dot com> - James Bottomley <James dot Bottomley at hansenpartnership dot com> - Patrick Mansfield <patmans at us dot ibm dot com> - Christoph Hellwig <hch at infradead dot org> - Doug Ledford <dledford at redhat dot com> - Andries Brouwer <Andries dot Brouwer at cwi dot nl> - Randy Dunlap <rdunlap at xenotime dot net> - Alan Stern <stern at rowland dot harvard dot edu> - - -Douglas Gilbert -dgilbert at interlog dot com -21st September 2004 diff --git a/Documentation/scsi/scsi_transport_srp/Makefile b/Documentation/scsi/scsi_transport_srp/Makefile deleted file mode 100644 index 5f6b567e955c..000000000000 --- a/Documentation/scsi/scsi_transport_srp/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -all: rport_state_diagram.svg rport_state_diagram.png - -rport_state_diagram.svg: rport_state_diagram.dot - dot -Tsvg -o $@ $< - -rport_state_diagram.png: rport_state_diagram.dot - dot -Tpng -o $@ $< diff --git a/Documentation/scsi/scsi_transport_srp/figures.rst b/Documentation/scsi/scsi_transport_srp/figures.rst new file mode 100644 index 000000000000..6c8f8dd6301b --- /dev/null +++ b/Documentation/scsi/scsi_transport_srp/figures.rst @@ -0,0 +1,6 @@ +.. SPDX-License-Identifier: GPL-2.0 + +SCSI RDMA (SRP) transport class diagram +======================================= + +.. kernel-figure:: rport_state_diagram.dot diff --git a/Documentation/scsi/sd-parameters.rst b/Documentation/scsi/sd-parameters.rst new file mode 100644 index 000000000000..87d554008bfb --- /dev/null +++ b/Documentation/scsi/sd-parameters.rst @@ -0,0 +1,27 @@ +.. SPDX-License-Identifier: GPL-2.0 + +====================================== +Linux SCSI Disk Driver (sd) Parameters +====================================== + +cache_type (RW) +--------------- +Enable/disable drive write & read cache. + +=========================== === === =========== ========== + cache_type string WCE RCD Write cache Read cache +=========================== === === =========== ========== + write through 0 0 off on + none 0 1 off off + write back 1 0 on on + write back, no read (daft) 1 1 on off +=========================== === === =========== ========== + +To set cache type to "write back" and save this setting to the drive:: + + # echo "write back" > cache_type + +To modify the caching mode without making the change persistent, prepend +"temporary " to the cache type string. E.g.:: + + # echo "temporary write back" > cache_type diff --git a/Documentation/scsi/sd-parameters.txt b/Documentation/scsi/sd-parameters.txt deleted file mode 100644 index 8e5af00d88e7..000000000000 --- a/Documentation/scsi/sd-parameters.txt +++ /dev/null @@ -1,22 +0,0 @@ -Linux SCSI Disk Driver (sd) Parameters -====================================== - -cache_type (RW) ---------------- -Enable/disable drive write & read cache. - - cache_type string | WCE RCD | Write cache | Read cache -----------------------------+---------+-------------+------------ - write through | 0 0 | off | on - none | 0 1 | off | off - write back | 1 0 | on | on - write back, no read (daft) | 1 1 | on | off - -To set cache type to "write back" and save this setting to the drive: - - # echo "write back" > cache_type - -To modify the caching mode without making the change persistent, prepend -"temporary " to the cache type string. E.g.: - - # echo "temporary write back" > cache_type diff --git a/Documentation/scsi/smartpqi.txt b/Documentation/scsi/smartpqi.rst index df129f55ace5..a7de27352c6f 100644 --- a/Documentation/scsi/smartpqi.txt +++ b/Documentation/scsi/smartpqi.rst @@ -1,6 +1,8 @@ +.. SPDX-License-Identifier: GPL-2.0 +===================================== SMARTPQI - Microsemi Smart PQI Driver ------------------------------------------ +===================================== This file describes the smartpqi SCSI driver for Microsemi (http://www.microsemi.com) PQI controllers. The smartpqi driver @@ -16,20 +18,21 @@ For Microsemi smartpqi controller support, enable the smartpqi driver when configuring the kernel. For more information on the PQI Queuing Interface, please see: -http://www.t10.org/drafts.htm -http://www.t10.org/members/w_pqi2.htm -Supported devices: ------------------- +- http://www.t10.org/drafts.htm +- http://www.t10.org/members/w_pqi2.htm + +Supported devices +================= <Controller names to be added as they become publicly available.> smartpqi specific entries in /sys ------------------------------ +================================= - smartpqi host attributes: - ------------------------- - /sys/class/scsi_host/host*/rescan - /sys/class/scsi_host/host*/driver_version +smartpqi host attributes +------------------------ + - /sys/class/scsi_host/host*/rescan + - /sys/class/scsi_host/host*/driver_version The host rescan attribute is a write only attribute. Writing to this attribute will trigger the driver to scan for new, changed, or removed @@ -37,12 +40,13 @@ smartpqi specific entries in /sys The version attribute is read-only and will return the driver version and the controller firmware version. - For example: + For example:: + driver: 0.9.13-370 firmware: 0.01-522 - smartpqi sas device attributes - ------------------------------ +smartpqi sas device attributes +------------------------------ HBA devices are added to the SAS transport layer. These attributes are automatically added by the SAS transport layer. @@ -50,31 +54,25 @@ smartpqi specific entries in /sys /sys/class/sas_device/end_device-X:X/enclosure_identifier /sys/class/sas_device/end_device-X:X/scsi_target_id -smartpqi specific ioctls: -------------------------- +smartpqi specific ioctls +======================== For compatibility with applications written for the cciss protocol. - CCISS_DEREGDISK - CCISS_REGNEWDISK - CCISS_REGNEWD - - The above three ioctls all do exactly the same thing, which is to cause the driver - to rescan for new devices. This does exactly the same thing as writing to the - smartpqi specific host "rescan" attribute. + CCISS_DEREGDISK, CCISS_REGNEWDISK, CCISS_REGNEWD + The above three ioctls all do exactly the same thing, which is to cause the driver + to rescan for new devices. This does exactly the same thing as writing to the + smartpqi specific host "rescan" attribute. CCISS_GETPCIINFO - Returns PCI domain, bus, device and function and "board ID" (PCI subsystem ID). CCISS_GETDRIVVER + Returns driver version in three bytes encoded as:: - Returns driver version in three bytes encoded as: - (DRIVER_MAJOR << 28) | (DRIVER_MINOR << 24) | (DRIVER_RELEASE << 16) | DRIVER_REVISION; + (DRIVER_MAJOR << 28) | (DRIVER_MINOR << 24) | (DRIVER_RELEASE << 16) | DRIVER_REVISION; CCISS_PASSTHRU - Allows "BMIC" and "CISS" commands to be passed through to the Smart Storage Array. These are used extensively by the SSA Array Configuration Utility, SNMP storage agents, etc. - diff --git a/Documentation/scsi/st.txt b/Documentation/scsi/st.rst index ec0acf6acccd..d3b28c28d74c 100644 --- a/Documentation/scsi/st.txt +++ b/Documentation/scsi/st.rst @@ -1,3 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0 + +==================== +The SCSI Tape Driver +==================== + This file contains brief information about the SCSI tape driver. The driver is currently maintained by Kai Mäkisara (email Kai.Makisara@kolumbus.fi) @@ -5,7 +11,8 @@ Kai.Makisara@kolumbus.fi) Last modified: Tue Feb 9 21:54:16 2016 by kai.makisara -BASICS +Basics +====== The driver is generic, i.e., it does not contain any code tailored to any specific tape drive. The tape parameters can be specified with @@ -110,15 +117,17 @@ tape in the drive (commands trying to write something return error if attempted). -MINOR NUMBERS +Minor Numbers +============= The tape driver currently supports up to 2^17 drives if 4 modes for each drive are used. -The minor numbers consist of the following bit fields: +The minor numbers consist of the following bit fields:: + + dev_upper non-rew mode dev-lower + 20 - 8 7 6 5 4 0 -dev_upper non-rew mode dev-lower - 20 - 8 7 6 5 4 0 The non-rewind bit is always bit 7 (the uppermost bit in the lowermost byte). The bits defining the mode are below the non-rewind bit. The remaining bits define the tape device number. This numbering is @@ -126,7 +135,8 @@ backward compatible with the numbering used when the minor number was only 8 bits wide. -SYSFS SUPPORT +Sysfs Support +============= The driver creates the directory /sys/class/scsi_tape and populates it with directories corresponding to the existing tape devices. There are autorewind @@ -148,10 +158,11 @@ bit definitions are the same as those used with MTSETDRVBUFFER in setting the options. A link named 'tape' is made from the SCSI device directory to the class -directory corresponding to the mode 0 auto-rewind device (e.g., st0). +directory corresponding to the mode 0 auto-rewind device (e.g., st0). -SYSFS AND STATISTICS FOR TAPE DEVICES +Sysfs and Statistics for Tape Devices +===================================== The st driver maintains statistics for tape drives inside the sysfs filesystem. The following method can be used to locate the statistics that are @@ -160,10 +171,10 @@ available (assuming that sysfs is mounted at /sys): 1. Use opendir(3) on the directory /sys/class/scsi_tape 2. Use readdir(3) to read the directory contents 3. Use regcomp(3)/regexec(3) to match directory entries to the extended - regular expression "^st[0-9]+$" + regular expression "^st[0-9]+$" 4. Access the statistics from the /sys/class/scsi_tape/<match>/stats - directory (where <match> is a directory entry from /sys/class/scsi_tape - that matched the extended regular expression) + directory (where <match> is a directory entry from /sys/class/scsi_tape + that matched the extended regular expression) The reason for using this approach is that all the character devices pointing to the same tape drive use the same statistics. That means @@ -171,29 +182,41 @@ that st0 would have the same statistics as nst0. The directory contains the following statistics files: -1. in_flight - The number of I/Os currently outstanding to this device. -2. io_ns - The amount of time spent waiting (in nanoseconds) for all I/O +1. in_flight + - The number of I/Os currently outstanding to this device. +2. io_ns + - The amount of time spent waiting (in nanoseconds) for all I/O to complete (including read and write). This includes tape movement commands such as seeking between file or set marks and implicit tape movement such as when rewind on close tape devices are used. -3. other_cnt - The number of I/Os issued to the tape drive other than read or +3. other_cnt + - The number of I/Os issued to the tape drive other than read or write commands. The time taken to complete these commands uses the following calculation io_ms-read_ms-write_ms. -4. read_byte_cnt - The number of bytes read from the tape drive. -5. read_cnt - The number of read requests issued to the tape drive. -6. read_ns - The amount of time (in nanoseconds) spent waiting for read +4. read_byte_cnt + - The number of bytes read from the tape drive. +5. read_cnt + - The number of read requests issued to the tape drive. +6. read_ns + - The amount of time (in nanoseconds) spent waiting for read requests to complete. -7. write_byte_cnt - The number of bytes written to the tape drive. -8. write_cnt - The number of write requests issued to the tape drive. -9. write_ns - The amount of time (in nanoseconds) spent waiting for write +7. write_byte_cnt + - The number of bytes written to the tape drive. +8. write_cnt + - The number of write requests issued to the tape drive. +9. write_ns + - The amount of time (in nanoseconds) spent waiting for write requests to complete. -10. resid_cnt - The number of times during a read or write we found +10. resid_cnt + - The number of times during a read or write we found the residual amount to be non-zero. This should mean that a program is issuing a read larger thean the block size on tape. For write not all data made it to tape. -Note: The in_flight value is incremented when an I/O starts the I/O -itself is not added to the statistics until it completes. +.. Note:: + + The in_flight value is incremented when an I/O starts the I/O + itself is not added to the statistics until it completes. The total of read_cnt, write_cnt, and other_cnt may not total to the same value as iodone_cnt at the device level. The tape statistics only count @@ -210,7 +233,8 @@ The value of in_flight is 0 when there are no I/Os outstanding that are issued by the st driver. Tape statistics do not take into account any I/O performed via the sg device. -BSD AND SYS V SEMANTICS +BSD and Sys V Semantics +======================= The user can choose between these two behaviours of the tape driver by defining the value of the symbol ST_SYSV. The semantics differ when a @@ -221,13 +245,15 @@ filemark unless the filemark has just been crossed. The default is BSD semantics. -BUFFERING +Buffering +========= The driver tries to do transfers directly to/from user space. If this is not possible, a driver buffer allocated at run-time is used. If direct i/o is not possible for the whole transfer, the driver buffer is used (i.e., bounce buffers for individual pages are not used). Direct i/o can be impossible because of several reasons, e.g.: + - one or more pages are at addresses not reachable by the HBA - the number of pages in the transfer exceeds the number of scatter/gather segments permitted by the HBA @@ -269,28 +295,30 @@ in the physical memory) are used if contiguous buffers can't be allocated. To support all SCSI adapters (including those not supporting scatter/gather), buffer allocation is using the following three kinds of chunks: + 1. The initial segment that is used for all SCSI adapters including -those not supporting scatter/gather. The size of this buffer will be -(PAGE_SIZE << ST_FIRST_ORDER) bytes if the system can give a chunk of -this size (and it is not larger than the buffer size specified by -ST_BUFFER_BLOCKS). If this size is not available, the driver halves -the size and tries again until the size of one page. The default -settings in st_options.h make the driver to try to allocate all of the -buffer as one chunk. + those not supporting scatter/gather. The size of this buffer will be + (PAGE_SIZE << ST_FIRST_ORDER) bytes if the system can give a chunk of + this size (and it is not larger than the buffer size specified by + ST_BUFFER_BLOCKS). If this size is not available, the driver halves + the size and tries again until the size of one page. The default + settings in st_options.h make the driver to try to allocate all of the + buffer as one chunk. 2. The scatter/gather segments to fill the specified buffer size are -allocated so that as many segments as possible are used but the number -of segments does not exceed ST_FIRST_SG. + allocated so that as many segments as possible are used but the number + of segments does not exceed ST_FIRST_SG. 3. The remaining segments between ST_MAX_SG (or the module parameter -max_sg_segs) and the number of segments used in phases 1 and 2 -are used to extend the buffer at run-time if this is necessary. The -number of scatter/gather segments allowed for the SCSI adapter is not -exceeded if it is smaller than the maximum number of scatter/gather -segments specified. If the maximum number allowed for the SCSI adapter -is smaller than the number of segments used in phases 1 and 2, -extending the buffer will always fail. + max_sg_segs) and the number of segments used in phases 1 and 2 + are used to extend the buffer at run-time if this is necessary. The + number of scatter/gather segments allowed for the SCSI adapter is not + exceeded if it is smaller than the maximum number of scatter/gather + segments specified. If the maximum number allowed for the SCSI adapter + is smaller than the number of segments used in phases 1 and 2, + extending the buffer will always fail. -EOM BEHAVIOUR WHEN WRITING +EOM Behaviour When Writing +========================== When the end of medium early warning is encountered, the current write is finished and the number of bytes is returned. The next write @@ -300,12 +328,13 @@ bytes is returned. After this, -1 and the number of bytes are alternately returned until the physical end of medium (or some other error) is encountered. - -MODULE PARAMETERS +Module Parameters +================= The buffer size, write threshold, and the maximum number of allocated buffers are configurable when the driver is loaded as a module. The keywords are: +========================== =========================================== buffer_kbs=xxx the buffer size for fixed block mode is set to xxx kilobytes write_threshold_kbs=xxx the write threshold in kilobytes set to xxx @@ -313,12 +342,14 @@ max_sg_segs=xxx the maximum number of scatter/gather segments try_direct_io=x try direct transfer between user buffer and tape drive if this is non-zero +========================== =========================================== Note that if the buffer size is changed but the write threshold is not set, the write threshold is set to the new buffer size - 2 kB. -BOOT TIME CONFIGURATION +Boot Time Configuration +======================= If the driver is compiled into the kernel, the same parameters can be also set using, e.g., the LILO command line. The preferred syntax is @@ -332,21 +363,23 @@ versions is supported. The same keywords can be used as when loading the driver as module. If several parameters are set, the keyword-value pairs are separated with a comma (no spaces allowed). A colon can be used instead of the equal mark. The definition is prepended by the -string st=. Here is an example: +string st=. Here is an example:: st=buffer_kbs:64,write_threshold_kbs:60 -The following syntax used by the old kernel versions is also supported: +The following syntax used by the old kernel versions is also supported:: st=aa[,bb[,dd]] -where - aa is the buffer size for fixed block mode in 1024 byte units - bb is the write threshold in 1024 byte units - dd is the maximum number of scatter/gather segments +where: + - aa is the buffer size for fixed block mode in 1024 byte units + - bb is the write threshold in 1024 byte units + - dd is the maximum number of scatter/gather segments -IOCTLS + +IOCTLs +====== The tape is positioned and the drive parameters are set with ioctls defined in mtio.h The tape control program 'mt' uses these ioctls. Try @@ -359,55 +392,80 @@ The supported ioctls are: The following use the structure mtop: -MTFSF Space forward over count filemarks. Tape positioned after filemark. -MTFSFM As above but tape positioned before filemark. -MTBSF Space backward over count filemarks. Tape positioned before +MTFSF + Space forward over count filemarks. Tape positioned after filemark. +MTFSFM + As above but tape positioned before filemark. +MTBSF + Space backward over count filemarks. Tape positioned before filemark. -MTBSFM As above but ape positioned after filemark. -MTFSR Space forward over count records. -MTBSR Space backward over count records. -MTFSS Space forward over count setmarks. -MTBSS Space backward over count setmarks. -MTWEOF Write count filemarks. -MTWEOFI Write count filemarks with immediate bit set (i.e., does not +MTBSFM + As above but ape positioned after filemark. +MTFSR + Space forward over count records. +MTBSR + Space backward over count records. +MTFSS + Space forward over count setmarks. +MTBSS + Space backward over count setmarks. +MTWEOF + Write count filemarks. +MTWEOFI + Write count filemarks with immediate bit set (i.e., does not wait until data is on tape) -MTWSM Write count setmarks. -MTREW Rewind tape. -MTOFFL Set device off line (often rewind plus eject). -MTNOP Do nothing except flush the buffers. -MTRETEN Re-tension tape. -MTEOM Space to end of recorded data. -MTERASE Erase tape. If the argument is zero, the short erase command +MTWSM + Write count setmarks. +MTREW + Rewind tape. +MTOFFL + Set device off line (often rewind plus eject). +MTNOP + Do nothing except flush the buffers. +MTRETEN + Re-tension tape. +MTEOM + Space to end of recorded data. +MTERASE + Erase tape. If the argument is zero, the short erase command is used. The long erase command is used with all other values of the argument. -MTSEEK Seek to tape block count. Uses Tandberg-compatible seek (QFA) +MTSEEK + Seek to tape block count. Uses Tandberg-compatible seek (QFA) for SCSI-1 drives and SCSI-2 seek for SCSI-2 drives. The file and block numbers in the status are not valid after a seek. -MTSETBLK Set the drive block size. Setting to zero sets the drive into +MTSETBLK + Set the drive block size. Setting to zero sets the drive into variable block mode (if applicable). -MTSETDENSITY Sets the drive density code to arg. See drive +MTSETDENSITY + Sets the drive density code to arg. See drive documentation for available codes. -MTLOCK and MTUNLOCK Explicitly lock/unlock the tape drive door. -MTLOAD and MTUNLOAD Explicitly load and unload the tape. If the +MTLOCK and MTUNLOCK + Explicitly lock/unlock the tape drive door. +MTLOAD and MTUNLOAD + Explicitly load and unload the tape. If the command argument x is between MT_ST_HPLOADER_OFFSET + 1 and MT_ST_HPLOADER_OFFSET + 6, the number x is used sent to the drive with the command and it selects the tape slot to use of HP C1553A changer. -MTCOMPRESSION Sets compressing or uncompressing drive mode using the +MTCOMPRESSION + Sets compressing or uncompressing drive mode using the SCSI mode page 15. Note that some drives other methods for control of compression. Some drives (like the Exabytes) use density codes for compression control. Some drives use another mode page but this page has not been implemented in the driver. Some drives without compression capability will accept any compression mode without error. -MTSETPART Moves the tape to the partition given by the argument at the +MTSETPART + Moves the tape to the partition given by the argument at the next tape operation. The block at which the tape is positioned is the block where the tape was previously positioned in the new active partition unless the next tape operation is MTSEEK. In this case the tape is moved directly to the block specified by MTSEEK. MTSETPART is inactive unless MT_ST_CAN_PARTITIONS set. -MTMKPART Formats the tape with one partition (argument zero) or two +MTMKPART + Formats the tape with one partition (argument zero) or two partitions (argument non-zero). If the argument is positive, it specifies the size of partition 1 in megabytes. For DDS drives and several early drives this is the physically first @@ -422,64 +480,81 @@ MTSETDRVBUFFER with mask MT_SET_OPTIONS, the low order bits are used as argument. This command is only allowed for the superuser (root). The subcommands are: - 0 + + * 0 The drive buffer option is set to the argument. Zero means no buffering. - MT_ST_BOOLEANS + * MT_ST_BOOLEANS Sets the buffering options. The bits are the new states (enabled/disabled) the following options (in the parenthesis is specified whether the option is global or can be specified differently for each mode): - MT_ST_BUFFER_WRITES write buffering (mode) - MT_ST_ASYNC_WRITES asynchronous writes (mode) - MT_ST_READ_AHEAD read ahead (mode) - MT_ST_TWO_FM writing of two filemarks (global) - MT_ST_FAST_EOM using the SCSI spacing to EOD (global) - MT_ST_AUTO_LOCK automatic locking of the drive door (global) - MT_ST_DEF_WRITES the defaults are meant only for writes (mode) - MT_ST_CAN_BSR backspacing over more than one records can + + MT_ST_BUFFER_WRITES + write buffering (mode) + MT_ST_ASYNC_WRITES + asynchronous writes (mode) + MT_ST_READ_AHEAD + read ahead (mode) + MT_ST_TWO_FM + writing of two filemarks (global) + MT_ST_FAST_EOM + using the SCSI spacing to EOD (global) + MT_ST_AUTO_LOCK + automatic locking of the drive door (global) + MT_ST_DEF_WRITES + the defaults are meant only for writes (mode) + MT_ST_CAN_BSR + backspacing over more than one records can be used for repositioning the tape (global) - MT_ST_NO_BLKLIMS the driver does not ask the block limits + MT_ST_NO_BLKLIMS + the driver does not ask the block limits from the drive (block size can be changed only to variable) (global) - MT_ST_CAN_PARTITIONS enables support for partitioned + MT_ST_CAN_PARTITIONS + enables support for partitioned tapes (global) - MT_ST_SCSI2LOGICAL the logical block number is used in + MT_ST_SCSI2LOGICAL + the logical block number is used in the MTSEEK and MTIOCPOS for SCSI-2 drives instead of the device dependent address. It is recommended to set this flag unless there are tapes using the device dependent (from the old times) (global) - MT_ST_SYSV sets the SYSV semantics (mode) - MT_ST_NOWAIT enables immediate mode (i.e., don't wait for + MT_ST_SYSV + sets the SYSV semantics (mode) + MT_ST_NOWAIT + enables immediate mode (i.e., don't wait for the command to finish) for some commands (e.g., rewind) - MT_ST_NOWAIT_EOF enables immediate filemark mode (i.e. when + MT_ST_NOWAIT_EOF + enables immediate filemark mode (i.e. when writing a filemark, don't wait for it to complete). Please see the BASICS note about MTWEOFI with respect to the possible dangers of writing immediate filemarks. - MT_ST_SILI enables setting the SILI bit in SCSI commands when + MT_ST_SILI + enables setting the SILI bit in SCSI commands when reading in variable block mode to enhance performance when reading blocks shorter than the byte count; set this only if you are sure that the drive supports SILI and the HBA correctly returns transfer residuals - MT_ST_DEBUGGING debugging (global; debugging must be + MT_ST_DEBUGGING + debugging (global; debugging must be compiled into the driver) - MT_ST_SETBOOLEANS - MT_ST_CLEARBOOLEANS + + * MT_ST_SETBOOLEANS, MT_ST_CLEARBOOLEANS Sets or clears the option bits. - MT_ST_WRITE_THRESHOLD + * MT_ST_WRITE_THRESHOLD Sets the write threshold for this device to kilobytes specified by the lowest bits. - MT_ST_DEF_BLKSIZE + * MT_ST_DEF_BLKSIZE Defines the default block size set automatically. Value 0xffffff means that the default is not used any more. - MT_ST_DEF_DENSITY - MT_ST_DEF_DRVBUFFER + * MT_ST_DEF_DENSITY, MT_ST_DEF_DRVBUFFER Used to set or clear the density (8 bits), and drive buffer state (3 bits). If the value is MT_ST_CLEAR_DEFAULT (0xfffff) the default will not be used any more. Otherwise the lowermost bits of the value contain the new value of the parameter. - MT_ST_DEF_COMPRESSION + * MT_ST_DEF_COMPRESSION The compression default will not be used if the value of the lowermost byte is 0xff. Otherwise the lowermost bit contains the new default. If the bits 8-15 are set to a @@ -487,17 +562,17 @@ MTSETDRVBUFFER used as the compression algorithm. The value MT_ST_CLEAR_DEFAULT can be used to clear the compression default. - MT_ST_SET_TIMEOUT + * MT_ST_SET_TIMEOUT Set the normal timeout in seconds for this device. The default is 900 seconds (15 minutes). The timeout should be long enough for the retries done by the device while reading/writing. - MT_ST_SET_LONG_TIMEOUT + * MT_ST_SET_LONG_TIMEOUT Set the long timeout that is used for operations that are known to take a long time. The default is 14000 seconds (3.9 hours). For erase this value is further multiplied by eight. - MT_ST_SET_CLN + * MT_ST_SET_CLN Set the cleaning request interpretation parameters using the lowest 24 bits of the argument. The driver can set the generic status bit GMT_CLN if a cleaning request bit pattern @@ -506,7 +581,7 @@ MTSETDRVBUFFER cleaning. The bits are device-dependent. The driver is given the number of the sense data byte (the lowest eight bits of the argument; must be >= 18 (values 1 - 17 - reserved) and <= the maximum requested sense data sixe), + reserved) and <= the maximum requested sense data sixe), a mask to select the relevant bits (the bits 9-16), and the bit pattern (bits 17-23). If the bit pattern is zero, one or more bits under the mask indicate cleaning request. If @@ -518,12 +593,16 @@ MTSETDRVBUFFER MT_ST_SET_CLN.) The following ioctl uses the structure mtpos: -MTIOCPOS Reads the current position from the drive. Uses + +MTIOCPOS + Reads the current position from the drive. Uses Tandberg-compatible QFA for SCSI-1 drives and the SCSI-2 command for the SCSI-2 drives. The following ioctl uses the structure mtget to return the status: -MTIOCGET Returns some status information. + +MTIOCGET + Returns some status information. The file number and block number within file are returned. The block is -1 when it can't be determined (e.g., after MTBSF). The drive type is either MTISSCSI1 or MTISSCSI2. @@ -537,7 +616,8 @@ MTIOCGET Returns some status information. end of recorded data or end of tape. GMT_EOT means end of tape. -MISCELLANEOUS COMPILE OPTIONS +Miscellaneous Compile Options +============================= The recovered write errors are considered fatal if ST_RECOVERED_WRITE_FATAL is defined. @@ -568,7 +648,8 @@ time or the MT_ST_CAN_BSR bit is set for the drive with an ioctl. user does not request data that far.) -DEBUGGING HINTS +Debugging Hints +=============== Debugging code is now compiled in by default but debugging is turned off with the kernel module parameter debug_flag defaulting to 0. Debugging diff --git a/Documentation/scsi/sym53c500_cs.txt b/Documentation/scsi/sym53c500_cs.rst index 75febcf9298c..55464861bbd5 100644 --- a/Documentation/scsi/sym53c500_cs.txt +++ b/Documentation/scsi/sym53c500_cs.rst @@ -1,3 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0 + +======================= +The sym53c500_cs Driver +======================= + The sym53c500_cs driver originated as an add-on to David Hinds' pcmcia-cs package, and was written by Tom Corner (tcorner@via.at). A rewrite was long overdue, and the current version addresses the following concerns: @@ -20,4 +26,4 @@ Through the years, there have been a number of downloads of the pcmcia-cs version of this driver, and I guess it worked for those users. It worked for Tom Corner, and it works for me. Your mileage will probably vary. ---Bob Tracy (rct@frus.com) +Bob Tracy (rct@frus.com) diff --git a/Documentation/scsi/sym53c8xx_2.txt b/Documentation/scsi/sym53c8xx_2.rst index d28186553fb0..8de44a7baa9b 100644 --- a/Documentation/scsi/sym53c8xx_2.txt +++ b/Documentation/scsi/sym53c8xx_2.rst @@ -1,99 +1,111 @@ +.. SPDX-License-Identifier: GPL-2.0 + +========================================= The Linux SYM-2 driver documentation file +========================================= Written by Gerard Roudier <groudier@free.fr> + 21 Rue Carnot + 95170 DEUIL LA BARRE - FRANCE Updated by Matthew Wilcox <matthew@wil.cx> 2004-10-09 -=============================================================================== - -1. Introduction -2. Supported chips and SCSI features -3. Advantages of this driver for newer chips. - 3.1 Optimized SCSI SCRIPTS - 3.2 New features appeared with the SYM53C896 -4. Memory mapped I/O versus normal I/O -5. Tagged command queueing -6. Parity checking -7. Profiling information -8. Control commands - 8.1 Set minimum synchronous period - 8.2 Set wide size - 8.3 Set maximum number of concurrent tagged commands - 8.4 Set debug mode - 8.5 Set flag (no_disc) - 8.6 Set verbose level - 8.7 Reset all logical units of a target - 8.8 Abort all tasks of all logical units of a target -9. Configuration parameters -10. Boot setup commands - 10.1 Syntax - 10.2 Available arguments - 10.2.1 Default number of tagged commands - 10.2.2 Burst max - 10.2.3 LED support - 10.2.4 Differential mode - 10.2.5 IRQ mode - 10.2.6 Check SCSI BUS - 10.2.7 Suggest a default SCSI id for hosts - 10.2.8 Verbosity level - 10.2.9 Debug mode - 10.2.10 Settle delay - 10.2.11 Serial NVRAM - 10.2.12 Exclude a host from being attached - 10.3 Converting from old options - 10.4 SCSI BUS checking boot option -11. SCSI problem troubleshooting - 15.1 Problem tracking - 15.2 Understanding hardware error reports -12. Serial NVRAM support (by Richard Waltham) - 17.1 Features - 17.2 Symbios NVRAM layout - 17.3 Tekram NVRAM layout - -=============================================================================== + +.. Contents + + 1. Introduction + 2. Supported chips and SCSI features + 3. Advantages of this driver for newer chips. + 3.1 Optimized SCSI SCRIPTS + 3.2 New features appeared with the SYM53C896 + 4. Memory mapped I/O versus normal I/O + 5. Tagged command queueing + 6. Parity checking + 7. Profiling information + 8. Control commands + 8.1 Set minimum synchronous period + 8.2 Set wide size + 8.3 Set maximum number of concurrent tagged commands + 8.4 Set debug mode + 8.5 Set flag (no_disc) + 8.6 Set verbose level + 8.7 Reset all logical units of a target + 8.8 Abort all tasks of all logical units of a target + 9. Configuration parameters + 10. Boot setup commands + 10.1 Syntax + 10.2 Available arguments + 10.2.1 Default number of tagged commands + 10.2.2 Burst max + 10.2.3 LED support + 10.2.4 Differential mode + 10.2.5 IRQ mode + 10.2.6 Check SCSI BUS + 10.2.7 Suggest a default SCSI id for hosts + 10.2.8 Verbosity level + 10.2.9 Debug mode + 10.2.10 Settle delay + 10.2.11 Serial NVRAM + 10.2.12 Exclude a host from being attached + 10.3 Converting from old options + 10.4 SCSI BUS checking boot option + 11. SCSI problem troubleshooting + 15.1 Problem tracking + 15.2 Understanding hardware error reports + 12. Serial NVRAM support (by Richard Waltham) + 17.1 Features + 17.2 Symbios NVRAM layout + 17.3 Tekram NVRAM layout + 1. Introduction +=============== This driver supports the whole SYM53C8XX family of PCI-SCSI controllers. -It also support the subset of LSI53C10XX PCI-SCSI controllers that are based +It also support the subset of LSI53C10XX PCI-SCSI controllers that are based on the SYM53C8XX SCRIPTS language. -It replaces the sym53c8xx+ncr53c8xx driver bundle and shares its core code -with the FreeBSD SYM-2 driver. The `glue' that allows this driver to work +It replaces the sym53c8xx+ncr53c8xx driver bundle and shares its core code +with the FreeBSD SYM-2 driver. The 'glue' that allows this driver to work under Linux is contained in 2 files named sym_glue.h and sym_glue.c. -Other drivers files are intended not to depend on the Operating System +Other drivers files are intended not to depend on the Operating System on which the driver is used. The history of this driver can be summarized as follows: 1993: ncr driver written for 386bsd and FreeBSD by: - Wolfgang Stanglmeier <wolf@cologne.de> - Stefan Esser <se@mi.Uni-Koeln.de> + + - Wolfgang Stanglmeier <wolf@cologne.de> + - Stefan Esser <se@mi.Uni-Koeln.de> 1996: port of the ncr driver to Linux-1.2.13 and rename it ncr53c8xx. - Gerard Roudier -1998: new sym53c8xx driver for Linux based on LOAD/STORE instruction and that + - Gerard Roudier + +1998: new sym53c8xx driver for Linux based on LOAD/STORE instruction and that adds full support for the 896 but drops support for early NCR devices. - Gerard Roudier -1999: port of the sym53c8xx driver to FreeBSD and support for the LSI53C1010 - 33 MHz and 66MHz Ultra-3 controllers. The new driver is named `sym'. - Gerard Roudier + - Gerard Roudier -2000: Add support for early NCR devices to FreeBSD `sym' driver. - Break the driver into several sources and separate the OS glue +1999: port of the sym53c8xx driver to FreeBSD and support for the LSI53C1010 + 33 MHz and 66MHz Ultra-3 controllers. The new driver is named 'sym'. + + - Gerard Roudier + +2000: Add support for early NCR devices to FreeBSD 'sym' driver. + Break the driver into several sources and separate the OS glue code from the core code that can be shared among different O/Ses. Write a glue code for Linux. - Gerard Roudier + + - Gerard Roudier 2004: Remove FreeBSD compatibility code. Remove support for versions of Linux before 2.6. Start using Linux facilities. -This README file addresses the Linux version of the driver. Under FreeBSD, +This README file addresses the Linux version of the driver. Under FreeBSD, the driver documentation is the sym.8 man page. Information about new chips is available at LSILOGIC web server: @@ -104,113 +116,145 @@ SCSI standard documentations are available at T10 site: http://www.t10.org/ -Useful SCSI tools written by Eric Youngdale are part of most Linux +Useful SCSI tools written by Eric Youngdale are part of most Linux distributions: - scsiinfo: command line tool - scsi-config: TCL/Tk tool using scsiinfo + + ============ ========================== + scsiinfo command line tool + scsi-config TCL/Tk tool using scsiinfo + ============ ========================== 2. Supported chips and SCSI features +==================================== The following features are supported for all chips: - Synchronous negotiation - Disconnection - Tagged command queuing - SCSI parity checking - PCI Master parity checking + - Synchronous negotiation + - Disconnection + - Tagged command queuing + - SCSI parity checking + - PCI Master parity checking Other features depends on chip capabilities. -The driver notably uses optimized SCRIPTS for devices that support -LOAD/STORE and handles PHASE MISMATCH from SCRIPTS for devices that + +The driver notably uses optimized SCRIPTS for devices that support +LOAD/STORE and handles PHASE MISMATCH from SCRIPTS for devices that support the corresponding feature. The following table shows some characteristics of the chip family. - On board LOAD/STORE HARDWARE -Chip SDMS BIOS Wide SCSI std. Max. sync SCRIPTS PHASE MISMATCH ----- --------- ---- --------- ---------- ---------- -------------- -810 N N FAST10 10 MB/s N N -810A N N FAST10 10 MB/s Y N -815 Y N FAST10 10 MB/s N N -825 Y Y FAST10 20 MB/s N N -825A Y Y FAST10 20 MB/s Y N -860 N N FAST20 20 MB/s Y N -875 Y Y FAST20 40 MB/s Y N -875A Y Y FAST20 40 MB/s Y Y -876 Y Y FAST20 40 MB/s Y N -895 Y Y FAST40 80 MB/s Y N -895A Y Y FAST40 80 MB/s Y Y -896 Y Y FAST40 80 MB/s Y Y -897 Y Y FAST40 80 MB/s Y Y -1510D Y Y FAST40 80 MB/s Y Y -1010 Y Y FAST80 160 MB/s Y Y -1010_66* Y Y FAST80 160 MB/s Y Y - -* Chip supports 33MHz and 66MHz PCI bus clock. ++--------+-----------+-----+-----------+------------+------------+---------+ +| | | | | |Load/store |Hardware | +| |On board | | | |scripts |phase | +|Chip |SDMS BIOS |Wide |SCSI std. | Max. sync | |mismatch | ++--------+-----------+-----+-----------+------------+------------+---------+ +|810 | N | N | FAST10 | 10 MB/s | N | N | ++--------+-----------+-----+-----------+------------+------------+---------+ +|810A | N | N | FAST10 | 10 MB/s | Y | N | ++--------+-----------+-----+-----------+------------+------------+---------+ +|815 | Y | N | FAST10 | 10 MB/s | N | N | ++--------+-----------+-----+-----------+------------+------------+---------+ +|825 | Y | Y | FAST10 | 20 MB/s | N | N | ++--------+-----------+-----+-----------+------------+------------+---------+ +|825A | Y | Y | FAST10 | 20 MB/s | Y | N | ++--------+-----------+-----+-----------+------------+------------+---------+ +|860 | N | N | FAST20 | 20 MB/s | Y | N | ++--------+-----------+-----+-----------+------------+------------+---------+ +|875 | Y | Y | FAST20 | 40 MB/s | Y | N | ++--------+-----------+-----+-----------+------------+------------+---------+ +|875A | Y | Y | FAST20 | 40 MB/s | Y | Y | ++--------+-----------+-----+-----------+------------+------------+---------+ +|876 | Y | Y | FAST20 | 40 MB/s | Y | N | ++--------+-----------+-----+-----------+------------+------------+---------+ +|895 | Y | Y | FAST40 | 80 MB/s | Y | N | ++--------+-----------+-----+-----------+------------+------------+---------+ +|895A | Y | Y | FAST40 | 80 MB/s | Y | Y | ++--------+-----------+-----+-----------+------------+------------+---------+ +|896 | Y | Y | FAST40 | 80 MB/s | Y | Y | ++--------+-----------+-----+-----------+------------+------------+---------+ +|897 | Y | Y | FAST40 | 80 MB/s | Y | Y | ++--------+-----------+-----+-----------+------------+------------+---------+ +|1510D | Y | Y | FAST40 | 80 MB/s | Y | Y | ++--------+-----------+-----+-----------+------------+------------+---------+ +|1010 | Y | Y | FAST80 |160 MB/s | Y | Y | ++--------+-----------+-----+-----------+------------+------------+---------+ +|1010_66 | Y | Y | FAST80 |160 MB/s | Y | Y | +|[1]_ | | | | | | | ++--------+-----------+-----+-----------+------------+------------+---------+ + +.. [1] Chip supports 33MHz and 66MHz PCI bus clock. Summary of other supported features: -Module: allow to load the driver -Memory mapped I/O: increases performance -Control commands: write operations to the proc SCSI file system -Debugging information: written to syslog (expert only) -Scatter / gather -Shared interrupt -Boot setup commands -Serial NVRAM: Symbios and Tekram formats +:Module: allow to load the driver +:Memory mapped I/O: increases performance +:Control commands: write operations to the proc SCSI file system +:Debugging information: written to syslog (expert only) +:Serial NVRAM: Symbios and Tekram formats + +- Scatter / gather +- Shared interrupt +- Boot setup commands 3. Advantages of this driver for newer chips. +============================================= -3.1 Optimized SCSI SCRIPTS. +3.1 Optimized SCSI SCRIPTS +-------------------------- -All chips except the 810, 815 and 825, support new SCSI SCRIPTS instructions -named LOAD and STORE that allow to move up to 1 DWORD from/to an IO register -to/from memory much faster that the MOVE MEMORY instruction that is supported +All chips except the 810, 815 and 825, support new SCSI SCRIPTS instructions +named LOAD and STORE that allow to move up to 1 DWORD from/to an IO register +to/from memory much faster that the MOVE MEMORY instruction that is supported by the 53c7xx and 53c8xx family. -The LOAD/STORE instructions support absolute and DSA relative addressing -modes. The SCSI SCRIPTS had been entirely rewritten using LOAD/STORE instead +The LOAD/STORE instructions support absolute and DSA relative addressing +modes. The SCSI SCRIPTS had been entirely rewritten using LOAD/STORE instead of MOVE MEMORY instructions. -Due to the lack of LOAD/STORE SCRIPTS instructions by earlier chips, this -driver also incorporates a different SCRIPTS set based on MEMORY MOVE, in +Due to the lack of LOAD/STORE SCRIPTS instructions by earlier chips, this +driver also incorporates a different SCRIPTS set based on MEMORY MOVE, in order to provide support for the entire SYM53C8XX chips family. 3.2 New features appeared with the SYM53C896 +-------------------------------------------- -Newer chips (see above) allows handling of the phase mismatch context from -SCRIPTS (avoids the phase mismatch interrupt that stops the SCSI processor +Newer chips (see above) allows handling of the phase mismatch context from +SCRIPTS (avoids the phase mismatch interrupt that stops the SCSI processor until the C code has saved the context of the transfer). -The 896 and 1010 chips support 64 bit PCI transactions and addressing, +The 896 and 1010 chips support 64 bit PCI transactions and addressing, while the 895A supports 32 bit PCI transactions and 64 bit addressing. -The SCRIPTS processor of these chips is not true 64 bit, but uses segment -registers for bit 32-63. Another interesting feature is that LOAD/STORE +The SCRIPTS processor of these chips is not true 64 bit, but uses segment +registers for bit 32-63. Another interesting feature is that LOAD/STORE instructions that address the on-chip RAM (8k) remain internal to the chip. 4. Memory mapped I/O versus normal I/O +====================================== -Memory mapped I/O has less latency than normal I/O and is the recommended -way for doing IO with PCI devices. Memory mapped I/O seems to work fine on -most hardware configurations, but some poorly designed chipsets may break -this feature. A configuration option is provided for normal I/O to be +Memory mapped I/O has less latency than normal I/O and is the recommended +way for doing IO with PCI devices. Memory mapped I/O seems to work fine on +most hardware configurations, but some poorly designed chipsets may break +this feature. A configuration option is provided for normal I/O to be used but the driver defaults to MMIO. 5. Tagged command queueing +========================== -Queuing more than 1 command at a time to a device allows it to perform -optimizations based on actual head positions and its mechanical +Queuing more than 1 command at a time to a device allows it to perform +optimizations based on actual head positions and its mechanical characteristics. This feature may also reduce average command latency. -In order to really gain advantage of this feature, devices must have -a reasonable cache size (No miracle is to be expected for a low-end +In order to really gain advantage of this feature, devices must have +a reasonable cache size (No miracle is to be expected for a low-end hard disk with 128 KB or less). + Some known old SCSI devices do not properly support tagged command queuing. -Generally, firmware revisions that fix this kind of problems are available +Generally, firmware revisions that fix this kind of problems are available at respective vendor web/ftp sites. -All I can say is that I never have had problem with tagged queuing using -this driver and its predecessors. Hard disks that behaved correctly for + +All I can say is that I never have had problem with tagged queuing using +this driver and its predecessors. Hard disks that behaved correctly for me using tagged commands are the following: - IBM S12 0662 @@ -223,9 +267,9 @@ me using tagged commands are the following: - Quantum Atlas IV - Seagate Cheetah II -If your controller has NVRAM, you can configure this feature per target -from the user setup tool. The Tekram Setup program allows to tune the -maximum number of queued commands up to 32. The Symbios Setup only allows +If your controller has NVRAM, you can configure this feature per target +from the user setup tool. The Tekram Setup program allows to tune the +maximum number of queued commands up to 32. The Symbios Setup only allows to enable or disable this feature. The maximum number of simultaneous tagged commands queued to a device @@ -233,15 +277,15 @@ is currently set to 16 by default. This value is suitable for most SCSI disks. With large SCSI disks (>= 2GB, cache >= 512KB, average seek time <= 10 ms), using a larger value may give better performances. -This driver supports up to 255 commands per device, and but using more than -64 is generally not worth-while, unless you are using a very large disk or -disk arrays. It is noticeable that most of recent hard disks seem not to -accept more than 64 simultaneous commands. So, using more than 64 queued +This driver supports up to 255 commands per device, and but using more than +64 is generally not worth-while, unless you are using a very large disk or +disk arrays. It is noticeable that most of recent hard disks seem not to +accept more than 64 simultaneous commands. So, using more than 64 queued commands is probably just resource wasting. -If your controller does not have NVRAM or if it is managed by the SDMS -BIOS/SETUP, you can configure tagged queueing feature and device queue -depths from the boot command-line. For example: +If your controller does not have NVRAM or if it is managed by the SDMS +BIOS/SETUP, you can configure tagged queueing feature and device queue +depths from the boot command-line. For example:: sym53c8xx=tags:4/t2t3q15-t4q7/t1u0q32 @@ -257,25 +301,28 @@ In some special conditions, some SCSI disk firmwares may return a QUEUE FULL status for a SCSI command. This behaviour is managed by the driver using the following heuristic: -- Each time a QUEUE FULL status is returned, tagged queue depth is reduced - to the actual number of disconnected commands. +- Each time a QUEUE FULL status is returned, tagged queue depth is reduced + to the actual number of disconnected commands. - Every 200 successfully completed SCSI commands, if allowed by the current limit, the maximum number of queueable commands is incremented. -Since QUEUE FULL status reception and handling is resource wasting, the -driver notifies by default this problem to user by indicating the actual -number of commands used and their status, as well as its decision on the +Since QUEUE FULL status reception and handling is resource wasting, the +driver notifies by default this problem to user by indicating the actual +number of commands used and their status, as well as its decision on the device queue depth change. -The heuristic used by the driver in handling QUEUE FULL ensures that the -impact on performances is not too bad. You can get rid of the messages by +The heuristic used by the driver in handling QUEUE FULL ensures that the +impact on performances is not too bad. You can get rid of the messages by setting verbose level to zero, as follow: -1st method: boot your system using 'sym53c8xx=verb:0' option. -2nd method: apply "setverbose 0" control command to the proc fs entry +1st method: + boot your system using 'sym53c8xx=verb:0' option. +2nd method: + apply "setverbose 0" control command to the proc fs entry corresponding to your controller after boot-up. 6. Parity checking +================== The driver supports SCSI parity checking and PCI bus master parity checking. These features must be enabled in order to ensure safe @@ -284,17 +331,19 @@ with parity. The options to defeat parity checking have been removed from the driver. 7. Profiling information +======================== This driver does not provide profiling information as did its predecessors. -This feature was not this useful and added complexity to the code. -As the driver code got more complex, I have decided to remove everything +This feature was not this useful and added complexity to the code. +As the driver code got more complex, I have decided to remove everything that didn't seem actually useful. 8. Control commands +=================== Control commands can be sent to the driver with write operations to the proc SCSI file system. The generic command syntax is the -following: +following:: echo "<verb> <parameters>" >/proc/scsi/sym53c8xx/0 (assumes controller number is 0) @@ -305,97 +354,112 @@ apply to all targets of the SCSI chain (except the controller). Available commands: 8.1 Set minimum synchronous period factor +----------------------------------------- setsync <target> <period factor> - target: target number - period: minimum synchronous period. + :target: target number + :period: minimum synchronous period. Maximum speed = 1000/(4*period factor) except for special cases below. Specify a period of 0, to force asynchronous transfer mode. - 9 means 12.5 nano-seconds synchronous period - 10 means 25 nano-seconds synchronous period - 11 means 30 nano-seconds synchronous period - 12 means 50 nano-seconds synchronous period + - 9 means 12.5 nano-seconds synchronous period + - 10 means 25 nano-seconds synchronous period + - 11 means 30 nano-seconds synchronous period + - 12 means 50 nano-seconds synchronous period 8.2 Set wide size +----------------- setwide <target> <size> - target: target number - size: 0=8 bits, 1=16bits + :target: target number + :size: 0=8 bits, 1=16bits 8.3 Set maximum number of concurrent tagged commands - +---------------------------------------------------- + settags <target> <tags> - target: target number - tags: number of concurrent tagged commands + :target: target number + :tags: number of concurrent tagged commands must not be greater than configured (default: 16) 8.4 Set debug mode +------------------ setdebug <list of debug flags> Available debug flags: - alloc: print info about memory allocations (ccb, lcb) - queue: print info about insertions into the command start queue - result: print sense data on CHECK CONDITION status - scatter: print info about the scatter process - scripts: print info about the script binding process - tiny: print minimal debugging information - timing: print timing information of the NCR chip - nego: print information about SCSI negotiations - phase: print information on script interruptions + + ======== ======================================================== + alloc print info about memory allocations (ccb, lcb) + queue print info about insertions into the command start queue + result print sense data on CHECK CONDITION status + scatter print info about the scatter process + scripts print info about the script binding process + tiny print minimal debugging information + timing print timing information of the NCR chip + nego print information about SCSI negotiations + phase print information on script interruptions + ======== ======================================================== Use "setdebug" with no argument to reset debug flags. 8.5 Set flag (no_disc) - +---------------------- + setflag <target> <flag> - target: target number + :target: target number For the moment, only one flag is available: no_disc: not allow target to disconnect. Do not specify any flag in order to reset the flag. For example: - - setflag 4 + + setflag 4 will reset no_disc flag for target 4, so will allow it disconnections. - - setflag all + setflag all will allow disconnection for all devices on the SCSI bus. 8.6 Set verbose level +--------------------- setverbose #level - The driver default verbose level is 1. This command allows to change + The driver default verbose level is 1. This command allows to change th driver verbose level after boot-up. 8.7 Reset all logical units of a target +--------------------------------------- resetdev <target> - target: target number + :target: target number + The driver will try to send a BUS DEVICE RESET message to the target. 8.8 Abort all tasks of all logical units of a target +---------------------------------------------------- cleardev <target> - target: target number - The driver will try to send a ABORT message to all the logical units + :target: target number + + The driver will try to send a ABORT message to all the logical units of the target. 9. Configuration parameters +=========================== -Under kernel configuration tools (make menuconfig, for example), it is +Under kernel configuration tools (make menuconfig, for example), it is possible to change some default driver configuration parameters. If the firmware of all your devices is perfect enough, all the features supported by the driver can be enabled at start-up. However, @@ -414,166 +478,238 @@ Default tagged command queue depth (default answer: 16) This parameter can be specified from the boot command line. Maximum number of queued commands (default answer: 32) - This option allows you to specify the maximum number of tagged commands + This option allows you to specify the maximum number of tagged commands that can be queued to a device. The maximum supported value is 255. Synchronous transfers frequency (default answer: 80) - This option allows you to specify the frequency in MHz the driver + This option allows you to specify the frequency in MHz the driver will use at boot time for synchronous data transfer negotiations. 0 means "asynchronous data transfers". 10. Boot setup commands +======================= 10.1 Syntax +----------- Setup commands can be passed to the driver either at boot time or as parameters to modprobe, as described in Documentation/admin-guide/kernel-parameters.rst -Example of boot setup command under lilo prompt: +Example of boot setup command under lilo prompt:: -lilo: linux root=/dev/sda2 sym53c8xx.cmd_per_lun=4 sym53c8xx.sync=10 sym53c8xx.debug=0x200 + lilo: linux root=/dev/sda2 sym53c8xx.cmd_per_lun=4 sym53c8xx.sync=10 sym53c8xx.debug=0x200 - enable tagged commands, up to 4 tagged commands queued. - set synchronous negotiation speed to 10 Mega-transfers / second. - set DEBUG_NEGO flag. The following command will install the driver module with the same -options as above. +options as above:: modprobe sym53c8xx cmd_per_lun=4 sync=10 debug=0x200 10.2 Available arguments +------------------------ 10.2.1 Default number of tagged commands - cmd_per_lun=0 (or cmd_per_lun=1) tagged command queuing disabled - cmd_per_lun=#tags (#tags > 1) tagged command queuing enabled +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + - cmd_per_lun=0 (or cmd_per_lun=1) tagged command queuing disabled + - cmd_per_lun=#tags (#tags > 1) tagged command queuing enabled + #tags will be truncated to the max queued commands configuration parameter. 10.2.2 Burst max +^^^^^^^^^^^^^^^^ + + ========== ====================================================== burst=0 burst disabled burst=255 get burst length from initial IO register settings. burst=#x burst enabled (1<<#x burst transfers max) - #x is an integer value which is log base 2 of the burst transfers max. + + #x is an integer value which is log base 2 of the burst + transfers max. + ========== ====================================================== + By default the driver uses the maximum value supported by the chip. 10.2.3 LED support +^^^^^^^^^^^^^^^^^^ + + ===== =================== led=1 enable LED support led=0 disable LED support + ===== =================== + Do not enable LED support if your scsi board does not use SDMS BIOS. (See 'Configuration parameters') 10.2.4 Differential mode - diff=0 never set up diff mode +^^^^^^^^^^^^^^^^^^^^^^^^ + + ====== ================================= + diff=0 never set up diff mode diff=1 set up diff mode if BIOS set it diff=2 always set up diff mode diff=3 set diff mode if GPIO3 is not set + ====== ================================= 10.2.5 IRQ mode +^^^^^^^^^^^^^^^ + + ====== ================================================ irqm=0 always open drain irqm=1 same as initial settings (assumed BIOS settings) irqm=2 always totem pole + ====== ================================================ + +10.2.6 Check SCSI BUS +^^^^^^^^^^^^^^^^^^^^^ -10.2.6 Check SCSI BUS buschk=<option bits> Available option bits: - 0x0: No check. - 0x1: Check and do not attach the controller on error. - 0x2: Check and just warn on error. + + === ================================================ + 0x0 No check. + 0x1 Check and do not attach the controller on error. + 0x2 Check and just warn on error. + === ================================================ 10.2.7 Suggest a default SCSI id for hosts +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + ========== ========================================== hostid=255 no id suggested. - hostid=#x (0 < x < 7) x suggested for hosts SCSI id. + hostid=#x (0 < x < 7) x suggested for hosts SCSI id. + ========== ========================================== - If a host SCSI id is available from the NVRAM, the driver will ignore - any value suggested as boot option. Otherwise, if a suggested value - different from 255 has been supplied, it will use it. Otherwise, it will - try to deduce the value previously set in the hardware and use value + If a host SCSI id is available from the NVRAM, the driver will ignore + any value suggested as boot option. Otherwise, if a suggested value + different from 255 has been supplied, it will use it. Otherwise, it will + try to deduce the value previously set in the hardware and use value 7 if the hardware value is zero. 10.2.8 Verbosity level +^^^^^^^^^^^^^^^^^^^^^^^ + + ====== ======== verb=0 minimal verb=1 normal verb=2 too much + ====== ======== 10.2.9 Debug mode - debug=0 clear debug flags - debug=#x set debug flags - #x is an integer value combining the following power-of-2 values: - DEBUG_ALLOC 0x1 - DEBUG_PHASE 0x2 - DEBUG_POLL 0x4 - DEBUG_QUEUE 0x8 - DEBUG_RESULT 0x10 - DEBUG_SCATTER 0x20 - DEBUG_SCRIPT 0x40 - DEBUG_TINY 0x80 - DEBUG_TIMING 0x100 - DEBUG_NEGO 0x200 - DEBUG_TAGS 0x400 - DEBUG_FREEZE 0x800 - DEBUG_RESTART 0x1000 - - You can play safely with DEBUG_NEGO. However, some of these flags may - generate bunches of syslog messages. +^^^^^^^^^^^^^^^^^ + + ========= ==================================== + debug=0 clear debug flags + debug=#x set debug flags + + #x is an integer value combining the + following power-of-2 values: + + ============= ====== + DEBUG_ALLOC 0x1 + DEBUG_PHASE 0x2 + DEBUG_POLL 0x4 + DEBUG_QUEUE 0x8 + DEBUG_RESULT 0x10 + DEBUG_SCATTER 0x20 + DEBUG_SCRIPT 0x40 + DEBUG_TINY 0x80 + DEBUG_TIMING 0x100 + DEBUG_NEGO 0x200 + DEBUG_TAGS 0x400 + DEBUG_FREEZE 0x800 + DEBUG_RESTART 0x1000 + ============= ====== + ========= ==================================== + + You can play safely with DEBUG_NEGO. However, some of these flags may + generate bunches of syslog messages. 10.2.10 Settle delay +^^^^^^^^^^^^^^^^^^^^ + + ======== =================== settle=n delay for n seconds + ======== =================== After a bus reset, the driver will delay for n seconds before talking to any device on the bus. The default is 3 seconds and safe mode will default it to 10. 10.2.11 Serial NVRAM - NB: option not currently implemented. +^^^^^^^^^^^^^^^^^^^^ + + .. Note:: option not currently implemented. + + ======= ========================================= nvram=n do not look for serial NVRAM nvram=y test controllers for onboard serial NVRAM + ======= ========================================= + (alternate binary form) + nvram=<bits options> + + ==== ================================================================= 0x01 look for NVRAM (equivalent to nvram=y) 0x02 ignore NVRAM "Synchronous negotiation" parameters for all devices 0x04 ignore NVRAM "Wide negotiation" parameter for all devices 0x08 ignore NVRAM "Scan at boot time" parameter for all devices 0x80 also attach controllers set to OFF in the NVRAM (sym53c8xx only) + ==== ================================================================= 10.2.12 Exclude a host from being attached +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + excl=<io_address>,... Prevent host at a given io address from being attached. - For example 'excl=0xb400,0xc000' indicate to the + For example 'excl=0xb400,0xc000' indicate to the driver not to attach hosts at address 0xb400 and 0xc000. 10.3 Converting from old style options +-------------------------------------- + +Previously, the sym2 driver accepted arguments of the form:: -Previously, the sym2 driver accepted arguments of the form sym53c8xx=tags:4,sync:10,debug:0x200 As a result of the new module parameters, this is no longer available. Most of the options have remained the same, but tags has become cmd_per_lun to reflect its different purposes. The sample above would -be specified as: +be specified as:: + modprobe sym53c8xx cmd_per_lun=4 sync=10 debug=0x200 -or on the kernel boot line as: +or on the kernel boot line as:: + sym53c8xx.cmd_per_lun=4 sym53c8xx.sync=10 sym53c8xx.debug=0x200 -10.4 SCSI BUS checking boot option. +10.4 SCSI BUS checking boot option +---------------------------------- -When this option is set to a non-zero value, the driver checks SCSI lines +When this option is set to a non-zero value, the driver checks SCSI lines logic state, 100 micro-seconds after having asserted the SCSI RESET line. The driver just reads SCSI lines and checks all lines read FALSE except RESET. -Since SCSI devices shall release the BUS at most 800 nano-seconds after SCSI +Since SCSI devices shall release the BUS at most 800 nano-seconds after SCSI RESET has been asserted, any signal to TRUE may indicate a SCSI BUS problem. Unfortunately, the following common SCSI BUS problems are not detected: + - Only 1 terminator installed. - Misplaced terminators. - Bad quality terminators. -On the other hand, either bad cabling, broken devices, not conformant + +On the other hand, either bad cabling, broken devices, not conformant devices, ... may cause a SCSI signal to be wrong when te driver reads it. 15. SCSI problem troubleshooting +================================ 15.1 Problem tracking +--------------------- Most SCSI problems are due to a non conformant SCSI bus or too buggy devices. If unfortunately you have SCSI problems, you can check the @@ -607,86 +743,96 @@ hard disks. Good SCSI hard disks with a large cache gain advantage of tagged commands queuing. 15.2 Understanding hardware error reports +----------------------------------------- -When the driver detects an unexpected error condition, it may display a -message of the following pattern. +When the driver detects an unexpected error condition, it may display a +message of the following pattern:: -sym0:1: ERROR (0:48) (1-21-65) (f/95/0) @ (script 7c0:19000000). -sym0: script cmd = 19000000 -sym0: regdump: da 10 80 95 47 0f 01 07 75 01 81 21 80 01 09 00. + sym0:1: ERROR (0:48) (1-21-65) (f/95/0) @ (script 7c0:19000000). + sym0: script cmd = 19000000 + sym0: regdump: da 10 80 95 47 0f 01 07 75 01 81 21 80 01 09 00. -Some fields in such a message may help you understand the cause of the -problem, as follows: +Some fields in such a message may help you understand the cause of the +problem, as follows:: -sym0:1: ERROR (0:48) (1-21-65) (f/95/0) @ (script 7c0:19000000). -.....A.........B.C....D.E..F....G.H..I.......J.....K...L....... + sym0:1: ERROR (0:48) (1-21-65) (f/95/0) @ (script 7c0:19000000). + .....A.........B.C....D.E..F....G.H..I.......J.....K...L....... Field A : target number. - SCSI ID of the device the controller was talking with at the moment the + SCSI ID of the device the controller was talking with at the moment the error occurs. Field B : DSTAT io register (DMA STATUS) - Bit 0x40 : MDPE Master Data Parity Error + ======== ============================================================= + Bit 0x40 MDPE Master Data Parity Error Data parity error detected on the PCI BUS. - Bit 0x20 : BF Bus Fault + Bit 0x20 BF Bus Fault PCI bus fault condition detected - Bit 0x01 : IID Illegal Instruction Detected - Set by the chip when it detects an Illegal Instruction format + Bit 0x01 IID Illegal Instruction Detected + Set by the chip when it detects an Illegal Instruction format on some condition that makes an instruction illegal. - Bit 0x80 : DFE Dma Fifo Empty + Bit 0x80 DFE Dma Fifo Empty Pure status bit that does not indicate an error. - If the reported DSTAT value contains a combination of MDPE (0x40), + ======== ============================================================= + + If the reported DSTAT value contains a combination of MDPE (0x40), BF (0x20), then the cause may be likely due to a PCI BUS problem. Field C : SIST io register (SCSI Interrupt Status) - Bit 0x08 : SGE SCSI GROSS ERROR - Indicates that the chip detected a severe error condition + ======== ================================================================== + Bit 0x08 SGE SCSI GROSS ERROR + Indicates that the chip detected a severe error condition on the SCSI BUS that prevents the SCSI protocol from functioning properly. - Bit 0x04 : UDC Unexpected Disconnection - Indicates that the device released the SCSI BUS when the chip - was not expecting this to happen. A device may behave so to + Bit 0x04 UDC Unexpected Disconnection + Indicates that the device released the SCSI BUS when the chip + was not expecting this to happen. A device may behave so to indicate the SCSI initiator that an error condition not reportable using the SCSI protocol has occurred. - Bit 0x02 : RST SCSI BUS Reset - Generally SCSI targets do not reset the SCSI BUS, although any + Bit 0x02 RST SCSI BUS Reset + Generally SCSI targets do not reset the SCSI BUS, although any device on the BUS can reset it at any time. - Bit 0x01 : PAR Parity + Bit 0x01 PAR Parity SCSI parity error detected. - On a faulty SCSI BUS, any error condition among SGE (0x08), UDC (0x04) and - PAR (0x01) may be detected by the chip. If your SCSI system sometimes - encounters such error conditions, especially SCSI GROSS ERROR, then a SCSI + ======== ================================================================== + + On a faulty SCSI BUS, any error condition among SGE (0x08), UDC (0x04) and + PAR (0x01) may be detected by the chip. If your SCSI system sometimes + encounters such error conditions, especially SCSI GROSS ERROR, then a SCSI BUS problem is likely the cause of these errors. -For fields D,E,F,G and H, you may look into the sym53c8xx_defs.h file +For fields D,E,F,G and H, you may look into the sym53c8xx_defs.h file that contains some minimal comments on IO register bits. + Field D : SOCL Scsi Output Control Latch - This register reflects the state of the SCSI control lines the + This register reflects the state of the SCSI control lines the chip want to drive or compare against. Field E : SBCL Scsi Bus Control Lines Actual value of control lines on the SCSI BUS. Field F : SBDL Scsi Bus Data Lines Actual value of data lines on the SCSI BUS. Field G : SXFER SCSI Transfer - Contains the setting of the Synchronous Period for output and + Contains the setting of the Synchronous Period for output and the current Synchronous offset (offset 0 means asynchronous). Field H : SCNTL3 Scsi Control Register 3 - Contains the setting of timing values for both asynchronous and - synchronous data transfers. + Contains the setting of timing values for both asynchronous and + synchronous data transfers. Field I : SCNTL4 Scsi Control Register 4 Only meaningful for 53C1010 Ultra3 controllers. -Understanding Fields J, K, L and dumps requires to have good knowledge of +Understanding Fields J, K, L and dumps requires to have good knowledge of SCSI standards, chip cores functionnals and internal driver data structures. -You are not required to decode and understand them, unless you want to help +You are not required to decode and understand them, unless you want to help maintain the driver code. 17. Serial NVRAM (added by Richard Waltham: dormouse@farsrobt.demon.co.uk) +========================================================================== 17.1 Features +------------- Enabling serial NVRAM support enables detection of the serial NVRAM included -on Symbios and some Symbios compatible host adaptors, and Tekram boards. The -serial NVRAM is used by Symbios and Tekram to hold set up parameters for the +on Symbios and some Symbios compatible host adaptors, and Tekram boards. The +serial NVRAM is used by Symbios and Tekram to hold set up parameters for the host adaptor and its attached drives. The Symbios NVRAM also holds data on the boot order of host adaptors in a @@ -694,102 +840,122 @@ system with more than one host adaptor. This information is no longer used as it's fundamentally incompatible with the hotplug PCI model. Tekram boards using Symbios chips, DC390W/F/U, which have NVRAM are detected -and this is used to distinguish between Symbios compatible and Tekram host +and this is used to distinguish between Symbios compatible and Tekram host adaptors. This is used to disable the Symbios compatible "diff" setting -incorrectly set on Tekram boards if the CONFIG_SCSI_53C8XX_SYMBIOS_COMPAT -configuration parameter is set enabling both Symbios and Tekram boards to be +incorrectly set on Tekram boards if the CONFIG_SCSI_53C8XX_SYMBIOS_COMPAT +configuration parameter is set enabling both Symbios and Tekram boards to be used together with the Symbios cards using all their features, including "diff" support. ("led pin" support for Symbios compatible cards can remain enabled when using Tekram cards. It does nothing useful for Tekram host adaptors but does not cause problems either.) -The parameters the driver is able to get from the NVRAM depend on the +The parameters the driver is able to get from the NVRAM depend on the data format used, as follow: - Tekram format Symbios format -General and host parameters - Boot order N Y - Host SCSI ID Y Y - SCSI parity checking Y Y - Verbose boot messages N Y -SCSI devices parameters - Synchronous transfer speed Y Y - Wide 16 / Narrow Y Y - Tagged Command Queuing enabled Y Y - Disconnections enabled Y Y - Scan at boot time N Y - -In order to speed up the system boot, for each device configured without -the "scan at boot time" option, the driver forces an error on the ++-------------------------------+------------------+--------------+ +| |Tekram format |Symbios format| ++-------------------------------+------------------+--------------+ +|General and host parameters | | | ++-------------------------------+------------------+--------------+ +| * Boot order | N | Y | ++-------------------------------+------------------+--------------+ +| * Host SCSI ID | Y | Y | ++-------------------------------+------------------+--------------+ +| * SCSI parity checking | Y | Y | ++-------------------------------+------------------+--------------+ +| * Verbose boot messages | N | Y | ++-------------------------------+------------------+--------------+ +|SCSI devices parameters | ++-------------------------------+------------------+--------------+ +| * Synchronous transfer speed | Y | Y | ++-------------------------------+------------------+--------------+ +| * Wide 16 / Narrow | Y | Y | ++-------------------------------+------------------+--------------+ +| * Tagged Command Queuing | Y | Y | +| enabled | | | ++-------------------------------+------------------+--------------+ +| * Disconnections enabled | Y | Y | ++-------------------------------+------------------+--------------+ +| * Scan at boot time | N | Y | ++-------------------------------+------------------+--------------+ + + +In order to speed up the system boot, for each device configured without +the "scan at boot time" option, the driver forces an error on the first TEST UNIT READY command received for this device. 17.2 Symbios NVRAM layout +------------------------- + +typical data at NVRAM address 0x100 (53c810a NVRAM):: + + 00 00 + 64 01 + 8e 0b + + 00 30 00 00 00 00 07 00 00 00 00 00 00 00 07 04 10 04 00 00 + + 04 00 0f 00 00 10 00 50 00 00 01 00 00 62 + 04 00 03 00 00 10 00 58 00 00 01 00 00 63 + 04 00 01 00 00 10 00 48 00 00 01 00 00 61 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + + fe fe + 00 00 + 00 00 -typical data at NVRAM address 0x100 (53c810a NVRAM) ------------------------------------------------------------ -00 00 -64 01 -8e 0b - -00 30 00 00 00 00 07 00 00 00 00 00 00 00 07 04 10 04 00 00 - -04 00 0f 00 00 10 00 50 00 00 01 00 00 62 -04 00 03 00 00 10 00 58 00 00 01 00 00 63 -04 00 01 00 00 10 00 48 00 00 01 00 00 61 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 - -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 - -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 - -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 - -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 - -fe fe -00 00 -00 00 ------------------------------------------------------------ NVRAM layout details -NVRAM Address 0x000-0x0ff not used - 0x100-0x26f initialised data - 0x270-0x7ff not used +============= ================= +NVRAM Address +============= ================= +0x000-0x0ff not used +0x100-0x26f initialised data +0x270-0x7ff not used +============= ================= -general layout +general layout:: header - 6 bytes, data - 356 bytes (checksum is byte sum of this data) @@ -797,7 +963,7 @@ general layout --- total 368 bytes -data area layout +data area layout:: controller set up - 20 bytes boot configuration - 56 bytes (4x14 bytes) @@ -806,52 +972,51 @@ data area layout --- total 356 bytes ------------------------------------------------------------ -header - -00 00 - ?? start marker -64 01 - byte count (lsb/msb excludes header/trailer) -8e 0b - checksum (lsb/msb excludes header/trailer) ------------------------------------------------------------ -controller set up - -00 30 00 00 00 00 07 00 00 00 00 00 00 00 07 04 10 04 00 00 - | | | | - | | | -- host ID - | | | - | | --Removable Media Support - | | 0x00 = none - | | 0x01 = Bootable Device - | | 0x02 = All with Media - | | - | --flag bits 2 - | 0x00000001= scan order hi->low - | (default 0x00 - scan low->hi) - --flag bits 1 - 0x00000001 scam enable - 0x00000010 parity enable - 0x00000100 verbose boot msgs +header:: + + 00 00 - ?? start marker + 64 01 - byte count (lsb/msb excludes header/trailer) + 8e 0b - checksum (lsb/msb excludes header/trailer) + +controller set up:: + + 00 30 00 00 00 00 07 00 00 00 00 00 00 00 07 04 10 04 00 00 + | | | | + | | | -- host ID + | | | + | | --Removable Media Support + | | 0x00 = none + | | 0x01 = Bootable Device + | | 0x02 = All with Media + | | + | --flag bits 2 + | 0x00000001= scan order hi->low + | (default 0x00 - scan low->hi) + --flag bits 1 + 0x00000001 scam enable + 0x00000010 parity enable + 0x00000100 verbose boot msgs remaining bytes unknown - they do not appear to change in my current set up for any of the controllers. default set up is identical for 53c810a and 53c875 NVRAM (Removable Media added Symbios BIOS version 4.09) ------------------------------------------------------------ + boot configuration -boot order set by order of the devices in this table +boot order set by order of the devices in this table:: -04 00 0f 00 00 10 00 50 00 00 01 00 00 62 -- 1st controller -04 00 03 00 00 10 00 58 00 00 01 00 00 63 2nd controller -04 00 01 00 00 10 00 48 00 00 01 00 00 61 3rd controller -00 00 00 00 00 00 00 00 00 00 00 00 00 00 4th controller - | | | | | | | | - | | | | | | ---- PCI io port adr - | | | | | --0x01 init/scan at boot time - | | | | --PCI device/function number (0xdddddfff) - | | ----- ?? PCI vendor ID (lsb/msb) - ----PCI device ID (lsb/msb) + 04 00 0f 00 00 10 00 50 00 00 01 00 00 62 -- 1st controller + 04 00 03 00 00 10 00 58 00 00 01 00 00 63 2nd controller + 04 00 01 00 00 10 00 48 00 00 01 00 00 61 3rd controller + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4th controller + | | | | | | | | + | | | | | | ---- PCI io port adr + | | | | | --0x01 init/scan at boot time + | | | | --PCI device/function number (0xdddddfff) + | | ----- ?? PCI vendor ID (lsb/msb) + ----PCI device ID (lsb/msb) ?? use of this data is a guess but seems reasonable @@ -859,120 +1024,120 @@ remaining bytes unknown - they do not appear to change in my current set up default set up is identical for 53c810a and 53c875 NVRAM ------------------------------------------------------------ -device set up (up to 16 devices - includes controller) - -0f 00 08 08 64 00 0a 00 - id 0 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 - -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 -0f 00 08 08 64 00 0a 00 - id 15 - | | | | | | - | | | | ----timeout (lsb/msb) - | | | --synch period (0x?? 40 Mtrans/sec- fast 40) (probably 0x28) - | | | (0x30 20 Mtrans/sec- fast 20) - | | | (0x64 10 Mtrans/sec- fast ) - | | | (0xc8 5 Mtrans/sec) - | | | (0x00 asynchronous) - | | -- ?? max sync offset (0x08 in NVRAM on 53c810a) - | | (0x10 in NVRAM on 53c875) - | --device bus width (0x08 narrow) - | (0x10 16 bit wide) - --flag bits - 0x00000001 - disconnect enabled - 0x00000010 - scan at boot time - 0x00000100 - scan luns - 0x00001000 - queue tags enabled + +device set up (up to 16 devices - includes controller):: + + 0f 00 08 08 64 00 0a 00 - id 0 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 + 0f 00 08 08 64 00 0a 00 - id 15 + | | | | | | + | | | | ----timeout (lsb/msb) + | | | --synch period (0x?? 40 Mtrans/sec- fast 40) (probably 0x28) + | | | (0x30 20 Mtrans/sec- fast 20) + | | | (0x64 10 Mtrans/sec- fast ) + | | | (0xc8 5 Mtrans/sec) + | | | (0x00 asynchronous) + | | -- ?? max sync offset (0x08 in NVRAM on 53c810a) + | | (0x10 in NVRAM on 53c875) + | --device bus width (0x08 narrow) + | (0x10 16 bit wide) + --flag bits + 0x00000001 - disconnect enabled + 0x00000010 - scan at boot time + 0x00000100 - scan luns + 0x00001000 - queue tags enabled remaining bytes unknown - they do not appear to change in my current set up -?? use of this data is a guess but seems reasonable +?? use of this data is a guess but seems reasonable (but it could be max bus width) default set up for 53c810a NVRAM -default set up for 53c875 NVRAM - bus width - 0x10 +default set up for 53c875 NVRAM + + - bus width - 0x10 - sync offset ? - 0x10 - sync period - 0x30 ------------------------------------------------------------ -?? spare device space (32 bit bus ??) - -00 00 00 00 00 00 00 00 (19x8bytes) -. -. -00 00 00 00 00 00 00 00 -default set up is identical for 53c810a and 53c875 NVRAM ------------------------------------------------------------ -trailer +?? spare device space (32 bit bus ??):: -fe fe - ? end marker ? -00 00 -00 00 + 00 00 00 00 00 00 00 00 (19x8bytes) + . + . + 00 00 00 00 00 00 00 00 default set up is identical for 53c810a and 53c875 NVRAM ------------------------------------------------------------ +trailer:: + fe fe - ? end marker ? + 00 00 + 00 00 + +default set up is identical for 53c810a and 53c875 NVRAM 17.3 Tekram NVRAM layout +------------------------ nvram 64x16 (1024 bit) -Drive settings - -Drive ID 0-15 (addr 0x0yyyy0 = device setup, yyyy = ID) - (addr 0x0yyyy1 = 0x0000) - - x x x x x x x x x x x x x x x x - | | | | | | | | | - | | | | | | | | ----- parity check 0 - off - | | | | | | | | 1 - on - | | | | | | | | - | | | | | | | ------- sync neg 0 - off - | | | | | | | 1 - on - | | | | | | | - | | | | | | --------- disconnect 0 - off - | | | | | | 1 - on - | | | | | | - | | | | | ----------- start cmd 0 - off - | | | | | 1 - on - | | | | | - | | | | -------------- tagged cmds 0 - off - | | | | 1 - on - | | | | - | | | ---------------- wide neg 0 - off - | | | 1 - on - | | | - --------------------------- sync rate 0 - 10.0 Mtrans/sec - 1 - 8.0 - 2 - 6.6 - 3 - 5.7 - 4 - 5.0 - 5 - 4.0 - 6 - 3.0 - 7 - 2.0 - 7 - 2.0 - 8 - 20.0 - 9 - 16.7 - a - 13.9 - b - 11.9 +Drive settings:: + + Drive ID 0-15 (addr 0x0yyyy0 = device setup, yyyy = ID) + (addr 0x0yyyy1 = 0x0000) + + x x x x x x x x x x x x x x x x + | | | | | | | | | + | | | | | | | | ----- parity check 0 - off + | | | | | | | | 1 - on + | | | | | | | | + | | | | | | | ------- sync neg 0 - off + | | | | | | | 1 - on + | | | | | | | + | | | | | | --------- disconnect 0 - off + | | | | | | 1 - on + | | | | | | + | | | | | ----------- start cmd 0 - off + | | | | | 1 - on + | | | | | + | | | | -------------- tagged cmds 0 - off + | | | | 1 - on + | | | | + | | | ---------------- wide neg 0 - off + | | | 1 - on + | | | + --------------------------- sync rate 0 - 10.0 Mtrans/sec + 1 - 8.0 + 2 - 6.6 + 3 - 5.7 + 4 - 5.0 + 5 - 4.0 + 6 - 3.0 + 7 - 2.0 + 7 - 2.0 + 8 - 20.0 + 9 - 16.7 + a - 13.9 + b - 11.9 Global settings -Host flags 0 (addr 0x100000, 32) +Host flags 0 (addr 0x100000, 32):: x x x x x x x x x x x x x x x x | | | | | | | | | | | | @@ -980,7 +1145,7 @@ Host flags 0 (addr 0x100000, 32) | | | | | | | | | | | | | | | ----------------------- support for 0 - off | | | | | | | > 2 drives 1 - on - | | | | | | | + | | | | | | | | | | | | | ------------------------- support drives 0 - off | | | | | | > 1Gbytes 1 - on | | | | | | @@ -1000,10 +1165,10 @@ Host flags 0 (addr 0x100000, 32) as BIOS dev 1 - boot device 2 - all -Host flags 1 (addr 0x100001, 33) +Host flags 1 (addr 0x100001, 33):: x x x x x x x x x x x x x x x x - | | | | | | + | | | | | | | | | --------- boot delay 0 - 3 sec | | | 1 - 5 | | | 2 - 10 @@ -1018,7 +1183,7 @@ Host flags 1 (addr 0x100001, 33) 3 - 16 4 - 32 -Host flags 2 (addr 0x100010, 34) +Host flags 2 (addr 0x100010, 34):: x x x x x x x x x x x x x x x x | @@ -1031,18 +1196,14 @@ checksum = 0x1234 - (sum addr 0-63) ---------------------------------------------------------------------------- -default nvram data: - -0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 -0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 -0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 -0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 - -0x0f07 0x0400 0x0001 0x0000 0x0000 0x0000 0x0000 0x0000 -0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 -0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 -0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0xfbbc +default nvram data:: + 0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 + 0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 + 0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 + 0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 0x0037 0x0000 -=============================================================================== -End of Linux SYM-2 driver documentation file + 0x0f07 0x0400 0x0001 0x0000 0x0000 0x0000 0x0000 0x0000 + 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 + 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 + 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0xfbbc diff --git a/Documentation/scsi/tcm_qla2xxx.txt b/Documentation/scsi/tcm_qla2xxx.rst index c3a670a25e2b..91bc1fcd369e 100644 --- a/Documentation/scsi/tcm_qla2xxx.txt +++ b/Documentation/scsi/tcm_qla2xxx.rst @@ -1,22 +1,36 @@ +.. SPDX-License-Identifier: GPL-2.0 + +======================== +tcm_qla2xxx Driver Notes +======================== + tcm_qla2xxx jam_host attribute ------------------------------ There is now a new module endpoint atribute called jam_host -attribute: jam_host: boolean=0/1 +attribute:: + + jam_host: boolean=0/1 + This attribute and accompanying code is only included if the Kconfig parameter TCM_QLA2XXX_DEBUG is set to Y + By default this jammer code and functionality is disabled Use this attribute to control the discarding of SCSI commands to a selected host. + This may be useful for testing error handling and simulating slow drain and other fabric issues. Setting a boolean of 1 for the jam_host attribute for a particular host - will discard the commands for that host. +will discard the commands for that host. + Reset back to 0 to stop the jamming. -Enable host 4 to be jammed -echo 1 > /sys/kernel/config/target/qla2xxx/21:00:00:24:ff:27:8f:ae/tpgt_1/attrib/jam_host +Enable host 4 to be jammed:: + + echo 1 > /sys/kernel/config/target/qla2xxx/21:00:00:24:ff:27:8f:ae/tpgt_1/attrib/jam_host + +Disable jamming on host 4:: -Disable jamming on host 4 -echo 0 > /sys/kernel/config/target/qla2xxx/21:00:00:24:ff:27:8f:ae/tpgt_1/attrib/jam_host + echo 0 > /sys/kernel/config/target/qla2xxx/21:00:00:24:ff:27:8f:ae/tpgt_1/attrib/jam_host diff --git a/Documentation/scsi/ufs.txt b/Documentation/scsi/ufs.rst index 81842ec3e116..a920c0a5a1f6 100644 --- a/Documentation/scsi/ufs.txt +++ b/Documentation/scsi/ufs.rst @@ -1,24 +1,26 @@ - Universal Flash Storage - ======================= +.. SPDX-License-Identifier: GPL-2.0 +======================= +Universal Flash Storage +======================= -Contents --------- -1. Overview -2. UFS Architecture Overview - 2.1 Application Layer - 2.2 UFS Transport Protocol(UTP) layer - 2.3 UFS Interconnect(UIC) Layer -3. UFSHCD Overview - 3.1 UFS controller initialization - 3.2 UTP Transfer requests - 3.3 UFS error handling - 3.4 SCSI Error handling +.. Contents + + 1. Overview + 2. UFS Architecture Overview + 2.1 Application Layer + 2.2 UFS Transport Protocol(UTP) layer + 2.3 UFS Interconnect(UIC) Layer + 3. UFSHCD Overview + 3.1 UFS controller initialization + 3.2 UTP Transfer requests + 3.3 UFS error handling + 3.4 SCSI Error handling 1. Overview ------------ +=========== Universal Flash Storage(UFS) is a storage specification for flash devices. It is aimed to provide a universal storage interface for both @@ -28,19 +30,25 @@ is defined by JEDEC Solid State Technology Association. UFS is based on MIPI M-PHY physical layer standard. UFS uses MIPI M-PHY as the physical layer and MIPI Unipro as the link layer. -The main goals of UFS is to provide, +The main goals of UFS is to provide: + * Optimized performance: - For UFS version 1.0 and 1.1 the target performance is as follows, - Support for Gear1 is mandatory (rate A: 1248Mbps, rate B: 1457.6Mbps) - Support for Gear2 is optional (rate A: 2496Mbps, rate B: 2915.2Mbps) + + For UFS version 1.0 and 1.1 the target performance is as follows: + + - Support for Gear1 is mandatory (rate A: 1248Mbps, rate B: 1457.6Mbps) + - Support for Gear2 is optional (rate A: 2496Mbps, rate B: 2915.2Mbps) + Future version of the standard, - Gear3 (rate A: 4992Mbps, rate B: 5830.4Mbps) + + - Gear3 (rate A: 4992Mbps, rate B: 5830.4Mbps) + * Low power consumption * High random IOPs and low latency 2. UFS Architecture Overview ----------------------------- +============================ UFS has a layered communication architecture which is based on SCSI SAM-5 architectural model. @@ -48,16 +56,22 @@ SAM-5 architectural model. UFS communication architecture consists of following layers, 2.1 Application Layer +--------------------- The Application layer is composed of UFS command set layer(UCS), Task Manager and Device manager. The UFS interface is designed to be protocol agnostic, however SCSI has been selected as a baseline protocol for versions 1.0 and 1.1 of UFS protocol layer. + UFS supports subset of SCSI commands defined by SPC-4 and SBC-3. - * UCS: It handles SCSI commands supported by UFS specification. - * Task manager: It handles task management functions defined by the + + * UCS: + It handles SCSI commands supported by UFS specification. + * Task manager: + It handles task management functions defined by the UFS which are meant for command queue control. - * Device manager: It handles device level operations and device + * Device manager: + It handles device level operations and device configuration operations. Device level operations mainly involve device power management operations and commands to Interconnect layers. Device level configurations involve handling of query @@ -65,10 +79,12 @@ UFS communication architecture consists of following layers, information of the device. 2.2 UFS Transport Protocol(UTP) layer +------------------------------------- UTP layer provides services for the higher layers through Service Access Points. UTP defines 3 service access points for higher layers. + * UDM_SAP: Device manager service access point is exposed to device manager for device level operations. These device level operations are done through query requests. @@ -76,20 +92,23 @@ UFS communication architecture consists of following layers, set layer(UCS) to transport commands. * UTP_TM_SAP: Task management service access point is exposed to task manager to transport task management functions. + UTP transports messages through UFS protocol information unit(UPIU). 2.3 UFS Interconnect(UIC) Layer +------------------------------- UIC is the lowest layer of UFS layered architecture. It handles connection between UFS host and UFS device. UIC consists of MIPI UniPro and MIPI M-PHY. UIC provides 2 service access points to upper layer, + * UIC_SAP: To transport UPIU between UFS host and UFS device. * UIO_SAP: To issue commands to Unipro layers. 3. UFSHCD Overview ------------------- +================== The UFS host controller driver is based on Linux SCSI Framework. UFSHCD is a low level device driver which acts as an interface between @@ -98,12 +117,14 @@ SCSI Midlayer and PCIe based UFS host controllers. The current UFSHCD implementation supports following functionality, 3.1 UFS controller initialization +--------------------------------- The initialization module brings UFS host controller to active state and prepares the controller to transfer commands/response between UFSHCD and UFS device. 3.2 UTP Transfer requests +------------------------- Transfer request handling module of UFSHCD receives SCSI commands from SCSI Midlayer, forms UPIUs and issues the UPIUs to UFS Host @@ -112,11 +133,13 @@ The current UFSHCD implementation supports following functionality, of the status of the command. 3.3 UFS error handling +---------------------- Error handling module handles Host controller fatal errors, Device fatal errors and UIC interconnect layer related errors. 3.4 SCSI Error handling +----------------------- This is done through UFSHCD SCSI error handling routines registered with SCSI Midlayer. Examples of some of the error handling commands @@ -129,7 +152,7 @@ In this version of UFSHCD Query requests and power management functionality are not implemented. 4. BSG Support ------------------- +============== This transport driver supports exchanging UFS protocol information units (UPIUs) with a UFS device. Typically, user space will allocate @@ -138,7 +161,7 @@ request_upiu and reply_upiu respectively. Filling those UPIUs should be done in accordance with JEDEC spec UFS2.1 paragraph 10.7. *Caveat emptor*: The driver makes no further input validations and sends the UPIU to the device as it is. Open the bsg device in /dev/ufs-bsg and -send SG_IO with the applicable sg_io_v4: +send SG_IO with the applicable sg_io_v4:: io_hdr_v4.guard = 'Q'; io_hdr_v4.protocol = BSG_PROTOCOL_SCSI; @@ -166,6 +189,7 @@ upiu-based protocol is available at: For more detailed information about the tool and its supported features, please see the tool's README. -UFS Specifications can be found at, -UFS - http://www.jedec.org/sites/default/files/docs/JESD220.pdf -UFSHCI - http://www.jedec.org/sites/default/files/docs/JESD223.pdf +UFS Specifications can be found at: + +- UFS - http://www.jedec.org/sites/default/files/docs/JESD220.pdf +- UFSHCI - http://www.jedec.org/sites/default/files/docs/JESD223.pdf diff --git a/Documentation/scsi/wd719x.rst b/Documentation/scsi/wd719x.rst new file mode 100644 index 000000000000..a35015dfedd9 --- /dev/null +++ b/Documentation/scsi/wd719x.rst @@ -0,0 +1,24 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=============================================================== +Driver for Western Digital WD7193, WD7197 and WD7296 SCSI cards +=============================================================== + +The card requires firmware that can be cut out of the Windows NT driver that +can be downloaded from WD at: +http://support.wdc.com/product/download.asp?groupid=801&sid=27&lang=en + +There is no license anywhere in the file or on the page - so the firmware +probably cannot be added to linux-firmware. + +This script downloads and extracts the firmware, creating wd719x-risc.bin and +d719x-wcs.bin files. Put them in /lib/firmware/:: + + #!/bin/sh + wget http://support.wdc.com/download/archive/pciscsi.exe + lha xi pciscsi.exe pci-scsi.exe + lha xi pci-scsi.exe nt/wd7296a.sys + rm pci-scsi.exe + dd if=wd7296a.sys of=wd719x-risc.bin bs=1 skip=5760 count=14336 + dd if=wd7296a.sys of=wd719x-wcs.bin bs=1 skip=20096 count=514 + rm wd7296a.sys diff --git a/Documentation/scsi/wd719x.txt b/Documentation/scsi/wd719x.txt deleted file mode 100644 index 0816b0220238..000000000000 --- a/Documentation/scsi/wd719x.txt +++ /dev/null @@ -1,21 +0,0 @@ -Driver for Western Digital WD7193, WD7197 and WD7296 SCSI cards ---------------------------------------------------------------- - -The card requires firmware that can be cut out of the Windows NT driver that -can be downloaded from WD at: -http://support.wdc.com/product/download.asp?groupid=801&sid=27&lang=en - -There is no license anywhere in the file or on the page - so the firmware -probably cannot be added to linux-firmware. - -This script downloads and extracts the firmware, creating wd719x-risc.bin and -d719x-wcs.bin files. Put them in /lib/firmware/. - -#!/bin/sh -wget http://support.wdc.com/download/archive/pciscsi.exe -lha xi pciscsi.exe pci-scsi.exe -lha xi pci-scsi.exe nt/wd7296a.sys -rm pci-scsi.exe -dd if=wd7296a.sys of=wd719x-risc.bin bs=1 skip=5760 count=14336 -dd if=wd7296a.sys of=wd719x-wcs.bin bs=1 skip=20096 count=514 -rm wd7296a.sys diff --git a/Documentation/sound/alsa-configuration.rst b/Documentation/sound/alsa-configuration.rst index 392875a1b94e..72f97d4b01a7 100644 --- a/Documentation/sound/alsa-configuration.rst +++ b/Documentation/sound/alsa-configuration.rst @@ -2234,6 +2234,19 @@ use_vmalloc buffers. If mmap is used on such architectures, turn off this option, so that the DMA-coherent buffers are allocated and used instead. +delayed_register + The option is needed for devices that have multiple streams + defined in multiple USB interfaces. The driver may invoke + registrations multiple times (once per interface) and this may + lead to the insufficient device enumeration. + This option receives an array of strings, and you can pass + ID:INTERFACE like ``0123abcd:4`` for performing the delayed + registration to the given device. In this example, when a USB + device 0123:abcd is probed, the driver waits the registration + until the USB interface 4 gets probed. + The driver prints a message like "Found post-registration device + assignment: 1234abcd:04" for such a device, so that user can + notice the need. This module supports multiple devices, autoprobe and hotplugging. diff --git a/Documentation/sound/hd-audio/index.rst b/Documentation/sound/hd-audio/index.rst index f8a72ffffe66..6e12de9fc34e 100644 --- a/Documentation/sound/hd-audio/index.rst +++ b/Documentation/sound/hd-audio/index.rst @@ -8,3 +8,4 @@ HD-Audio models controls dp-mst + realtek-pc-beep diff --git a/Documentation/sound/hd-audio/models.rst b/Documentation/sound/hd-audio/models.rst index 11298f0ce44d..0ea967d34583 100644 --- a/Documentation/sound/hd-audio/models.rst +++ b/Documentation/sound/hd-audio/models.rst @@ -216,8 +216,6 @@ alc298-dell-aio ALC298 fixups on Dell AIO machines alc275-dell-xps ALC275 fixups on Dell XPS models -alc256-dell-xps13 - ALC256 fixups on Dell XPS13 lenovo-spk-noise Workaround for speaker noise on Lenovo machines lenovo-hotkey diff --git a/Documentation/sound/hd-audio/realtek-pc-beep.rst b/Documentation/sound/hd-audio/realtek-pc-beep.rst new file mode 100644 index 000000000000..be47c6f76a6e --- /dev/null +++ b/Documentation/sound/hd-audio/realtek-pc-beep.rst @@ -0,0 +1,129 @@ +=============================== +Realtek PC Beep Hidden Register +=============================== + +This file documents the "PC Beep Hidden Register", which is present in certain +Realtek HDA codecs and controls a muxer and pair of passthrough mixers that can +route audio between pins but aren't themselves exposed as HDA widgets. As far +as I can tell, these hidden routes are designed to allow flexible PC Beep output +for codecs that don't have mixer widgets in their output paths. Why it's easier +to hide a mixer behind an undocumented vendor register than to just expose it +as a widget, I have no idea. + +Register Description +==================== + +The register is accessed via processing coefficient 0x36 on NID 20h. Bits not +identified below have no discernible effect on my machine, a Dell XPS 13 9350:: + + MSB LSB + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | |h|S|L| | B |R| | Known bits + +=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+ + |0|0|1|1| 0x7 |0|0x0|1| 0x7 | Reset value + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + +1Ah input select (B): 2 bits + When zero, expose the PC Beep line (from the internal beep generator, when + enabled with the Set Beep Generation verb on NID 01h, or else from the + external PCBEEP pin) on the 1Ah pin node. When nonzero, expose the headphone + jack (or possibly Line In on some machines) input instead. If PC Beep is + selected, the 1Ah boost control has no effect. + +Amplify 1Ah loopback, left (L): 1 bit + Amplify the left channel of 1Ah before mixing it into outputs as specified + by h and S bits. Does not affect the level of 1Ah exposed to other widgets. + +Amplify 1Ah loopback, right (R): 1 bit + Amplify the right channel of 1Ah before mixing it into outputs as specified + by h and S bits. Does not affect the level of 1Ah exposed to other widgets. + +Loopback 1Ah to 21h [active low] (h): 1 bit + When zero, mix 1Ah (possibly with amplification, depending on L and R bits) + into 21h (headphone jack on my machine). Mixed signal respects the mute + setting on 21h. + +Loopback 1Ah to 14h (S): 1 bit + When one, mix 1Ah (possibly with amplification, depending on L and R bits) + into 14h (internal speaker on my machine). Mixed signal **ignores** the mute + setting on 14h and is present whenever 14h is configured as an output. + +Path diagrams +============= + +1Ah input selection (DIV is the PC Beep divider set on NID 01h):: + + <Beep generator> <PCBEEP pin> <Headphone jack> + | | | + +--DIV--+--!DIV--+ {1Ah boost control} + | | + +--(b == 0)--+--(b != 0)--+ + | + >1Ah (Beep/Headphone Mic/Line In)< + +Loopback of 1Ah to 21h/14h:: + + <1Ah (Beep/Headphone Mic/Line In)> + | + {amplify if L/R} + | + +-----!h-----+-----S-----+ + | | + {21h mute control} | + | | + >21h (Headphone)< >14h (Internal Speaker)< + +Background +========== + +All Realtek HDA codecs have a vendor-defined widget with node ID 20h which +provides access to a bank of registers that control various codec functions. +Registers are read and written via the standard HDA processing coefficient +verbs (Set/Get Coefficient Index, Set/Get Processing Coefficient). The node is +named "Realtek Vendor Registers" in public datasheets' verb listings and, +apart from that, is entirely undocumented. + +This particular register, exposed at coefficient 0x36 and named in commits from +Realtek, is of note: unlike most registers, which seem to control detailed +amplifier parameters not in scope of the HDA specification, it controls audio +routing which could just as easily have been defined using standard HDA mixer +and selector widgets. + +Specifically, it selects between two sources for the input pin widget with Node +ID (NID) 1Ah: the widget's signal can come either from an audio jack (on my +laptop, a Dell XPS 13 9350, it's the headphone jack, but comments in Realtek +commits indicate that it might be a Line In on some machines) or from the PC +Beep line (which is itself multiplexed between the codec's internal beep +generator and external PCBEEP pin, depending on if the beep generator is +enabled via verbs on NID 01h). Additionally, it can mix (with optional +amplification) that signal onto the 21h and/or 14h output pins. + +The register's reset value is 0x3717, corresponding to PC Beep on 1Ah that is +then amplified and mixed into both the headphones and the speakers. Not only +does this violate the HDA specification, which says that "[a vendor defined +beep input pin] connection may be maintained *only* while the Link reset +(**RST#**) is asserted", it means that we cannot ignore the register if we care +about the input that 1Ah would otherwise expose or if the PCBEEP trace is +poorly shielded and picks up chassis noise (both of which are the case on my +machine). + +Unfortunately, there are lots of ways to get this register configuration wrong. +Linux, it seems, has gone through most of them. For one, the register resets +after S3 suspend: judging by existing code, this isn't the case for all vendor +registers, and it's led to some fixes that improve behavior on cold boot but +don't last after suspend. Other fixes have successfully switched the 1Ah input +away from PC Beep but have failed to disable both loopback paths. On my +machine, this means that the headphone input is amplified and looped back to +the headphone output, which uses the exact same pins! As you might expect, this +causes terrible headphone noise, the character of which is controlled by the +1Ah boost control. (If you've seen instructions online to fix XPS 13 headphone +noise by changing "Headphone Mic Boost" in ALSA, now you know why.) + +The information here has been obtained through black-box reverse engineering of +the ALC256 codec's behavior and is not guaranteed to be correct. It likely +also applies for the ALC255, ALC257, ALC235, and ALC236, since those codecs +seem to be close relatives of the ALC256. (They all share one initialization +function.) Additionally, other codecs like the ALC225 and ALC285 also have this +register, judging by existing fixups in ``patch_realtek.c``, but specific +data (e.g. node IDs, bit positions, pin mappings) for those codecs may differ +from what I've described here. diff --git a/Documentation/sound/soc/codec-to-codec.rst b/Documentation/sound/soc/codec-to-codec.rst index 810109d7500d..4eaa9a0c41fc 100644 --- a/Documentation/sound/soc/codec-to-codec.rst +++ b/Documentation/sound/soc/codec-to-codec.rst @@ -104,5 +104,10 @@ Make sure to name your corresponding cpu and codec playback and capture dai names ending with "Playback" and "Capture" respectively as dapm core will link and power those dais based on the name. -Note that in current device tree there is no way to mark a dai_link -as codec to codec. However, it may change in future. +A dai_link in a "simple-audio-card" will automatically be detected as +codec to codec when all DAIs on the link belong to codec components. +The dai_link will be initialized with the subset of stream parameters +(channels, format, sample rate) supported by all DAIs on the link. Since +there is no way to provide these parameters in the device tree, this is +mostly useful for communication with simple fixed-function codecs, such +as a Bluetooth controller or cellular modem. diff --git a/Documentation/trace/coresight/coresight-ect.rst b/Documentation/trace/coresight/coresight-ect.rst new file mode 100644 index 000000000000..ecc1e57012ef --- /dev/null +++ b/Documentation/trace/coresight/coresight-ect.rst @@ -0,0 +1,222 @@ +.. SPDX-License-Identifier: GPL-2.0 +============================================= +CoreSight Embedded Cross Trigger (CTI & CTM). +============================================= + + :Author: Mike Leach <mike.leach@linaro.org> + :Date: November 2019 + +Hardware Description +-------------------- + +The CoreSight Cross Trigger Interface (CTI) is a hardware device that takes +individual input and output hardware signals known as triggers to and from +devices and interconnects them via the Cross Trigger Matrix (CTM) to other +devices via numbered channels, in order to propagate events between devices. + +e.g.:: + + 0000000 in_trigs ::::::: + 0 C 0----------->: : +======>(other CTI channel IO) + 0 P 0<-----------: : v + 0 U 0 out_trigs : : Channels ***** ::::::: + 0000000 : CTI :<=========>*CTM*<====>: CTI :---+ + ####### in_trigs : : (id 0-3) ***** ::::::: v + # ETM #----------->: : ^ ####### + # #<-----------: : +---# ETR # + ####### out_trigs ::::::: ####### + +The CTI driver enables the programming of the CTI to attach triggers to +channels. When an input trigger becomes active, the attached channel will +become active. Any output trigger attached to that channel will also +become active. The active channel is propagated to other CTIs via the CTM, +activating connected output triggers there, unless filtered by the CTI +channel gate. + +It is also possible to activate a channel using system software directly +programming registers in the CTI. + +The CTIs are registered by the system to be associated with CPUs and/or other +CoreSight devices on the trace data path. When these devices are enabled the +attached CTIs will also be enabled. By default/on power up the CTIs have +no programmed trigger/channel attachments, so will not affect the system +until explicitly programmed. + +The hardware trigger connections between CTIs and devices is implementation +defined, unless the CPU/ETM combination is a v8 architecture, in which case +the connections have an architecturally defined standard layout. + +The hardware trigger signals can also be connected to non-CoreSight devices +(e.g. UART), or be propagated off chip as hardware IO lines. + +All the CTI devices are associated with a CTM. On many systems there will be a +single effective CTM (one CTM, or multiple CTMs all interconnected), but it is +possible that systems can have nets of CTIs+CTM that are not interconnected by +a CTM to each other. On these systems a CTM index is declared to associate +CTI devices that are interconnected via a given CTM. + +Sysfs files and directories +--------------------------- + +The CTI devices appear on the existing CoreSight bus alongside the other +CoreSight devices:: + + >$ ls /sys/bus/coresight/devices + cti_cpu0 cti_cpu2 cti_sys0 etm0 etm2 funnel0 replicator0 tmc_etr0 + cti_cpu1 cti_cpu3 cti_sys1 etm1 etm3 funnel1 tmc_etf0 tpiu0 + +The ``cti_cpu<N>`` named CTIs are associated with a CPU, and any ETM used by +that core. The ``cti_sys<N>`` CTIs are general system infrastructure CTIs that +can be associated with other CoreSight devices, or other system hardware +capable of generating or using trigger signals.:: + + >$ ls /sys/bus/coresight/devices/etm0/cti_cpu0 + channels ctmid enable nr_trigger_cons mgmt power powered regs + subsystem triggers0 triggers1 uevent + +*Key file items are:-* + * ``enable``: enables/disables the CTI. Read to determine current state. + If this shows as enabled (1), but ``powered`` shows unpowered (0), then + the enable indicates a request to enabled when the device is powered. + * ``ctmid`` : associated CTM - only relevant if system has multiple CTI+CTM + clusters that are not interconnected. + * ``nr_trigger_cons`` : total connections - triggers<N> directories. + * ``powered`` : Read to determine if the CTI is currently powered. + +*Sub-directories:-* + * ``triggers<N>``: contains list of triggers for an individual connection. + * ``channels``: Contains the channel API - CTI main programming interface. + * ``regs``: Gives access to the raw programmable CTI regs. + * ``mgmt``: the standard CoreSight management registers. + + +triggers<N> directories +~~~~~~~~~~~~~~~~~~~~~~~ + +Individual trigger connection information. This describes trigger signals for +CoreSight and non-CoreSight connections. + +Each triggers directory has a set of parameters describing the triggers for +the connection. + + * ``name`` : name of connection + * ``in_signals`` : input trigger signal indexes used in this connection. + * ``in_types`` : functional types for in signals. + * ``out_signals`` : output trigger signals for this connection. + * ``out_types`` : functional types for out signals. + +e.g:: + + >$ ls ./cti_cpu0/triggers0/ + in_signals in_types name out_signals out_types + >$ cat ./cti_cpu0/triggers0/name + cpu0 + >$ cat ./cti_cpu0/triggers0/out_signals + 0-2 + >$ cat ./cti_cpu0/triggers0/out_types + pe_edbgreq pe_dbgrestart pe_ctiirq + >$ cat ./cti_cpu0/triggers0/in_signals + 0-1 + >$ cat ./cti_cpu0/triggers0/in_types + pe_dbgtrigger pe_pmuirq + +If a connection has zero signals in either the 'in' or 'out' triggers then +those parameters will be omitted. + +Channels API Directory +~~~~~~~~~~~~~~~~~~~~~~ + +This provides an easy way to attach triggers to channels, without needing +the multiple register operations that are required if manipulating the +'regs' sub-directory elements directly. + +A number of files provide this API:: + + >$ ls ./cti_sys0/channels/ + chan_clear chan_inuse chan_xtrigs_out trigin_attach + chan_free chan_pulse chan_xtrigs_reset trigin_detach + chan_gate_disable chan_set chan_xtrigs_sel trigout_attach + chan_gate_enable chan_xtrigs_in trig_filter_enable trigout_detach + trigout_filtered + +Most access to these elements take the form:: + + echo <chan> [<trigger>] > /<device_path>/<operation> + +where the optional <trigger> is only needed for trigXX_attach | detach +operations. + +e.g.:: + + >$ echo 0 1 > ./cti_sys0/channels/trigout_attach + >$ echo 0 > ./cti_sys0/channels/chan_set + +Attaches trigout(1) to channel(0), then activates channel(0) generating a +set state on cti_sys0.trigout(1) + + +*API operations* + + * ``trigin_attach, trigout_attach``: Attach a channel to a trigger signal. + * ``trigin_detach, trigout_detach``: Detach a channel from a trigger signal. + * ``chan_set``: Set the channel - the set state will be propagated around + the CTM to other connected devices. + * ``chan_clear``: Clear the channel. + * ``chan_pulse``: Set the channel for a single CoreSight clock cycle. + * ``chan_gate_enable``: Write operation sets the CTI gate to propagate + (enable) the channel to other devices. This operation takes a channel + number. CTI gate is enabled for all channels by default at power up. Read + to list the currently enabled channels on the gate. + * ``chan_gate_disable``: Write channel number to disable gate for that + channel. + * ``chan_inuse``: Show the current channels attached to any signal + * ``chan_free``: Show channels with no attached signals. + * ``chan_xtrigs_sel``: write a channel number to select a channel to view, + read to show the selected channel number. + * ``chan_xtrigs_in``: Read to show the input triggers attached to + the selected view channel. + * ``chan_xtrigs_out``:Read to show the output triggers attached to + the selected view channel. + * ``trig_filter_enable``: Defaults to enabled, disable to allow potentially + dangerous output signals to be set. + * ``trigout_filtered``: Trigger out signals that are prevented from being + set if filtering ``trig_filter_enable`` is enabled. One use is to prevent + accidental ``EDBGREQ`` signals stopping a core. + * ``chan_xtrigs_reset``: Write 1 to clear all channel / trigger programming. + Resets device hardware to default state. + + +The example below attaches input trigger index 1 to channel 2, and output +trigger index 6 to the same channel. It then examines the state of the +channel / trigger connections using the appropriate sysfs attributes. + +The settings mean that if either input trigger 1, or channel 2 go active then +trigger out 6 will go active. We then enable the CTI, and use the software +channel control to activate channel 2. We see the active channel on the +``choutstatus`` register and the active signal on the ``trigoutstatus`` +register. Finally clearing the channel removes this. + +e.g.:: + + .../cti_sys0/channels# echo 2 1 > trigin_attach + .../cti_sys0/channels# echo 2 6 > trigout_attach + .../cti_sys0/channels# cat chan_free + 0-1,3 + .../cti_sys0/channels# cat chan_inuse + 2 + .../cti_sys0/channels# echo 2 > chan_xtrigs_sel + .../cti_sys0/channels# cat chan_xtrigs_trigin + 1 + .../cti_sys0/channels# cat chan_xtrigs_trigout + 6 + .../cti_sys0/# echo 1 > enable + .../cti_sys0/channels# echo 2 > chan_set + .../cti_sys0/channels# cat ../regs/choutstatus + 0x4 + .../cti_sys0/channels# cat ../regs/trigoutstatus + 0x40 + .../cti_sys0/channels# echo 2 > chan_clear + .../cti_sys0/channels# cat ../regs/trigoutstatus + 0x0 + .../cti_sys0/channels# cat ../regs/choutstatus + 0x0 diff --git a/Documentation/trace/coresight/coresight.rst b/Documentation/trace/coresight/coresight.rst index a566719f8e7e..108600ee1e12 100644 --- a/Documentation/trace/coresight/coresight.rst +++ b/Documentation/trace/coresight/coresight.rst @@ -491,8 +491,21 @@ interface provided for that purpose by the generic STM API:: Details on how to use the generic STM API can be found here:- :doc:`../stm` [#second]_. +The CTI & CTM Modules +--------------------- + +The CTI (Cross Trigger Interface) provides a set of trigger signals between +individual CTIs and components, and can propagate these between all CTIs via +channels on the CTM (Cross Trigger Matrix). + +A separate documentation file is provided to explain the use of these devices. +(:doc:`coresight-ect`) [#fourth]_. + + .. [#first] Documentation/ABI/testing/sysfs-bus-coresight-devices-stm .. [#second] Documentation/trace/stm.rst .. [#third] https://github.com/Linaro/perf-opencsd + +.. [#fourth] Documentation/trace/coresight/coresight-ect.rst diff --git a/Documentation/trace/ftrace.rst b/Documentation/trace/ftrace.rst index ff658e27d25b..3b5614b1d1a5 100644 --- a/Documentation/trace/ftrace.rst +++ b/Documentation/trace/ftrace.rst @@ -125,10 +125,13 @@ of ftrace. Here is a list of some of the key files: trace: This file holds the output of the trace in a human - readable format (described below). Note, tracing is temporarily - disabled when the file is open for reading. Once all readers - are closed, tracing is re-enabled. Opening this file for + readable format (described below). Opening this file for writing with the O_TRUNC flag clears the ring buffer content. + Note, this file is not a consumer. If tracing is off + (no tracer running, or tracing_on is zero), it will produce + the same output each time it is read. When tracing is on, + it may produce inconsistent results as it tries to read + the entire buffer without consuming it. trace_pipe: @@ -142,9 +145,7 @@ of ftrace. Here is a list of some of the key files: will not be read again with a sequential read. The "trace" file is static, and if the tracer is not adding more data, it will display the same - information every time it is read. Unlike the - "trace" file, opening this file for reading will not - temporarily disable tracing. + information every time it is read. trace_options: @@ -262,6 +263,20 @@ of ftrace. Here is a list of some of the key files: traced by the function tracer as well. This option will also cause PIDs of tasks that exit to be removed from the file. + set_ftrace_notrace_pid: + + Have the function tracer ignore threads whose PID are listed in + this file. + + If the "function-fork" option is set, then when a task whose + PID is listed in this file forks, the child's PID will + automatically be added to this file, and the child will not be + traced by the function tracer as well. This option will also + cause PIDs of tasks that exit to be removed from the file. + + If a PID is in both this file and "set_ftrace_pid", then this + file takes precedence, and the thread will not be traced. + set_event_pid: Have the events only trace a task with a PID listed in this file. @@ -273,6 +288,19 @@ of ftrace. Here is a list of some of the key files: cause the PIDs of tasks to be removed from this file when the task exits. + set_event_notrace_pid: + + Have the events not trace a task with a PID listed in this file. + Note, sched_switch and sched_wakeup will trace threads not listed + in this file, even if a thread's PID is in the file if the + sched_switch or sched_wakeup events also trace a thread that should + be traced. + + To have the PIDs of children of tasks with their PID in this file + added on fork, enable the "event-fork" option. That option will also + cause the PIDs of tasks to be removed from this file when the task + exits. + set_graph_function: Functions listed in this file will cause the function graph @@ -1125,6 +1153,12 @@ Here are the available options: the trace displays additional information about the latency, as described in "Latency trace format". + pause-on-trace + When set, opening the trace file for read, will pause + writing to the ring buffer (as if tracing_on was set to zero). + This simulates the original behavior of the trace file. + When the file is closed, tracing will be enabled again. + record-cmd When any event or tracer is enabled, a hook is enabled in the sched_switch trace point to fill comm cache @@ -1176,6 +1210,8 @@ Here are the available options: tasks fork. Also, when tasks with PIDs in set_event_pid exit, their PIDs will be removed from the file. + This affects PIDs listed in set_event_notrace_pid as well. + function-trace The latency tracers will enable function tracing if this option is enabled (default it is). When @@ -1190,6 +1226,8 @@ Here are the available options: set_ftrace_pid exit, their PIDs will be removed from the file. + This affects PIDs in set_ftrace_notrace_pid as well. + display-graph When set, the latency tracers (irqsoff, wakeup, etc) will use function graph tracing instead of function tracing. @@ -2126,6 +2164,8 @@ periodically make a CPU constantly busy with interrupts disabled. # cat trace # tracer: hwlat # + # entries-in-buffer/entries-written: 13/13 #P:8 + # # _-----=> irqs-off # / _----=> need-resched # | / _---=> hardirq/softirq @@ -2133,12 +2173,18 @@ periodically make a CPU constantly busy with interrupts disabled. # ||| / delay # TASK-PID CPU# |||| TIMESTAMP FUNCTION # | | | |||| | | - <...>-3638 [001] d... 19452.055471: #1 inner/outer(us): 12/14 ts:1499801089.066141940 - <...>-3638 [003] d... 19454.071354: #2 inner/outer(us): 11/9 ts:1499801091.082164365 - <...>-3638 [002] dn.. 19461.126852: #3 inner/outer(us): 12/9 ts:1499801098.138150062 - <...>-3638 [001] d... 19488.340960: #4 inner/outer(us): 8/12 ts:1499801125.354139633 - <...>-3638 [003] d... 19494.388553: #5 inner/outer(us): 8/12 ts:1499801131.402150961 - <...>-3638 [003] d... 19501.283419: #6 inner/outer(us): 0/12 ts:1499801138.297435289 nmi-total:4 nmi-count:1 + <...>-1729 [001] d... 678.473449: #1 inner/outer(us): 11/12 ts:1581527483.343962693 count:6 + <...>-1729 [004] d... 689.556542: #2 inner/outer(us): 16/9 ts:1581527494.889008092 count:1 + <...>-1729 [005] d... 714.756290: #3 inner/outer(us): 16/16 ts:1581527519.678961629 count:5 + <...>-1729 [001] d... 718.788247: #4 inner/outer(us): 9/17 ts:1581527523.889012713 count:1 + <...>-1729 [002] d... 719.796341: #5 inner/outer(us): 13/9 ts:1581527524.912872606 count:1 + <...>-1729 [006] d... 844.787091: #6 inner/outer(us): 9/12 ts:1581527649.889048502 count:2 + <...>-1729 [003] d... 849.827033: #7 inner/outer(us): 18/9 ts:1581527654.889013793 count:1 + <...>-1729 [007] d... 853.859002: #8 inner/outer(us): 9/12 ts:1581527658.889065736 count:1 + <...>-1729 [001] d... 855.874978: #9 inner/outer(us): 9/11 ts:1581527660.861991877 count:1 + <...>-1729 [001] d... 863.938932: #10 inner/outer(us): 9/11 ts:1581527668.970010500 count:1 nmi-total:7 nmi-count:1 + <...>-1729 [007] d... 878.050780: #11 inner/outer(us): 9/12 ts:1581527683.385002600 count:1 nmi-total:5 nmi-count:1 + <...>-1729 [007] d... 886.114702: #12 inner/outer(us): 9/12 ts:1581527691.385001600 count:1 The above output is somewhat the same in the header. All events will have @@ -2148,7 +2194,7 @@ interrupts disabled 'd'. Under the FUNCTION title there is: This is the count of events recorded that were greater than the tracing_threshold (See below). - inner/outer(us): 12/14 + inner/outer(us): 11/11 This shows two numbers as "inner latency" and "outer latency". The test runs in a loop checking a timestamp twice. The latency detected within @@ -2156,11 +2202,15 @@ interrupts disabled 'd'. Under the FUNCTION title there is: after the previous timestamp and the next timestamp in the loop is the "outer latency". - ts:1499801089.066141940 + ts:1581527483.343962693 + + The absolute timestamp that the first latency was recorded in the window. + + count:6 - The absolute timestamp that the event happened. + The number of times a latency was detected during the window. - nmi-total:4 nmi-count:1 + nmi-total:7 nmi-count:1 On architectures that support it, if an NMI comes in during the test, the time spent in NMI is reported in "nmi-total" (in diff --git a/Documentation/virt/kvm/index.rst b/Documentation/virt/kvm/index.rst index dcc252634cf9..b6833c7bb474 100644 --- a/Documentation/virt/kvm/index.rst +++ b/Documentation/virt/kvm/index.rst @@ -28,3 +28,5 @@ KVM arm/index devices/index + + running-nested-guests diff --git a/Documentation/virt/kvm/running-nested-guests.rst b/Documentation/virt/kvm/running-nested-guests.rst new file mode 100644 index 000000000000..d0a1fc754c84 --- /dev/null +++ b/Documentation/virt/kvm/running-nested-guests.rst @@ -0,0 +1,276 @@ +============================== +Running nested guests with KVM +============================== + +A nested guest is the ability to run a guest inside another guest (it +can be KVM-based or a different hypervisor). The straightforward +example is a KVM guest that in turn runs on a KVM guest (the rest of +this document is built on this example):: + + .----------------. .----------------. + | | | | + | L2 | | L2 | + | (Nested Guest) | | (Nested Guest) | + | | | | + |----------------'--'----------------| + | | + | L1 (Guest Hypervisor) | + | KVM (/dev/kvm) | + | | + .------------------------------------------------------. + | L0 (Host Hypervisor) | + | KVM (/dev/kvm) | + |------------------------------------------------------| + | Hardware (with virtualization extensions) | + '------------------------------------------------------' + +Terminology: + +- L0 – level-0; the bare metal host, running KVM + +- L1 – level-1 guest; a VM running on L0; also called the "guest + hypervisor", as it itself is capable of running KVM. + +- L2 – level-2 guest; a VM running on L1, this is the "nested guest" + +.. note:: The above diagram is modelled after the x86 architecture; + s390x, ppc64 and other architectures are likely to have + a different design for nesting. + + For example, s390x always has an LPAR (LogicalPARtition) + hypervisor running on bare metal, adding another layer and + resulting in at least four levels in a nested setup — L0 (bare + metal, running the LPAR hypervisor), L1 (host hypervisor), L2 + (guest hypervisor), L3 (nested guest). + + This document will stick with the three-level terminology (L0, + L1, and L2) for all architectures; and will largely focus on + x86. + + +Use Cases +--------- + +There are several scenarios where nested KVM can be useful, to name a +few: + +- As a developer, you want to test your software on different operating + systems (OSes). Instead of renting multiple VMs from a Cloud + Provider, using nested KVM lets you rent a large enough "guest + hypervisor" (level-1 guest). This in turn allows you to create + multiple nested guests (level-2 guests), running different OSes, on + which you can develop and test your software. + +- Live migration of "guest hypervisors" and their nested guests, for + load balancing, disaster recovery, etc. + +- VM image creation tools (e.g. ``virt-install``, etc) often run + their own VM, and users expect these to work inside a VM. + +- Some OSes use virtualization internally for security (e.g. to let + applications run safely in isolation). + + +Enabling "nested" (x86) +----------------------- + +From Linux kernel v4.19 onwards, the ``nested`` KVM parameter is enabled +by default for Intel and AMD. (Though your Linux distribution might +override this default.) + +In case you are running a Linux kernel older than v4.19, to enable +nesting, set the ``nested`` KVM module parameter to ``Y`` or ``1``. To +persist this setting across reboots, you can add it in a config file, as +shown below: + +1. On the bare metal host (L0), list the kernel modules and ensure that + the KVM modules:: + + $ lsmod | grep -i kvm + kvm_intel 133627 0 + kvm 435079 1 kvm_intel + +2. Show information for ``kvm_intel`` module:: + + $ modinfo kvm_intel | grep -i nested + parm: nested:bool + +3. For the nested KVM configuration to persist across reboots, place the + below in ``/etc/modprobed/kvm_intel.conf`` (create the file if it + doesn't exist):: + + $ cat /etc/modprobe.d/kvm_intel.conf + options kvm-intel nested=y + +4. Unload and re-load the KVM Intel module:: + + $ sudo rmmod kvm-intel + $ sudo modprobe kvm-intel + +5. Verify if the ``nested`` parameter for KVM is enabled:: + + $ cat /sys/module/kvm_intel/parameters/nested + Y + +For AMD hosts, the process is the same as above, except that the module +name is ``kvm-amd``. + + +Additional nested-related kernel parameters (x86) +------------------------------------------------- + +If your hardware is sufficiently advanced (Intel Haswell processor or +higher, which has newer hardware virt extensions), the following +additional features will also be enabled by default: "Shadow VMCS +(Virtual Machine Control Structure)", APIC Virtualization on your bare +metal host (L0). Parameters for Intel hosts:: + + $ cat /sys/module/kvm_intel/parameters/enable_shadow_vmcs + Y + + $ cat /sys/module/kvm_intel/parameters/enable_apicv + Y + + $ cat /sys/module/kvm_intel/parameters/ept + Y + +.. note:: If you suspect your L2 (i.e. nested guest) is running slower, + ensure the above are enabled (particularly + ``enable_shadow_vmcs`` and ``ept``). + + +Starting a nested guest (x86) +----------------------------- + +Once your bare metal host (L0) is configured for nesting, you should be +able to start an L1 guest with:: + + $ qemu-kvm -cpu host [...] + +The above will pass through the host CPU's capabilities as-is to the +gues); or for better live migration compatibility, use a named CPU +model supported by QEMU. e.g.:: + + $ qemu-kvm -cpu Haswell-noTSX-IBRS,vmx=on + +then the guest hypervisor will subsequently be capable of running a +nested guest with accelerated KVM. + + +Enabling "nested" (s390x) +------------------------- + +1. On the host hypervisor (L0), enable the ``nested`` parameter on + s390x:: + + $ rmmod kvm + $ modprobe kvm nested=1 + +.. note:: On s390x, the kernel parameter ``hpage`` is mutually exclusive + with the ``nested`` paramter — i.e. to be able to enable + ``nested``, the ``hpage`` parameter *must* be disabled. + +2. The guest hypervisor (L1) must be provided with the ``sie`` CPU + feature — with QEMU, this can be done by using "host passthrough" + (via the command-line ``-cpu host``). + +3. Now the KVM module can be loaded in the L1 (guest hypervisor):: + + $ modprobe kvm + + +Live migration with nested KVM +------------------------------ + +Migrating an L1 guest, with a *live* nested guest in it, to another +bare metal host, works as of Linux kernel 5.3 and QEMU 4.2.0 for +Intel x86 systems, and even on older versions for s390x. + +On AMD systems, once an L1 guest has started an L2 guest, the L1 guest +should no longer be migrated or saved (refer to QEMU documentation on +"savevm"/"loadvm") until the L2 guest shuts down. Attempting to migrate +or save-and-load an L1 guest while an L2 guest is running will result in +undefined behavior. You might see a ``kernel BUG!`` entry in ``dmesg``, a +kernel 'oops', or an outright kernel panic. Such a migrated or loaded L1 +guest can no longer be considered stable or secure, and must be restarted. +Migrating an L1 guest merely configured to support nesting, while not +actually running L2 guests, is expected to function normally even on AMD +systems but may fail once guests are started. + +Migrating an L2 guest is always expected to succeed, so all the following +scenarios should work even on AMD systems: + +- Migrating a nested guest (L2) to another L1 guest on the *same* bare + metal host. + +- Migrating a nested guest (L2) to another L1 guest on a *different* + bare metal host. + +- Migrating a nested guest (L2) to a bare metal host. + +Reporting bugs from nested setups +----------------------------------- + +Debugging "nested" problems can involve sifting through log files across +L0, L1 and L2; this can result in tedious back-n-forth between the bug +reporter and the bug fixer. + +- Mention that you are in a "nested" setup. If you are running any kind + of "nesting" at all, say so. Unfortunately, this needs to be called + out because when reporting bugs, people tend to forget to even + *mention* that they're using nested virtualization. + +- Ensure you are actually running KVM on KVM. Sometimes people do not + have KVM enabled for their guest hypervisor (L1), which results in + them running with pure emulation or what QEMU calls it as "TCG", but + they think they're running nested KVM. Thus confusing "nested Virt" + (which could also mean, QEMU on KVM) with "nested KVM" (KVM on KVM). + +Information to collect (generic) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The following is not an exhaustive list, but a very good starting point: + + - Kernel, libvirt, and QEMU version from L0 + + - Kernel, libvirt and QEMU version from L1 + + - QEMU command-line of L1 -- when using libvirt, you'll find it here: + ``/var/log/libvirt/qemu/instance.log`` + + - QEMU command-line of L2 -- as above, when using libvirt, get the + complete libvirt-generated QEMU command-line + + - ``cat /sys/cpuinfo`` from L0 + + - ``cat /sys/cpuinfo`` from L1 + + - ``lscpu`` from L0 + + - ``lscpu`` from L1 + + - Full ``dmesg`` output from L0 + + - Full ``dmesg`` output from L1 + +x86-specific info to collect +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Both the below commands, ``x86info`` and ``dmidecode``, should be +available on most Linux distributions with the same name: + + - Output of: ``x86info -a`` from L0 + + - Output of: ``x86info -a`` from L1 + + - Output of: ``dmidecode`` from L0 + + - Output of: ``dmidecode`` from L1 + +s390x-specific info to collect +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Along with the earlier mentioned generic details, the below is +also recommended: + + - ``/proc/sysinfo`` from L1; this will also include the info from L0 diff --git a/Documentation/vm/.gitignore b/Documentation/vm/.gitignore index 09b164a5700f..bc74f5643008 100644 --- a/Documentation/vm/.gitignore +++ b/Documentation/vm/.gitignore @@ -1,2 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only page-types slabinfo diff --git a/Documentation/vm/free_page_reporting.rst b/Documentation/vm/free_page_reporting.rst new file mode 100644 index 000000000000..8c05e62d8b2b --- /dev/null +++ b/Documentation/vm/free_page_reporting.rst @@ -0,0 +1,40 @@ +.. _free_page_reporting: + +===================== +Free Page Reporting +===================== + +Free page reporting is an API by which a device can register to receive +lists of pages that are currently unused by the system. This is useful in +the case of virtualization where a guest is then able to use this data to +notify the hypervisor that it is no longer using certain pages in memory. + +For the driver, typically a balloon driver, to use of this functionality +it will allocate and initialize a page_reporting_dev_info structure. The +field within the structure it will populate is the "report" function +pointer used to process the scatterlist. It must also guarantee that it can +handle at least PAGE_REPORTING_CAPACITY worth of scatterlist entries per +call to the function. A call to page_reporting_register will register the +page reporting interface with the reporting framework assuming no other +page reporting devices are already registered. + +Once registered the page reporting API will begin reporting batches of +pages to the driver. The API will start reporting pages 2 seconds after +the interface is registered and will continue to do so 2 seconds after any +page of a sufficiently high order is freed. + +Pages reported will be stored in the scatterlist passed to the reporting +function with the final entry having the end bit set in entry nent - 1. +While pages are being processed by the report function they will not be +accessible to the allocator. Once the report function has been completed +the pages will be returned to the free area from which they were obtained. + +Prior to removing a driver that is making use of free page reporting it +is necessary to call page_reporting_unregister to have the +page_reporting_dev_info structure that is currently in use by free page +reporting removed. Doing this will prevent further reports from being +issued via the interface. If another driver or the same driver is +registered it is possible for it to resume where the previous driver had +left off in terms of reporting free pages. + +Alexander Duyck, Dec 04, 2019 diff --git a/Documentation/vm/zswap.rst b/Documentation/vm/zswap.rst index 61f6185188cd..f8c6a79d7c70 100644 --- a/Documentation/vm/zswap.rst +++ b/Documentation/vm/zswap.rst @@ -35,9 +35,11 @@ Zswap evicts pages from compressed cache on an LRU basis to the backing swap device when the compressed pool reaches its size limit. This requirement had been identified in prior community discussions. -Zswap is disabled by default but can be enabled at boot time by setting -the ``enabled`` attribute to 1 at boot time. ie: ``zswap.enabled=1``. Zswap -can also be enabled and disabled at runtime using the sysfs interface. +Whether Zswap is enabled at the boot time depends on whether +the ``CONFIG_ZSWAP_DEFAULT_ON`` Kconfig option is enabled or not. +This setting can then be overridden by providing the kernel command line +``zswap.enabled=`` option, for example ``zswap.enabled=0``. +Zswap can also be enabled and disabled at runtime using the sysfs interface. An example command to enable zswap at runtime, assuming sysfs is mounted at ``/sys``, is:: @@ -64,9 +66,10 @@ allocation in zpool is not directly accessible by address. Rather, a handle is returned by the allocation routine and that handle must be mapped before being accessed. The compressed memory pool grows on demand and shrinks as compressed pages are freed. The pool is not preallocated. By default, a zpool -of type zbud is created, but it can be selected at boot time by -setting the ``zpool`` attribute, e.g. ``zswap.zpool=zbud``. It can -also be changed at runtime using the sysfs ``zpool`` attribute, e.g.:: +of type selected in ``CONFIG_ZSWAP_ZPOOL_DEFAULT`` Kconfig option is created, +but it can be overridden at boot time by setting the ``zpool`` attribute, +e.g. ``zswap.zpool=zbud``. It can also be changed at runtime using the sysfs +``zpool`` attribute, e.g.:: echo zbud > /sys/module/zswap/parameters/zpool @@ -97,8 +100,9 @@ controlled policy: * max_pool_percent - The maximum percentage of memory that the compressed pool can occupy. -The default compressor is lzo, but it can be selected at boot time by -setting the ``compressor`` attribute, e.g. ``zswap.compressor=lzo``. +The default compressor is selected in ``CONFIG_ZSWAP_COMPRESSOR_DEFAULT`` +Kconfig option, but it can be overridden at boot time by setting the +``compressor`` attribute, e.g. ``zswap.compressor=lzo``. It can also be changed at runtime using the sysfs "compressor" attribute, e.g.:: diff --git a/Documentation/x86/boot.rst b/Documentation/x86/boot.rst index fa7ddc0428c8..5325c71ca877 100644 --- a/Documentation/x86/boot.rst +++ b/Documentation/x86/boot.rst @@ -1399,8 +1399,8 @@ must have read/write permission; CS must be __BOOT_CS and DS, ES, SS must be __BOOT_DS; interrupt must be disabled; %rsi must hold the base address of the struct boot_params. -EFI Handover Protocol -===================== +EFI Handover Protocol (deprecated) +================================== This protocol allows boot loaders to defer initialisation to the EFI boot stub. The boot loader is required to load the kernel/initrd(s) @@ -1408,6 +1408,12 @@ from the boot media and jump to the EFI handover protocol entry point which is hdr->handover_offset bytes from the beginning of startup_{32,64}. +The boot loader MUST respect the kernel's PE/COFF metadata when it comes +to section alignment, the memory footprint of the executable image beyond +the size of the file itself, and any other aspect of the PE/COFF header +that may affect correct operation of the image as a PE/COFF binary in the +execution context provided by the EFI firmware. + The function prototype for the handover entry point looks like this:: efi_main(void *handle, efi_system_table_t *table, struct boot_params *bp) @@ -1419,9 +1425,18 @@ UEFI specification. 'bp' is the boot loader-allocated boot params. The boot loader *must* fill out the following fields in bp:: - - hdr.code32_start - hdr.cmd_line_ptr - hdr.ramdisk_image (if applicable) - hdr.ramdisk_size (if applicable) All other fields should be zero. + +NOTE: The EFI Handover Protocol is deprecated in favour of the ordinary PE/COFF + entry point, combined with the LINUX_EFI_INITRD_MEDIA_GUID based initrd + loading protocol (refer to [0] for an example of the bootloader side of + this), which removes the need for any knowledge on the part of the EFI + bootloader regarding the internal representation of boot_params or any + requirements/limitations regarding the placement of the command line + and ramdisk in memory, or the placement of the kernel image itself. + +[0] https://github.com/u-boot/u-boot/commit/ec80b4735a593961fe701cc3a5d717d4739b0fd0 |