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authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>2017-06-21 15:29:12 +0200
committerMarc Zyngier <marc.zyngier@arm.com>2017-06-22 14:15:00 +0100
commit11f69da0dada3e4472b5b1319fae9b1df194e3d6 (patch)
tree9c4620a9d1cd92ee12a5623e08a0b48ec823999a /Documentation
parenta1628366227aff3433f646cec2beb36d1f018f86 (diff)
downloadlinux-11f69da0dada3e4472b5b1319fae9b1df194e3d6.tar.bz2
dt-bindings/interrupt-controller: Add DT binding for the Marvell GICP
This commit adds the Device Tree binding documentation for the Marvell GICP, an extension to the GIC that allows to trigger GIC SPI interrupts using memory transactions. It is used by the ICU unit in the Marvell CP110 block to turn wired interrupts inside the CP into SPI interrupts at the GIC level in the AP. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt27
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diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt
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+Marvell GICP Controller
+-----------------------
+
+GICP is a Marvell extension of the GIC that allows to trigger GIC SPI
+interrupts by doing a memory transaction. It is used by the ICU
+located in the Marvell CP110 to turn wired interrupts inside the CP
+into GIC SPI interrupts.
+
+Required properties:
+
+- compatible: Must be "marvell,ap806-gicp"
+
+- reg: Must be the address and size of the GICP SPI registers
+
+- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
+ for this GICP
+
+- msi-controller: indicates that this is an MSI controller
+
+Example:
+
+gicp_spi: gicp-spi@3f0040 {
+ compatible = "marvell,ap806-gicp";
+ reg = <0x3f0040 0x10>;
+ marvell,spi-ranges = <64 64>, <288 64>;
+ msi-controller;
+};